 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| preliminary this document contains information on a product under development at advanced micro devices. the information is intended to help you evaluate this product. amd reserves the right to change or discontinue work on this proposed product without notice. publication# 22929 rev: c amendment/ 0 issue date: august 2000 refer to amd?s website (www.amd.com) for the latest information. am79c976 pcnet-pro? 10/100 mbps pci ethernet controller distinctive characteristics integrated fast ethernet controller for the peripheral component interconnect (pci) bus ? 32-bit glueless pci host interface ? supports pci clock frequency from dc to 33 mhz independent of network clock ? supports network operation with pci clock from 15 mhz to 33 mhz ? high performance bus mastering architecture with integrated direct memory access (dma) buffer management unit for low cpu and bus utilization ? pci specification revision 2.2 compliant ? supports pci subsystem/subvendor id/vendor id programming through the eeprom interface ? supports both pci 3.3-v and 5.0-v signaling environments ? plug and play compatible ? uses advanced pci commands (mwi, mrl, mrm) ? optionally supports pci bursts aligned to cache line boundaries ? supports big endian and little endian byte alignments ? implements optional pci power management event (pme ) pin ? supports 40-bit addressing (using pci dual address cycles) media independent interface (mii) for connecting external 10/100 megabit per second (mbps) transceivers ? ieee 802.3-compliant mii ? intelligent auto-poll ? external phy status monitor and interrupt ? supports both auto-negotiable and non auto- negotiable external phys ? supports 10base-t, 100base-tx/fx, 100base-t4, and 100base-t2 ieee 802.3- compliant mii phys at full- or half-duplex full-duplex operation supported with independent transmit (tx) and receive (rx) channels includes support for ieee 802.1q vlans ? automatically inserts, deletes, or modifies vlan tag ? optionally filters untagged frames provides optional flow control features ? recognizes and transmits ieee 802.3x mac flow control frames ? asserts collision-based back pressure in half-duplex mode provides internal management information base (mib) counters for network statistics supports pc97, pc98, pc99, and net pc requirements ? implements full onnow features including pattern matching and link status wake-up ? implements magic packet ? mode ? magic packet mode and the physical address loaded from eeprom at power up without requiring pci clock ? supports pci bus power management interface specification version 1.1 ? supports advanced configuration and power interface (acpi) specification version 1.0 ? supports network device class power management specification version 1.0 large independent external tx and rx fifos ? supports up to 4 megabytes (mbytes) external ssram for rx and tx frame storage ? programmable fifo watermarks for both transmit and receive operations ? receive frame queuing for high latency pci bus host operation ? programmable allocation of buffer space between transmit and receive queues
2 am79c976 8/01/00 preliminary dual-speed csma/cd (10 mbps and 100 mbps) media access controller (mac) compliant with ieee/ansi 802.3 and blue book ethernet standards programmable internal/external loopback capabilities supports patented external address detection interface (eadi) with receive frame tagging support for internetworking applications eeprom interface supports jumperless design and provides through-chip programming ? supports full programmability of all internal registers through eeprom mapping programmable phy reset output pin capable of resetting external phy without needing buffering integrated oscillator circuit is controlled by external crystal extensive programmable led status support supports up to 16 mbyte optional boot prom or flash for diskless node application look-ahead packet processing (lapp) data handling technique reduces system overhead by allowing protocol analysis to begin before the end of a receive frame optional delayed interrupt feature reduces cpu overhead programmable inter packet gap (ipg) to address less aggressive network mac controllers offers the modified back-off algorithm to address the ethernet capture effect optionally sends and receives non-standard frames of up to 64k octets in length ieee 1149.1-compliant jtag boundary scan test access port interface for board-level production connectivity test provides built-in self test (mbist) for the external ssram software compatible with amd pcnet family and lance/c-lance register and descriptor architecture compatible with the existing pcnet family driver and diagnostic software (except for statistics) available in 208-pin pqfp package +3.3-v power supply with 5-v tolerant i/os enables broad system compatibility support for operation in industrial temperature range (-40 c to +85 c) available. 8/01/00 am79c976 3 preliminary general description the am79c976 controller is a highly-integrated 32-bit full-duplex, 10/100-megabit per second (mbps) ether- net controller solution, designed to address high- performance system application requirements. it is a flexible bus mastering device that can be used in any application, including network-ready pcs and bridge/ router designs. the bus master architecture provides high data throughput and low cpu and system bus uti- lization. the am79c976 controller is fabricated with advanced low-power 3.3-v cmos process to provide low operating current for power sensitive applications. the am79c976 controller also has several enhance- ments over its predecessor, the am79c971 pcnet- fast device. in addition to providing access to a larger ssram, it further reduces system implemen- tation cost by the addition of a new eeprom program- mable pin (phy_rst) and the integration of the pal function needed for magic packet application. the phy_rst pin is implemented to reset the external phy without increasing the load to the pci bus and to block rst to the phy when pg input is low. the 32-bit multiplexed bus interface unit provides a di- rect interface to the pci local bus, simplifying the de- sign of an ethernet node in a pc system. the am79c976 controller provides the complete interface to an expansion rom or flash device allowing add-on card designs with only a single load per pci bus inter- face pin. with its built-in support for both little and big endian byte alignment, this controller also addresses non-pc applications. the am79c976 controller?s advanced cmos design allows the bus interface to be connected to either a +5-v or a +3.3-v signaling envi- ronment. an ieee 1149.1-compliant jtag test inter- face for board-level testing is also provided. the am79c976 controller is also compliant with the pc97, pc98, pc99, and network pc (net pc) specifi- cations. it includes the full implementation of the mi- crosoft onnow and acpi specifications, which are backward compatible with the magic packet technol- ogy, and it is compliant with the pci bus power man- agement interface specification by supporting the four power management states (d0, d1, d2, and d3), the optional pme pin, and the necessary configuration and data registers. the am79c976 controller is ideally suited for net pc, motherboard, network interface card (nic), and em- bedded designs. it is available in a 208-pin plastic quad flat pack (pqfp) package. the am79c976 controller contains a bus interface unit, a dma buffer management unit, an iso/iec 8802-3 (ieee 802.3)-compliant media access controller (mac), and an ieee 802.3-compliant mii. an interface to an external ram of up to 4 mbytes is provided for frame storage. the mii supports ieee 802.3-compliant full-duplex and half-duplex operations at 10 mbps or 100 mbps. the mii tx and rx clock signals can be stopped independently for home networking applica- tions. the am79c976 controller is register compatible with the lance? (am7990) and c-lance? (am79c90) ethernet controllers, and all ethernet controllers in the pcnet family except ilacc? (am79c900), including the pcnet?-isa controller (am79c960), pcnet?-isa+ (am79c961), pcnet?-isa ii (am79c961a), pcnet?-32 (am79c965), pcnet?- pci (am79c970), pcnet?-pci ii (am79c970a), and the pcnet?-fast (am79c971). the buffer management unit supports the lance and pcnet descriptor software models. the am79c976 controller supports auto-configuration in the pci configuration space. additional am79c976 controller configuration parameters, including the unique ieee physical address, can be read from an ex- ternal nonvolatile memory (eeprom) immediately fol- lowing system reset. in addition, the device provides programmable on-chip led drivers for transmit, receive, collision, link integrity, magic packet status, activity, address match, full- duplex, or 100 mbps status. the am79c976 controller also provides an eadi to allow external hardware ad- dress filtering in internetworking applications and a receive frame tagging feature. with the rise of embedded networking applications op- erating in harsh environments where temperatures may exceed the normal commercial temperature (0 c to +70 c) window, an industrial temperature (-40 c to +85 c) version is available. this industrial temperature version of the pcnet-pro ethernet controller is char- acterized across the industrial temperature range (-40 c to +85 c) within the published power supply specifi- cation (4.75v to 5.25v; 5% vcc). thus, conformance of the pcnet-pro performance over this temperature range is guaranteed by a design and characterization monitor. 4 am79c976 8/01/00 preliminary block diagram clk rst ad[31:0] c/be[3:0] par frame trdy irdy stop idsel devsel req gnt perr serr inta pci bus interface unit 93cxx eeprom interface expansion bus interface mib counters jtag port control onnow power management unit 802.3 mac core mii port eadi port eradv/floe eradsp/icen erclk erd[31:0]/fld[7:0]/fla[23.20] era[19:0]/fla[19:0] erce eroe erwe flcs pme rwu wumi pg phy_rst txd[3:0] tx_en tx_clk col rxd[3:0] rx_er rx_clk rx_dv crs sfbd ear rxfrtgd rxfrtge eecs eesk eedi eedo led0 led1 led2 led3 network port manager mdc mdio memory control unit register control and status unit descriptor management unit led control vaux_sense clock generator xtal1 xtal2 xclk clksel0 clksel1 clksel2 fc tck tms tdi tdo test 22929b1 8/01/00 am79c976 5 preliminary distinctive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 list of figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 standard products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 connection diagram (pqr208) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 pin designations (pqr208) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 listed by pin number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 listed by group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 pci interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 board interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 eeprom interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 external memory interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 media independent interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 external address detection interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 ieee 1149.1 (1990) test access port interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 power supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 basic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 system bus interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 software interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 network interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 detailed functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 slave bus interface unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 slave configuration transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 slave i/o transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 expansion rom transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 slave cycle termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 disconnect when busy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 disconnect of burst transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 8 parity error response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 master bus interface unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 bus acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 bus master dma transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 basic non-burst read transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 basic burst read transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 basic non-burst write transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 basic burst write transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 dma burst alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 target initiated termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 disconnect with data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 disconnect without data transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 target abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 master initiated termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 preemption during non-burst transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 preemption during burst transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 master abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 parity error response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 initialization block dma transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 descriptor dma transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 fifo dma transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 descriptor management unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table of contents 6 am79c976 8/01/00 preliminary re-initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 run and suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 descriptor management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 descriptor rings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 transmit polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 receive polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 look ahead packet processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 software interrupt timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 media access control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 transmit and receive message data encapsulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 framing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 destination address handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 media access management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 medium allocation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 signal quality error (sqe) test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 collision handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 transmit operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 transmit function programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 automatic pad generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 transmit fcs generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 transmit error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 loss of carrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 late collision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 transmit fifo underflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 receive operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 receive function programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 address matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 automatic pad stripping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 receive fcs checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 receive exception conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 statistics counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 receive statistics counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 transmit statistics counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 vlan support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 vlan frame size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 admit only vlan frames option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 vlan tags in descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 loopback operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 miscellaneous loopback features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 full-duplex operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 full-duplex link status led support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 media independent interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 mii transmit interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 mii receive interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 mii network status interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 mii management interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 mii management frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 host cpu access to external phy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 auto-poll state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 network port manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 auto-negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 auto-negotiation with multiple phy devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 operation without mmi management interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 regulating network traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 mac control pause frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 back pressure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 8/01/00 am79c976 7 preliminary enabling traffic regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 hardware control of traffic regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 software control of traffic regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 programming the pause length register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 pause frame reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 delayed interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 external address detection interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 external address detection interface: receive frame tagging . . . . . . . . . . . . . . . . . . . . . . . . . . 91 external memory interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 expansion rom - boot device access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 direct flash access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 flash/eprom read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 sram configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 eeprom interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 automatic eeprom read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 eeprom auto-detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 direct access to the interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 eeprom crc calculation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 led support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 power savings mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 power management support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 onnow wake-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 rwu wake-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 link change detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 magic packet mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 onnow pattern match mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 pattern match ram (pmr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 ieee 1149.1 (1990) test access port interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 03 boundary scan circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 tap finite state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 supported instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 boundary scan register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 other data registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 h_reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 ee_reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 s_reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 stop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 power on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 external phy reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 software access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 pci configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 i/o resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 address prom space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 reset register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 word i/o mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 double word i/o mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 8 user accessible registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 pci configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 pci vendor id register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 pci device id register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 pci command register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 pci status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 pci revision id register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 pci programming interface register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 pci sub-class register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 pci base-class register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 8 am79c976 8/01/00 preliminary pci cache line size register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 pci latency timer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 pci header type register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 pci i/o base address register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 pci memory mapped i/o base address register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 pci subsystem vendor id register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 pci subsystem id register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 pci expansion rom base address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 pci capabilities pointer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 pci interrupt line register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 pci interrupt pin register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 pci min_gnt register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 pci max_lat register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 pci capability identifier register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 pci next item pointer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 pci power management capabilities register (pmc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 pci power management control/status register (pmcsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 pci pmcsr bridge support extensions register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 pci data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 memory-mapped registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 mib offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 ap_value0: auto-poll value0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 ap_value1: auto-poll value1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 ap_value2: auto-poll value2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 ap_value3: auto-poll value3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 ap_value4: auto-poll value4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 ap_value5: auto-poll value5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 autopoll0: auto-poll0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 autopoll1: auto-poll1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 autopoll2: auto-poll2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 autopoll3: auto-poll3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 autopoll4: auto-poll4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7 autopoll5: auto-poll5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8 badr: receive ring base address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 badx: transmit ring base address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 chipid: chip id register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 chpolltime: chain poll timer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 cmd0: command0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 cmd2: command2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 cmd3: command3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 cmd7: command7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 ctrl0: control0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 ctrl1: control1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 ctrl2: control2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 ctrl3: control3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 datambist: memory built-in self-test access register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 delayed_int: delayed interrupts register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 eeprom_acc: eeprom access register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 flash_addr: flash address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 flash_data: flash data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 flow: flow control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 ifs1: inter-frame spacing part 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 int0: interrupt0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 inten0: interrupt0 enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 ipg: inter-packet gap register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157 ladrf: logical address filter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 led0 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 led1 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 8/01/00 am79c976 9 preliminary led2 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 led3 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 max_lat_a: pci maximum latency alias register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 min_gnt_a: pci minimum grant alias register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 padr: physical address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 60 pause count register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 pcidata0: pci data register zero alias register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 pcidata1: pci data register one alias register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 pcidata2: pci data register two alias register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 pcidata3: pci data register three alias register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 pcidata4: pci data register four alias register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 pcidata5: pci data register five alias register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 pcidata6: pci data register six alias register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 pcidata7: pci data register seven alias register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 phy access register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 pmat0: onnow pattern register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 pmat1: onnow pattern register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 pmc_a: pci power management capabilities alias register . . . . . . . . . . . . . . . . . . . . . . . . . . 165 receive protect register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 rcv_ring_len: receive ring length register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 rom_cfg: rom base address configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 sid_a: pci subsystem id alias register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 sram boundary register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167 sram size register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 stat0: status0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 software timer value register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169 svid_a: pci subsystem vendor id alias register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 vid_a: pci vendor id alias register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1 xmt_ring_len: transmit ring length register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 xmtpolltime: transmit poll timer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 rap register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 rap: register address port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 csr0: am79c976 controller status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 csr1: initialization block address 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 csr2: initialization block address 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 csr3: interrupt masks and deferral control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 csr4: test and features control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 csr5: extended control and interrupt 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 csr6: reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 csr7: extended control and interrupt 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 csr8: logical address filter 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184 csr9: logical address filter 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184 csr10: logical address filter 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184 csr11: logical address filter 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184 csr12: physical address register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 csr13: physical address register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 csr14: physical address register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 csr15: mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 csr16-23: reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 csr24: base address of receive ring lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 csr25: base address of receive ring upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 csr26-29: reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 csr30: base address of transmit ring lower. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 csr31: base address of transmit ring upper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 csr32-46: reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 csr47: transmit polling interval. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188 csr48: reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 10 am79c976 8/01/00 preliminary csr49: chain polling interval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 csr50-57: reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 csr58: software style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 csr59-75: reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 csr76: receive ring length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 csr77: reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 csr78: transmit ring length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191 csr79: reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 csr80: dma transfer counter and fifo threshold control . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 csr81-87: reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 csr88: chip id register lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 csr89: chip id register upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 csr90-99: reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 csr100: bus timeout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 csr101-111: reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 csr112: missed frame count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 93 csr113: reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 csr114: receive collision count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 93 csr115: reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 csr116: onnow power mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 csr117-121: reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 csr122: advanced feature control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 csr123: reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 csr124: test register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 csr125: mac enhanced configuration control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 bus configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 bcr0: master mode read active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8 bcr1: master mode write active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 98 bcr2: miscellaneous configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9 bcr4: led0 status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 bcr5: led1 status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 bcr6: led2 status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 bcr7: led3 status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 bcr9: full-duplex control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 bcr16: i/o base address lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7 bcr17: i/o base address upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8 bcr18: burst and bus control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 bcr19: eeprom control and status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 bcr20: software style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 bcr22: pci latency register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214 bcr23: pci subsystem vendor id register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 bcr24: pci subsystem id register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 bcr25: sram size register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 bcr26: sram boundary register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 bcr27: sram interface control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 bcr28: expansion bus port address lower (used for flash/eprom and sram accesses). . 216 bcr29: expansion port address upper (used for flash/eprom accesses) . . . . . . . . . . . . . . 216 bcr30: expansion bus data port register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 bcr31: software timer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 17 bcr32: mii control and status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 bcr33: mii address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219 bcr34: mii management data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 bcr35: pci vendor id register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 bcr36: pci power management capabilities (pmc) alias register . . . . . . . . . . . . . . . . . . . . . 220 bcr37: pci data register zero (data0) alias register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 bcr38: pci data register one (data1) alias register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 bcr39: pci data register two (data2) alias register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 bcr40: pci data register three (data3) alias register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 8/01/00 am79c976 11 preliminary bcr41: pci data register four (data4) alias register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 bcr42: pci data register five (data5) alias register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 bcr43: pci data register six (data6) alias register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 bcr44: pci data register seven (data7) alias register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 bcr45: onnow pattern matching register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 bcr46: onnow pattern matching register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 bcr47: onnow pattern matching register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 initialization block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 rlen and tlen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 rdra and tdra . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 ladrf. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 padr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 receive descriptors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 transmit descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 pci configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 memory-mapped registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 bus configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 register bit cross reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 register programming summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 programmable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 dc characteristics over commercial operating ranges . . . . . . . . . . . . . . . . . . . . . . . 267 switching characteristics: bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 key to switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 switching test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 switching waveforms: system bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 switching characteristics: eeprom interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 switching characteristics: jtag timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 switching characteristics: media independent interface . . . . . . . . . . . . . . . . . . . . . . 278 switching characteristics: external address detection interface . . . . . . . . . . . 281 switching waveforms: receive frame tag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 switching waveforms: external memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 physical dimensions* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 pqfp208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 plastic quad flat pack trimmed and formed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 appendix a: look-ahead packet processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-1 outline of lapp flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-2 setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-2 flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-2 lapp software requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-5 lapp rules for parsing descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-5 some examples of lapp descriptor interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-6 buffer size tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-7 an alternative lapp flow: two-interrupt method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-8 appendix b: mii management registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-1 control register (register 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-1 status register (register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-2 auto-negotiation advertisement register (register 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-3 technology ability field bit assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-3 auto-negotiation link partner ability register (register 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-4 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . index-1 12 am79c976 7/25/00 preliminary list of figures figure 1: slave configuration read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 2: slave configuration write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 3: slave read using i/o command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 4: slave write using memory command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 5: disconnect of slave cycle when busy . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 6: disconnect of slave burst transfer - no host wait states . . . . . . . . . . . . 38 figure 7: disconnect of slave burst transfer - host inserts wait states . . . . . . . . . 39 figure 8: address parity error response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 9: slave cycle data parity error response . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 10: bus acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 11: non-burst read transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 12: burst read transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 13: non-burst write transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 14: burst write transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 15: disconnect with data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 16: disconnect without data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 17: target abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 18: preemption during non-burst transaction . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 19: preemption during burst transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 20: master abor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 21: master cycle data parity error response . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 22: descriptor ring read in non-burst mode . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 23: descriptor ring read in burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 24: descriptor ring write in non-burst mode . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 25: descriptor ring write in burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 26: fifo burst write at start of unaligned buffer . . . . . . . . . . . . . . . . . . . . . 58 figure 27: fifo burst write at end of unaligned buffer . . . . . . . . . . . . . . . . . . . . . . 59 figure 28: 16-bit software model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 29: 32-bit software model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 30: iso 8802-3 (ieee/ansi 802.3) data frame . . . . . . . . . . . . . . . . . . . . . . . 70 figure 31: ieee 802.3 frame and length field transmission order . . . . . . . . . . . . . 73 figure 32: vlan-tagged frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 33: media independent interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 34: frame format at the mii interface connection . . . . . . . . . . . . . . . . . . . . . 83 figure 35: mii receive frame tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 36: external ssram and flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 37: expansion rom bus read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 38: flash read from expansion bus data port . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 39: flash write sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 40: eeprom data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 41: eeprom entry positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 42: crc flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 43: led control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 44: onnow functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 45: pattern match ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 figure 46: pci expansion rom base address register . . . . . . . . . . . . . . . . . . . . . 117 figure 47: address match logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 figure 48: normal and tri-state outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 7/25/00 am79c976 13 preliminary figure 49: clk waveform for 5 v signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 figure 50: clk waveform for 3.3 v signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 figure 51: input setup and hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 figure 52: output valid delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 figure 53: output tri-state delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 figure 54: eeprom read functional timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 figure 55: automatic pread eeprom timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 figure 56: jtag (ieee 1149.1) tck waveform for 5 v signaling . . . . . . . . . . . . . . 276 figure 57: jtag (ieee 1149.1) test signal timing . . . . . . . . . . . . . . . . . . . . . . . . . 277 figure 58: transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 figure 59: receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 figure 60: mdc waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 figure 61: management data setup and hold timing . . . . . . . . . . . . . . . . . . . . . . . 280 figure 62: management data output valid delay timing . . . . . . . . . . . . . . . . . . . . . 280 figure 63: reject timing - external phy mii @ 25 mhz . . . . . . . . . . . . . . . . . . . . . 281 figure 64: reject timing - external phy mii @ 2.5 mhz . . . . . . . . . . . . . . . . . . . . . 282 figure 65: receive frame tag timing with media independent interface . . . . . . . . 283 figure 66: external memory timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 figure a-1: lapp timeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-4 figure a-2: lapp 3 buffer grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-5 figure a-3: lapp timeline for two-interrupt method . . . . . . . . . . . . . . . . . . . . . . . . . a-9 figure a-4: lapp 3 buffer grouping for two-interrupt method . . . . . . . . . . . . . . . . a-10 14 am79c976 7/25/00 preliminary list of tables table 1: system clock selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 2: slave commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 3: pci commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 4: descriptor read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 5: descriptor write sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 6: receive address match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 7: receive statistics counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 8: transmit statistics counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 9: vlan tag control command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 10: vlan tag type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 11: auto-negotiation capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 12: mac control pause frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 13: fc pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 14: fccmd bit functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 15: sram_type field encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 16: led default configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 17: ieee 1149.1 supported instruction summary . . . . . . . . . . . . . . . . . . . . . 104 table 18: bsr mode of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 19: device id register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 20: pci configuration space layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 21: address prom space contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 22: i/o map in word i/o mode (dwio = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 23: legal i/o accesses in word i/o mode (dwio = 0) . . . . . . . . . . . . . . . . . 109 table 24: i/o map in dword i/o mode (dwio = 1) . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 25: legal i/o accesses in double word i/o mode (dwio =1) . . . . . . . . . . . . 109 table 26: ap_value0: auto-poll value0 register . . . . . . . . . . . . . . . . . . . . . . . . . 122 table 27: ap_value1: auto-poll value1 register . . . . . . . . . . . . . . . . . . . . . . . . . 123 table 28: ap_value2: auto-poll value2 register . . . . . . . . . . . . . . . . . . . . . . . . . 123 table 29: ap_value3: auto-poll value3 register . . . . . . . . . . . . . . . . . . . . . . . . . 123 table 30: ap_value4: auto-poll value4 register . . . . . . . . . . . . . . . . . . . . . . . . . 123 table 31: ap_value5: auto-poll value5 register . . . . . . . . . . . . . . . . . . . . . . . . . 123 table 32: autopoll0: auto-poll0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 table 33: autopoll1: auto-poll1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 table 34: autopoll2: auto-poll2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 table 35: autopoll3: auto-poll3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 table 36: autopoll4: auto-poll4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 table 37: autopoll5: auto-poll5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 table 38: receive ring base address register . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 table 39: transmit ring base address register . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 table 40: chipid: chip id register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 table 41: chpolltime: chain polling interval register . . . . . . . . . . . . . . . . . . . . 129 table 42: cmd0: command0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 table 43: cmd2: command2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 table 44: cmd3: command3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 table 45: cmd7: command7 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 table 46: ctrl0: control0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 table 47: ctrl1: control1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 table 48: ctrl2: control2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 7/25/00 am79c976 15 preliminary table 49: ctrl3: control3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 table 50: software styles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 table 51: datambist: memory built-in self-test access register . . . . . . . . . . . . 145 table 52: delayed_int: delayed interrupts register . . . . . . . . . . . . . . . . . . . . . . 147 table 53: eeprom_acc: eeprom access register . . . . . . . . . . . . . . . . . . . . . . 148 table 54: interface pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 table 55: flash_addr: flash address register . . . . . . . . . . . . . . . . . . . . . . . . . 150 table 56: flash_data: flash data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 table 57: flow: flow control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 table 58: ifs1: inter-frame spacing part 1 register . . . . . . . . . . . . . . . . . . . . . . . 152 table 59: int0: interrupt0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 table 60: inten0: interrupt0 enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 table 61: ipg: inter-packet gap register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 table 62: logical address filter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 table 63: led0 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 table 64: max_lat_a: pci maximum latency alias register . . . . . . . . . . . . . . . . 160 table 65: min_gnt_a: pci minimum grant alias register . . . . . . . . . . . . . . . . . . 160 table 66: padr: physical address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 table 67: pause_cnt: pause count register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 table 68: pcidata0: pci data register zero alias register . . . . . . . . . . . . . . . . 161 table 69: phy_access: phy access register . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 table 70: pmat0: onnow pattern register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 table 71: pmat1: onnow pattern register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 table 72: receive protect register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 table 73: rcv_ring_len: receive ring length register . . . . . . . . . . . . . . . . . . 165 table 74: rom_cfg: rom base address configuration register . . . . . . . . . . . . . 166 table 75: sid_a: pci subsystem id alias register . . . . . . . . . . . . . . . . . . . . . . . . . 166 table 76: sram boundary register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 table 77: sram size register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 table 78: stat0: status0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 table 79: software timer value register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 table 80: svid: pci subsystem vendor id shadow register . . . . . . . . . . . . . . . . . 170 table 81: test0: test register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 table 82: vid_a: pci vendor id alias register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 table 83: xmt_ring_len: transmit ring length register . . . . . . . . . . . . . . . . . . 171 table 84: xmtpolltime: transmit polling interval register . . . . . . . . . . . . . . . . . 172 table 85: software styles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 table 86: receive watermark programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 table 87: transmit start point programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 table 88: transmit watermark programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 table 89: bcr registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 table 90: eedet setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 table 91: interface pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 table 92: software styles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 table 93: sram_bnd programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 table 94: fmdc values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 table 95: apdw values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 table 96: initialization block (ssize32 = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 table 97: initialization block (ssize32 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 16 am79c976 7/25/00 preliminary table 98: r/tlen decoding (ssize32 = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 table 99: r/tlen decoding (ssize32 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 table 100: receive descriptor (swstyle = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 table 101: receive descriptor (swstyle = 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 table 102: receive descriptor (swstyle = 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 table 103: receive descriptor (swstyle = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 table 104: receive descriptor (swstyle = 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 table 105: receive descriptor, swstyle = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 table 106: receive descriptor, swstyle = 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 table 107: receive descriptor, swstyle = 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 table 108: receive descriptor, swstyle = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 table 109: receive descriptor, swstyle = 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 table 110: transmit descriptor (swstyle = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 table 111: transmit descriptor (swstyle = 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 table 112: transmit descriptor (swstyle = 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 table 113: transmit descriptor (swstyle = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 table 114: transmit descriptor (swstyle = 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 table 115: transmit descriptor, swstyle = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 table 116: transmit descriptor, swstyle = 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 table 117: transmit descriptor, swstyle = 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 table 118: transmit descriptor, swstyle = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 table 119: transmit descriptor, swstyle = 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 table 120: register bit cross reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 table 121: control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 table 122: bus configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 table b-1: mii management register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-1 table b-2: mii management control register (register 0) . . . . . . . . . . . . . . . . . . . . b-1 table b-3: mii management status register (register 1) . . . . . . . . . . . . . . . . . . . . . b-2 table b-4: auto-negotiation advertisement register (register 4) . . . . . . . . . . . . . . . b-3 table b-5: technology ability field bit assignments . . . . . . . . . . . . . . . . . . . . . . . . . b-3 table b-6: auto-negotiation link partner ability register (register 5) - base page format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-4 8/01/00 am79c976 17 preliminary ordering information standard products amd standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the elements below. am79c976 temperature range c = commercial (0 c to +70 c) i = industrial ( ? 40 c to 85 c speed option package type valid combinations list configurations planned to be supported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly released combinations. valid combinations device number/description not applicable k = plastic quad flat pack (pqr208) am79c976 pcnet-pro 10/100 mbps pci ethernet controller valid combinations am79c976 kc\wv, ki\w alternate packaging option \w = trimmed and formed in a tray \w c k 18 am79c976 8/01/00 preliminary connection diagram (pqr208) 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 171 170 169 168 167 166 165 164 163 162 161 172 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 127 126 125 124 123 122 121 120 119 118 117 128 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 90 91 92 93 94 95 96 97 98 99 100 89 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 30 31 32 33 34 35 36 37 38 39 40 29 erd3/fld3 erd17 vdd erd18 erd19 vssb tx_en txd2 erd0/fld0 erd1/fld1 txd1 txd0 vssb crs vdd erd2/fld2 vdd erd4/fld4 erd5/fld5 erd6/fld6 vss erd7/fld7 vdd erd8/fla20 erd10/fla22 erd11/fla23 vssb vdd erd13 erd14 erd15 erd16 vss erd12 erd9/fla21 vssb txd3 col erd20 vssb irdy vdd trdy stop vssb perr vss serr par vdd c/be1 ad15 ad14 ad30 ad29 vdd ad28 ad27 ad26 vssb ad25 ad24 c/be3 vdd idsel ad23 ad22 vssb ad21 ad20 ad19 vdd ad18 ad17 ad16 vssb c/be2 frame devsel vss erce vdd eroe vssb erwe/flwe eradv/floe eradsp/cen vss vssb era13/fla13 era3/fla3 era4/fla4 vdd era5/fla5 era6/fla6 era8/fla8 era9/fla9 vdd vss vssb era11/fla11 era12/fla12 era14/fla14 vdd vssb era15/fla15 vdd era18/fla18 era17/fla17 vdd flcs vssb era1/fla1 era7/fla7 era16/fla16 erd31 era0/fla0 era10/fla10 era2/fla2 era19/fla19 vdd vss avdd vssb xtal1 ear vdd led0/eedi led2/rxfrtge xtal2 led3/eedo/rxfrtgd vss vssb clksel0 test vaux_sense phy_rst mdc rxd3 vssb vdd rxd0 eecs pme wumi fc rwu tck tms tdo pg vssb tdi xclk clksel1 mdio rxd2 rxd1 led1/eesk clksel2 am79c976 pcnet-pro inta rst vdd clk gnt ad31 vssb req 41 42 43 44 45 46 47 48 vssb ad13 ad12 ad11 vdd ad10 ad9 ad8 53 54 55 56 57 58 59 60 ad5 vdd ad4 ad3 vssb ad2 ad1 ad0 116 115 114 113 112 111 110 109 vdd erd23 erd24 erd25 erd22 erd21 vssb erclk 49 50 51 52 vssb c/be0 ad7 ad6 108 107 106 105 vssb erd26 vdd erd27 101 102 103 104 erd29 vssb erd28 erd30 160 159 158 157 rx_dv rx_er tx_clk rx_clk 208 207 206 205 204 203 202 201 22929b2 8/01/00 am79c976 19 preliminary pin designations (pqr208) listed by pin number pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 ad30 53 ad5 105 erd27 157 tx_clk 2 ad29 54 vdd 106 vdd 158 rx_er 3 vdd 55 ad4 107 erd26 159 rx_clk 4 ad28 56 ad3 108 vssb 160 rx_dv 5 ad27 57 vssb 109 erclk 161 rxd0 6 ad26 58 ad2 110 erd25 162 vdd 7 vssb 59 ad1 111 erd24 163 rxd1 8 ad25 60 ad0 112 erd23 164 vssb 9 ad24 61 erce 113 vdd 165 rxd2 10 c/be3 62 vdd 114 erd22 166 rxd3 11 vdd 63 eroe 115 vssb 167 mdc 12 idsel 64 vssb 116 erd21 168 mdio 13 ad23 65 erwe /flwe 117 erd20 169 phy_rst 14 ad22 66 eradv /floe 118 erd19 170 vaux_sense 15 vssb 67 eradsp /cen 119 erd18 171 test 16 ad21 68 vss 120 vdd 172 clksel0 17 vss 69 flcs 121 erd17 173 clksel1 18 ad20 70 vdd 122 vssb 174 vssb 19 ad19 71 era0/fla0 123 vss 175 clksel2 20 vdd 72 vssb 124 erd16 176 vss 21 ad18 73 era1/fla1 125 erd15 177 xtal2 22 ad17 74 era2/fla2 126 erd14 178 xtal1 23 ad16 75 era3/fla3 127 erd13 179 avdd 24 vssb 76 era4/fla4 128 vdd 180 xclk 25 c/be2 77 vdd 129 erd12 181 vdd 26 frame 78 era5/fla5 130 vssb 182 led3 /eedo/ rxfrtgd 27 irdy 79 vssb 131 erd11/fla23 183 led2 /rxfrtge 28 vdd 80 era6/fla6 132 erd10/fla22 184 led1 /eesk 29 trdy 81 era7/fla7 133 erd9/fla21 185 led0 /eedi 30 devsel 82 era8/fla8 134 erd8/fla20 186 eecs 31 stop 83 era9/fla9 135 vdd 187 ear 32 vssb 84 vdd 136 erd7/fld7 188 vssb 33 perr 85 era10/fla10 137 vssb 189 vss 34 vss 86 vss 138 vss 190 fc 20 am79c976 8/01/00 preliminary 35 serr 87 vssb 139 erd6/fld6 191 vdd 36 par 88 era11/fla11 140 erd5/fld5 192 pme 37 vdd 89 era12/fla12 141 erd4/fld4 193 wumi 38 c/be1 90 era13/fla13 142 erd3/fld3 194 rwu 39 ad15 91 era14/fla14 143 vdd 195 tck 40 ad14 92 vdd 144 erd2/fld2 196 tms 41 vssb 93 era15/fla15 145 vssb 197 tdo 42 ad13 94 vssb 146 erd1/fld1 198 tdi 43 ad12 95 era16/fla16 147 erd0/fld0 199 vssb 44 ad11 96 era17/fla17 148 crs 200 pg 45 vdd 97 era18/fla18 149 col 201 inta 46 ad10 98 era19/fla19 150 vdd 202 rst 47 ad9 99 vdd 151 txd3 203 vdd 48 ad8 100 erd31 152 txd2 204 clk 49 vssb 101 vssb 153 vssb 205 gnt 50 c/be0 102 erd30 154 txd1 206 req 51 ad7 103 erd29 155 txd0 207 vssb 52 ad6 104 erd28 156 tx_en 208 ad31 pin no. pin name pin no. pin name pin no. pin name pin no. pin name 8/01/00 am79c976 21 preliminary pin designations listed by group pin name pin function signal type 1 pin type 1 no. of pins clock interface xtal1 crystal i i 1 xtal2 crystal o o 1 xclk external clock i i 1 clksel0 clock select i i 1 clksel1 clock select i i 1 clksel2 clock select i i 1 test test select i i 1 pci bus interface ad[31:0] address/data bus io io 32 c/be [3:0] bus command/byte enable io io 4 clk bus clock i i 1 devsel device select io io 1 frame cycle frame io io 1 gnt bus grant i i 1 idsel initialization device select i i 1 inta interrupt o tso 1 irdy initiator ready io io 1 pa r pa r i t y i o i o 1 perr parity error io io 1 req bus request o tso 1 rst reset i i 1 serr system error io io 1 stop stop io io 1 trdy target ready io io 1 board interface led0 led0 o tso 1 led1 led1 o tso 1 led2 led2 o io 1 led3 led3 o io 1 phy_rst reset to phy o o 1 fc flow control i i 1 eeprom interface 22 am79c976 8/01/00 preliminary eecs serial eeprom chip select o o 1 eedi serial eeprom data in o tso 1 eedo serial eeprom data out i io 1 eesk serial eeprom clock io tso 1 external memory interface erclk external memory clock o o 1 era[19:0]/fla[19:0] external memory address[19:0] o o 20 erd[31:0] / fla[23:20] / fld[7:0] external memory data [31:0]/flash address[23:20]/flash data[7:0] io io 32 eradv /floe external memory advance o o 1 eradsp /cen external memory address strobe o o 1 eroe external memory output enable o o 1 erwe /flwe external memory write enable o o 1 erce ssram chip enable o o 1 flcs flash memory chip select o o 1 media independent interface (mii) col collision i i 1 crs carrier sense i i 1 fc hardware flow control i i 1 mdc management data clock o o 1 mdio management data i/o io io 1 rx_clk receive clock i i 1 rxd[3:0] receive data i i 4 rx_dv receive data valid i i 1 rx_er receive error i i 1 tx_clk transmit clock i i 1 txd[3:0] transmit data o o 4 tx_en transmit data enable o o 1 external address detection interface (eadi) ear external address reject i i 1 sfbd start frame byte delimiter note 2 note 2 1 rxfrtgd receive frame tag data i io 1 rxfrtge receive frame tag enable i io 1 power management interface rwu remote wake up o tso 1 pme power management event o od 1 wumi wake-up mode indicator o od 1 pg power good i i 1 pin name pin function signal type 1 pin type 1 no. of pins 8/01/00 am79c976 23 preliminary notes: 1. since some pins provide more than one signal, the pin type for a signal may differ from the signal type. 2. the sfbd signal can be programmed to appear on any of the led pins. table legend: vaux_sense vaux sense i i 1 ieee 1149.1 test access port interface (jtag) tck test clock i i 1 tdi test data in i i 1 tdo test data out o o 1 tms test mode select i i 1 power supplies vdd digital and i/o buffer power p p 24 vss digital ground p p 8 avdd analog vdd for pll and osc p p 1 vssb i/o buffer ground p p 25 pin name pin function signal type 1 pin type 1 no. of pins name pin type io input/output i input o output tso three-state output od open drain 24 am79c976 8/01/00 preliminary pin descriptions pci interface ad[31:0] address and data input/output address and data are multiplexed on the same bus in- terface pins. during the first clock of a transaction, ad[31:0] contain a physical address (32 bits). during the subsequent clocks, ad[31:0] contain data. byte or- dering is little endian by default. ad[7:0] are defined as the least significant byte (lsb) and ad[31:24] are defined as the most significant byte (msb). for fifo data transfers, the am79c976 controller can be pro- grammed for big endian byte ordering. see control 0 register, bit 24 (bswp) for more details. during the address phase of the transaction, when the am79c976 controller is a bus master, ad[31:2] will address the active double word (dword). the am79c976 controller always drives ad[1:0] to ? 00 ? dur- ing the address phase indicating linear burst order. when the am79c976 controller is not a bus master, the ad[31:0] lines are continuously monitored to determine if an address match exists for slave transfers. during the data phase of the transaction, ad[31:0] are driven by the am79c976 controller when performing bus master write and slave read operations. data on ad[31:0] is latched by the am79c976 controller when performing bus master read and slave write operations. the am79c976 device supports dual address cycles (dac) for systems with 64-bit addressing. as a bus master the am79c976 device will generate addresses of up to 40 bits in length. if the value of the c/be [3:0] bus during the pci address phase is 1101b, the ad- dress phase is extended to two clock cycles. the low order address bits appear on the ad[31:0] bus during the first clock cycle, and the high order bits appear dur- ing the second clock cycle. in dual address cycles the pci bus command (memory read, i/o write, etc.) ap- pears on the c/be pins during the second clock cycle. c/be [3:0] bus command and byte enables input/output bus command and byte enables are multiplexed on the same bus interface pins. during the address phase of the transaction, c/be [3:0] define the bus command. during the data phase, c/be [3:0] are used as byte en- ables. the byte enables define which physical byte lanes carry meaningful data. c/be 0 applies to byte 0 (ad[7:0]) and c/be 3 applies to byte 3 (ad[31:24]). the function of the byte enables is independent of the byte ordering mode (bswp, csr3, bit 2). clk clock input this clock is used to drive the system bus interface. all bus signals are sampled on the rising edge of clk and all parameters are defined with respect to this edge. the am79c976 controller normally operates over a fre- quency range of 15 mhz to 33 mhz on the pci bus due to networking demands. the am79c976 controller will support a clock frequency of 0 mhz after certain pre- cautions are taken to ensure data integrity. this clock or a derivation is not used to drive any network func- tions. devsel device select input/output the am79c976 controller drives devsel when it de- tects a transaction that selects the device as a target. the device samples devsel to detect if a target claims a transaction that the am79c976 controller has initiated. frame cycle frame input/output frame is driven by the am79c976 controller when it is the bus master to indicate the beginning and duration of a transaction. frame is asserted to indicate a bus transaction is beginning. frame is asserted while data transfers continue. frame is deasserted before the final data phase of a transaction. when the am79c976 controller is in slave mode, it samples frame to determine the address phase of a transac- tion. gnt bus grant input this signal indicates that the access to the bus has been granted to the am79c976 controller. the am79c976 controller supports bus parking. when the pci bus is idle and the system arbiter asserts gnt without an active req from the am79c976 controller, the device will drive the ad[31:0], c/be [3:0], and par lines. idsel initialization device select input this signal is used as a chip select for the am79c976 controller during configuration read and write transac- tions. inta interrupt request output an attention signal which indicates that one or more enabled interrupt flag bits are set. see the descriptions of the int and inten registers for details. 8/01/00 am79c976 25 preliminary by default inta is an open-drain output. for applica- tions that need an active-high edge-sensitive interrupt signal, the inta pin can be configured for this mode by setting intlevel (cmd3, bit 13 or bcr2, bit 7) to 1. irdy initiator ready input/output irdy indicates the ability of the initiator of the transac- tion to complete the current data phase. irdy is used in conjunction with trdy . wait states are inserted until both irdy and trdy are asserted simultaneously. a data phase is completed on any clock when both irdy and trdy are asserted. when the am79c976 controller is a bus master, it as- serts irdy during all write data phases to indicate that valid data is present on ad[31:0]. during all read data phases, the device asserts irdy to indicate that it is ready to accept the data. when the am79c976 controller is the target of a trans- action, it checks irdy during all write data phases to determine if valid data is present on ad[31:0]. during all read data phases, the device checks irdy to deter- mine if the initiator is ready to accept the data. pa r parity input/output parity is even parity across ad[31:0] and c/be [3:0]. when the am79c976 controller is a bus master, it gen- erates parity during the address and write data phases. it checks parity during read data phases. when the am79c976 controller operates in slave mode, it checks parity during every address phase. when it is the target of a cycle, it checks parity during write data phases and it generates parity during read data phases. perr parity error input/output during any slave write transaction and any master read transaction, the am79c976 controller asserts perr when it detects a data parity error and reporting of the error is enabled by setting perren (pci command register, bit 6) to 1. during any master write transaction, the am79c976 controller monitors perr to see if the target reports a data parity error. req bus request input/output the am79c976 controller asserts req pin as a signal that it wishes to become a bus master. req is driven high when the am79c976 controller does not request the bus. rst reset input when rst is asserted low and the pg pin is high, then the am79c976 controller performs an internal system reset of the type h_reset (hardware_reset, see section on reset). imme- diately after the initial power up, rst must be held low for 26s. at any other time rst must be held low for a minimum of 30 clock periods to guarantee that the de- vice is properly reset. while in the h_reset state, the am79c976 controller will disable or deassert all out- puts. rst may be asynchronous to clock when as- serted or deasserted. asserting rst disables all of the pci pins except the pme pin. serr system error output during any slave transaction, the am79c976 controller asserts serr when it detects an address parity error, and reporting of the error is enabled by setting per- ren (pci command register, bit 6) and serren (pci command register, bit 8) to 1. by default serr is an open-drain output. for compo- nent test, it can be programmed to be an active-high totem-pole output. stop stop input/output in slave mode, the am79c976 controller drives the stop signal to inform the bus master to stop the cur- rent transaction. in bus master mode, the am79c976 controller checks stop to determine if the target wants to disconnect the current transaction. trdy target ready input/output trdy indicates the ability of the target of the transac- tion to complete the current data phase. wait states are inserted until both irdy and trdy are asserted simul- taneously. a data phase is completed on any clock when both irdy and trdy are asserted. when the am79c976 controller is a bus master, it checks trdy during all read data phases to determine if valid data is present on ad[31:0]. during all write data phases, the device checks trdy to determine if the target is ready to accept the data. when the am79c976 controller is the target of a trans- action, it asserts trdy during all read data phases to indicate that valid data is present on ad[31:0]. during all write data phases, the device asserts trdy to indi- cate that it is ready to accept the data. 26 am79c976 8/01/00 preliminary pme power management event output, open drain pme is an output that can be used to indicate that a power management event (a magic packet, an onnow pattern match, or a change in link state) has been de- tected. the pme pin is asserted when either: 1. pme_status and pme_en are both 1, 2. pme_en_ovr and mpmat are both 1, or 3. pme_en_ovr and lcdet are both 1. the pme signal is asynchronous with respect to the pci clock. board interface note: before programming the led pins, see the de- scription of ledpe in bcr2, bit 12. led0 led0 output this output is designed to directly drive an led. by de- fault, led0 indicates an active link connection. this pin can also be programmed to indicate other network sta- tus (see bcr4). the led0 pin polarity is programma- ble, but by default it is active low. when the led0 pin polarity is programmed to active low, the output is an open drain driver. when the led0 pin polarity is pro- grammed to active high, the output is a totem pole driver. note: the led0 pin is multiplexed with the eedi pin. led1 l ed1 o u tp u t this output is designed to directly drive an led. by de- fault, led1 indicates receive or transmit activity on the network. this pin can also be programmed to indicate other network status (see bcr5). the led1 pin polar- ity is programmable, but by default, it is active low. when the led1 pin polarity is programmed to active low, the output is an open drain driver. when the led1 pin polarity is programmed to active high, the output is a totem pole driver. note: the led1 pin is multiplexed with the eesk pin. led2 l e d 2 o u t p u t this output is designed to directly drive an led. by de- fault, led2 indicates that the network bit rate is 100 mb/s. this pin can also be programmed to indicate var- ious network status (see bcr6). the led2 pin polarity is programmable, but by default it is active low. when the led2 pin polarity is programmed to active low, the output is an open drain driver. when the led2 pin po- larity is programmed to active high, the output is a totem pole driver. note: the led2 pin is multiplexed with the rxfrtge pin. led3 led3 output this output is designed to directly drive an led. by de- fault, led3 indicates that a collision has occurred. this pin can also be programmed to indicate other network status (see bcr7). the led3 pin polarity is program- mable, but by default it is active low. when the led3 pin polarity is programmed to active low, the output is an open drain driver. when the led3 pin polarity is pro- grammed to active high, the output is a totem pole driver. special attention must be given to the external circuitry attached to this pin. when this pin is used to drive an led while an eeprom is used in the system, then buffering may be required between the led3 pin and the led circuit. if an led circuit were directly attached to this pin, it may create an i ol requirement that could not be met by the serial eeprom attached to this pin. if no eeprom is included in the system design or low current leds are used, then the led3 signal may be directly connected to an led without buffering. in any case, if an eeprom is present, there must be a pull-up resistor connected to this pin (10 k should be ade- quate). for more details regarding led connection, see the section on led support . note: the led3 pin is multiplexed with the eedo and rxfrtgd pins. pg power good input the pg pin has two functions: (1) it puts the device into magic packet mode, and (2) it blocks any resets when the pci bus power is off. when pg is low and either mppen or mpmode is set to 1, the device enters the magic packet mode. when pg is low, a low assertion of the pci rst pin will only cause the pci interface pins (except for pme ) to be put in the high impedance state. the internal logic will ignore the assertion of rst . when pg is high, assertion of the pci rst pin causes the controller logic to be reset and the configu- ration information to be loaded from the eeprom. rwu remo t e wake up o u t pu t rwu is an output that is asserted either when the con- troller is in the magic packet mode and a magic packet frame has been detected, or the controller is in the link change detect mode and a link change has been de- tected. 8/01/00 am79c976 27 preliminary this pin can drive the external system management logic that causes the cpu to get out of a low power mode of operation. this pin is implemented for designs that do not support the pme function. three bits that are loaded from the eeprom into csr116 can program the characteristics of this pin: 1. rwu_pol determines the polarity of the rwu sig- nal. 2. if rwu_gate bit is set, rwu is forced to the high impedance state when pg input is low. 3. rwu_driver determines whether the output is open drain or totem pole. the internal power-on-reset signal forces this output into the high impedance state until after the polarity and drive type have been determined. wumi wa k e - u p m o d e i n d i c a t o r o u t p u t , open drain this output, which is capable of driving an led, is as- serted when the device is in magic packet mode. it can be used to drive external logic that switches the device power source from the main power supply to an auxil- iary power supply. vaux_sense 3.3 vaux presence sense input the signal on this pin is logically anded with bit 15 of the pci pmc register when the pmc register is read. this pin should normally be connected to the pci 3.3 vaux pin. this allows the pmc register to indicate that the device is capable of supporting pme from the d3 cold state only when the 3.3 vaux pin is supplying power. clksel0 clock select 0 input the am79c976 system clock can either be driven by an external clock generator connected to the xclk pin or by an internal clock generator timed by a 25-mhz crystal connected between the xtal1 and xtal2 pins. the clksel0 and clksel1 pins select the source of the system clock and the frequency at which the exter- nal clock generator must run. in addition, clksel0 and clksel1 determine the frequency of erclk, the external ssram clock. table 1 shows the possible combinations. clksel1 clock select 1 input the am79c976 system clock can either be driven by an external clock generator connected to the xclk pin or by an internal clock generator timed by a 25-mhz crystal connected between the xtal1 and xtal2 pins. the clksel0 and clksel1 pins select the source of the system clock and the frequency at which the exter- nal clock generator must run. in addition clksel0 and clksel1 determine the frequency of erclk, the ex- ternal ssram clock. table 1 shows the possible com- binations. clksel2 clo ck s elec t 2 i np u t the clksel2 pin must be held low during normal op- eration. test test reset input the test pin must be held low during normal opera- tion. xclk external clock input input the am79c976 system clock can either be driven by an external clock generator connected to this pin or by a 25-mhz crystal connected between the xtal1 and xtal2 pins, depending on the state of the clksel0 and clksel1 pins. when either clksel0 or clksel1 or both are held high, a 20-, 25-, or 33 1 / 3 -mhz clock signal must be applied to xclk as shown in table 1. when clksel0 and clksel1 are both held low, the xclk pin should be connected to ei- ther vss or vdd. table 1. system clock selections xtal1 cr y st al i np u t if the clksel0 and clksel1 pins are both held low, a 25-mhz crystal should be connected between the xtal1 pin and the xtal2 pin. this crystal controls the frequency of the internal clock-generator circuit. if the clksel0 and clksel1 pins are not both held low, a 20-, 25-, or 33 1 / 3 -mhz clock source must be con- clksel2 clksel1 clksel0 clock source erclk (mhz) 1xx design factory te s t o n l y. 000 25-mhz crystal, xtal1,xt al2 87.5 001 xclk, 20 mhz 90 010 xclk, 25 mhz 87.5 011 xclk, 33 1 / 3 mhz 82.5 28 am79c976 8/01/00 preliminary nected to the xclk pin, and the xtal1 and xtal2 pins should be connected to vss. xtal1 and xtal2 are not 5-volt tolerant pins. xtal2 crystal output if the clksel0 and clksel1 pins are both held low, a 25 mhz crystal should be connected between the xtal1 pin and the xtal2 pin. this crystal controls the frequency of the internal clock generator circuit. if either the clksel0 or the clksel1 pin or both are held high, a 20-, 25-, or 33 1 / 3 -mhz clock source must be connected to the xclk pin, and the xtal1 and xtal2 pins should be connected to vss. xtal1 and xtal2 are not 5-volt tolerant pins. phy_rst phy reset output phy_rst is an output pin that is used to reset the ex- ternal phy. this output eliminates the need for a fan-out buffer for the pci rst signal, provides polarity for the specific phy used, and prevents the resetting of the phy when the pg input is low. the output polarity is determined by the phy_rst_pol bit (cmd3, bit0), which can be loaded from the eeprom. the length of time for which the phy_rst pin is as- serted depends on the number of registers that are loaded from the eeprom and the order in which the registers are loaded. immediately after the phy_rst_pol bit is loaded from the eeprom, the phy_rst pin is asserted. when the last register has been loaded from the eeprom, the phy_rst pin is deasserted. each register loaded after the phy_rst_pol bit is loaded adds about 240 s to the time that phy_rst is asserted. if the phy_rst pin is used to reset an external phy, the user should program the eeprom to make sure that phy_rst is asserted long enough to meet the requirements of the phy. the user can insert dummy writes to offset 28h to extend the reset period. fc flow control input the flow control input signal controls when mac con- trol pause frames are sent or when half-duplex back pressure is asserted. eeprom interface eecs e e p ro m c h i p s e l e c t o u t p u t this pin is designed to directly interface to a serial ee- prom that uses the 93cxx eeprom interface proto- col. eecs is connected to the eeprom ? s chip select pin. it is controlled by either the am79c976 controller during command portions of a read of the entire ee- prom, or indirectly by the host system by writing to bcr19, bit 2. eedi e e p ro m d a t a i n o u t p u t this pin is designed to directly interface to a serial ee- prom that uses the 93cxx eeprom interface proto- col. eedi is connected to the eeprom ? s data input pin. it is controlled by either the am79c976 controller during command portions of a read of the entire ee- prom, or indirectly by the host system by writing to bcr19, bit 0. note: the eedi pin is multiplexed with the led0 pin. eedo ee p ro m da t a o u t i np u t this pin is designed to directly interface to a serial ee- prom that uses the 93cxx eeprom interface proto- col. eedo is connected to the eeprom ? s data output pin. it is controlled by either the am79c976 controller during command portions of a read of the entire ee- prom, or indirectly by the host system by reading from bcr19, bit 0. note: the eedo pin is multiplexed with the led3 and rxfrtgd pins. eesk e e p ro m s e r i a l c l o ck o u t p u t this pin is designed to directly interface to a serial ee- prom that uses the 93cxx eeprom interface proto- col. eesk is connected to the eeprom ? s clock pin. it is controlled by either the am79c976 controller directly during a read of the entire eeprom, or indirectly by the host system by writing to bcr19, bit 1. note: the eesk pin is multiplexed with the led1 pin. external memory interface era[19:0]/fla[19:0] e x t e r n a l m e m o r y a d d r e s s [ 1 9 : 0 ] o u t p u t the era[19:0] pins provide addresses for both the ex- ternal ssram and the external boot rom device. all era[19:0] pin outputs are forced to a constant level to conserve power while no access on the external memory bus is being performed. fla[23:20] b o o t ro m ( f l a s h ) a d d r e s s [ 2 3 : 2 0 ] o u t p u t the fla[23:20] pins provide the 4 most significant bits of the address for the external boot rom device. all fla[23:20] pin outputs are forced to a constant level to conserve power while no access on the external memory bus is being performed. 8/01/00 am79c976 29 preliminary note: the fla[23:20] pins are multiplexed with the erd[11:8] pins. erd[31:0]/fld[7:0] external memory data [31:0] input/output the erd[7:0] pins provide data bits [7:0] for boot rom accesses. the erd[31:0] pins provide data bits [31:0] for external ssram accesses. the erd[31:0] signals are forced to a constant level to conserve power while no access on the external memory bus is being per- formed. note: the fla[23:20] pins are multiplexed with the erd[11:8] pins. erce ex te rn al ss ram ch ip en ab le o u tp u t erce serves as the chip enable for the external ss- ram. it is asserted low when the ssram address on the era[19:0] pins is valid. flcs bo o t ro m c hi p sel ect o u tp u t flcs serves as the chip select for the boot device. it is asserted low when the boot rom address on the fla[23:20] and era[19:0] pins is valid. eroe external ssram output enable output eroe is asserted active low during ssram device read operations to allow the ssram device to drive the erd[31:0] data bus. it is deasserted at all other times. floe expansion rom output enable output floe is asserted active low during boot rom read operations to allow the boot rom to drive the erd[7:0] data bus. it is deasserted at all other times. note: the floe pin is multiplexed with the eradv pin. erwe / flwe external memory write enable output erwe provides the write enable for write accesses to the external ssram and the flash (boot rom) device. eradsp / cen ex te rn al memo r y add re ss s t rob e o u tp u t eradsp provides the address strobe signal to load the address into the external ssram. eradv external memory address advance output eradv provides the address advance signal to the ex- ternal ssram. this signal is asserted low during a burst access to increment the address counter in the ssram. note: the floe pin is multiplexed with the eradv pin. erclk e x t e r n a l m e m o r y c l o c k o u t p u t erclk is the reference clock for all synchronous sram accesses. media independent interface tx_clk tra n smit clo ck i np u t tx_clk is a continuous clock input that provides the timing reference for the transfer of the tx_en and txd[3:0] signals out of the am79c976 device. tx_clk must provide a nibble rate clock (25% of the network data rate). hence, an mii transceiver operating at 10 mbps must provide a tx_clk frequency of 2.5 mhz and an mii transceiver operating at 100 mbps must provide a tx_clk frequency of 25 mhz. txd[3:0] tr a n s m i t d a t a o u t p u t txd[3:0] is the nibble-wide mii transmit data bus. valid data is generated on txd[3:0] on every tx_clk rising edge while tx_en is asserted. while tx_en is deas- serted, txd[3:0] values are driven to a 0. txd[3:0] transitions synchronous to tx_clk rising edges. tx_en transmit enable output tx_en indicates when the am79c976 device is pre- senting valid transmit nibbles on the mii. while tx_en is asserted, the am79c976 device generates txd[3:0] on tx_clk rising edges. tx_en is asserted with the first nibble of preamble and remains asserted through- out the duration of a packet until it is deasserted prior to the first tx_clk following the final nibble of the frame. tx_en transitions synchronous to tx_clk ris- ing edges. col collision input col is an input that indicates that a collision has been detected on the network medium. crs car rie r s en se i np u t crs is an input that indicates that a non-idle medium, due either to transmit or receive activity, has been de- tected. 30 am79c976 8/01/00 preliminary rx_clk receive clock input rx_clk is a clock input that provides the timing refer- ence for the transfer of the rx_dv, rxd[3:0], and rx_er signals into the am79c976 device. rx_clk must provide a nibble rate clock (25% of the network data rate). hence, an mii transceiver operating at 10 mbps must provide an rx_clk frequency of 2.5 mhz and an mii transceiver operating at 100 mbps must pro- vide an rx_clk frequency of 25 mhz. when the exter- nal phy switches the rx_clk and tx_clk, it must provide glitch-free clock pulses. rxd[3:0] receive data input rxd[3:0] is the nibble-wide mii receive data bus. data on rxd[3:0] is sampled on every rising edge of rx_clk while rx_dv is asserted. rxd[3:0] is ignored while rx_dv is de-asserted. rx_dv receive data valid input rx_dv is an input used to indicate that valid, received data is being presented on the rxd[3:0] pins and rx_clk is synchronous to the receive data. in order for a frame to be fully received by the am79c976 de- vice on the mii, rx_dv must be asserted prior to the rx_clk rising edge, when the first nibble of the start- of-frame delimiter is driven on rxd[3:0], and must re- main asserted until after the rising edge of rx_clk, when the last nibble of the crc is driven on rxd[3:0]. rx_dv must then be deasserted prior to the rx_clk rising edge which follows this final nibble. rx_dv tran- sitions are synchronous to rx_clk rising edges. rx_er receive error input rx_er is an input that indicates that the mii trans- ceiver device has detected a coding error in the receive frame currently being transferred on the rxd[3:0] pins. when rx_er is asserted while rx_dv is asserted, a crc error will be indicated in the receive descriptor for the incoming receive frame. rx_er is ignored while rx_dv is deasserted. special code groups generated on rxd while rx_dv is deasserted are ignored (e.g., bad ssd in tx and idle in t4). rx_er transitions are synchronous to rx_clk rising edges. mdc m a n a g e m e n t d a t a c l o ck o u t p u t mdc is a non-continuous clock output that provides a timing reference for bits on the mdio pin. during mii management port operations, mdc runs at a nominal frequency of 2.5 mhz. when no management opera- tions are in progress, mdc is driven low. if the mii management port is not used, the mdc pin can be left floating. mdio management data i/o input/output mdio is the bidirectional mii management port data pin. mdio is an output during the header portion of the management frame transfers and during the data por- tions of write transfers. mdio is an input during the data portions of read data transfers. when an operation is not in progress on the management port, mdio is not driven. mdio transitions from the am79c976 controller are synchronous to mdc falling edges. if the phy is attached through an mii physical connec- tor, then the mdio pin should be externally pulled down to vss with a 10-k 5% resistor. if the phy is perma- nently connected, then the mdio pin should be exter- nally pulled up to vcc with a 10-k 5% resistor. external address detection interface ear ex te rn al add res s re ject i np u t the incoming frame will be checked against the inter- nally active address detection mechanisms and the re- sult of this check will be or ? d with the value on the ear pin. the ear pin acts as an external address accept function. the pin value is or ? d with the internal ad- dress detection result to determine if the current frame should be accepted. if ear remains high while a frame is being received, the frame will be accepted regard- less of the state of the internal address matching logic. the ear pin must not be left unconnected. if it is not used, it should be tied to vss through a 10-k 5% re- sistor. sfbd s t a r t f r a m e - b y t e d e l i m i t e r o u t p u t an initial rising edge on the sfbd signal indicates that a start of valid data is present on the rxd[3:0] pins. sfbd will go high for one nibble time (400 ns when op- erating at 10 mbps and 40 ns when operating at 100 mbps) one rx_clk period after rx_dv has been as- serted and rx_er is deasserted, and there is the de- tection of the sfd (start of frame delimiter) of a received frame. data on the rxd[3:0] will be the start of the destination address field. sfbd will subsequently toggle every nib- ble time (1.25 mhz frequency when operating at 10 mbps and 12.5 mhz frequency when operating at 100 mbps), indicating the first nibble of each subsequent byte of the received nibble stream. the rx_clk should be used in conjunction with the sfbd to latch the correct data for external address matching. sfbd will be active only during frame reception. 8/01/00 am79c976 31 preliminary note: the sfbd signal can be programmed to appear on any of the led pins. rxfrtgd receive frame tag data input when the eadi is enabled (eadisel, bcr2, bit 3) and the receive frame tagging is enabled (rxfrtg, csr7, bit 14), the rxfrtgd pin becomes a data input pin for the receive frame tag. see the receive frame tagging section for details. note: the rxfrtgd pin is multiplexed with the led3 and eedo pins. rxfrtge receive frame tag enable input when the eadi is enabled (eadisel, bcr2, bit 3) and the receive frame tagging is enabled (rxfrtg, csr7, bit 14), the rxfrtge pin becomes a data input enable pin for the receive frame tag. see the receive frame tagging section for details. note: the rxfrtge pin is multiplexed with the led2 pin. ieee 1149.1 (1990) test access port interface tck test clock input tck is the clock input for the boundary scan test mode operation. it can operate at a frequency of up to 10 mhz. tck has an internal pull-up resistor. tdi test data in input tdi is the test data input path to the am79c976 con- troller. the pin has an internal pull-up resistor. tdo test data out output tdo is the test data output path from the am79c976 controller. the pin is tri-stated when the jtag port is in- active. tms test mode select input a serial input bit stream on the tms pin is used to define the specific boundary scan test to be executed. the pin has an internal pull-up resistor. power supply pins avdd analog power (1 pin) power this power supply pin is used for the internal oscillator and phase-locked loop circuits. this pin must be connected to a +3.3-v supply. vssb i/o buffer ground (25 pins) power there are 25 ground pins that are used by the input/ output buffer drivers. vdd digital and i/o buffer power (24 pins) power there are 24 power supply pins that are used by the in- ternal digital circuitry and i/o buffers. all vdd pins must be connected to a +3.3 v supply. vss digital ground (8 pins) power there are eight ground pins that are used by the inter- nal digital circuitry. 32 am79c976 8/01/00 preliminary system bus interface the am79c976 controller is designed to operate as a bus master during normal operations. some slave i/o accesses to the am79c976 controller are required in normal operations as well. initialization of the am79c976 controller is achieved through a combina- tion of pci configuration space accesses, bus slave accesses, bus master accesses, and an optional read of a serial eeprom that is performed by the am79c976 controller. the eeprom read operation is performed through the 93cxx eeprom interface. the iso 8802-3 (ieee/ansi 802.3) ethernet address may reside within the serial eeprom. some am79c976 controller configuration registers may also be pro- grammed by the eeprom read operation. the am79c976 controller requires 4 kbytes of memory address space for access to all the various internal reg- isters as well as access to some setup information stored in an external serial eeprom. for compatibility with previous pcnet family devices, the lower 32 bytes of the register space are also mapped into i/o space, but some functions of the am79c976 controller (such as network statistics) are only available in memory space. the location of the memory or i/o address space claimed by this device is programmed through the base address registers in pci configuration space. for diskless stations, the am79c976 controller sup- ports a rom or flash-based (both referred to as the expansion rom throughout this specification) boot de- vice of up to 16 mbyte in size. the host can map the boot device to any memory address that aligns to a de- vice size boundary by modifying the expansion rom base address register in the pci configuration space. the expansion rom device size is determined by the value set in the rom-cfg register. software interface the software interface to the am79c976 controller is divided into three parts. one part is the pci configura- tion registers used to identify the am79c976 controller and to setup the configuration of the device. the setup information includes the i/o or memory mapped i/o base address, mapping of the expansion rom, and the routing of the am79c976 controller interrupt chan- nel. this allows for a jumperless implementation. the second portion of the software interface is the direct access to the i/o resources of the am79c976 controller. the am79c976 controller requires 4 kbytes of memory address space for access to all the various internal registers as well as access to some setup infor- mation stored in an external serial eeprom. for com- patibility with previous pcnet family devices, the lower 32 bytes of the register space are also mapped into i/o space, but some functions of the am79c976 controller (such as network statistics) are only available in mem- ory space. the third portion of the software interface is the de- scriptor and buffer areas that are shared between the software and the am79c976 controller during normal network operations. the descriptor area boundaries are set by the software and do not change during nor- mal network operations. there is one descriptor area for receive activity and there is a separate area for transmit activity. the descriptor space contains relocat- able pointers to the network frame data, and it is used to transfer frame status from the am79c976 controller to the software. the buffer areas are locations that hold frame data for transmission or that accept frame data that has been received. network interface the am79c976 controller can be connected to an ieee 802.3 or proprietary network through the ieee 802.3-compliant media independent interface (mii). the mii is a nibble-wide interface to an external 100-mbps and/or 10-mbps transceiver device. the am79c976 controller supports both half-duplex and full-duplex operation on the network interface. 8/01/00 am79c976 33 preliminary detailed functions slave bus interface unit the slave bus interface unit (biu) controls all accesses to the pci configuration space, the control and status registers (csr), the bus configuration registers (bcr), the address prom (aprom) locations, and the expansion rom. table 2 shows the response of the am79c976 controller to each of the pci commands in slave mode. table 2. slave commands slave configuration transfers the host can access the am79c976 pci configuration space with a configuration read or write command. the am79c976 controller will assert devsel during the address phase when idsel is asserted, ad[1:0] are both 0, and the access is a configuration cycle. ad[7:2] select the dword location in the configuration space. the am79c976 controller requires ad[10:8] to be 0, because it is a single function device. ad[31:11] are ? don't care. ? the active bytes within a dword are determined by the byte enable signals. eight-bit, 16-bit, and 32-bit trans- fers are supported. devsel is asserted two clock cy- cles after the host has asserted frame . all configuration cycles are of fixed length. the am79c976 controller will assert trdy on the third or fourth clock of the data phase. the am79c976 controller does not support burst trans- fers for access to configuration space. when the host keeps frame asserted for a second data phase, the am79c976 controller will disconnect the transfer. when the host tries to access the pci configuration space while the automatic read of the eeprom after h_reset (see section on reset) is on-going, the am79c976 controller will terminate the access on the pci bus with a disconnect/retry response. the am79c976 controller supports fast back-to-back transactions to different targets. this is indicated by the fast back-to-back capable bit (pci status register, bit 7), which is hardwired to 1. the am79c976 control- ler is capable of detecting a configuration cycle even when its address phase immediately follows the data phase of a transaction to a different target without any idle state in-between. there will be no contention on the devsel , trdy, and stop signals, since the am79c976 controller asserts devsel on the second clock after frame is asserted (medium timing). slave i/o transfers after the am79c976 controller is configured as an i/o device by setting ioen (for regular i/o mode) or memen (for memory mapped i/o mode) in the pci command register, it starts monitoring the pci bus for access to its address space. if configured for regular i/o mode, the am79c976 controller will look for an ad- dress that falls within its 32 bytes of i/o address space (starting from the i/o base address). the am79c976 controller asserts devsel if it detects an address match and the access is an i/o cycle. if configured for memory mapped i/o mode, the am79c976 controller will look for an address that falls within its 4096 bytes of memory address space (starting from the memory mapped i/o base address). the am79c976 controller asserts devsel if it detects an address match and the c[3:0] command use 0000 interrupt acknowledge not used 0001 special cycle not used 0010 i/o read read of csr, bcr, aprom, and reset registers 0011 i/o write write to csr, bcr, and aprom 0100 reserved 0101 reserved 0110 memory read memory mapped i/o read of csr, bcr, aprom, and reset registers read of the expansion bus 0111 memory write memory mapped i/o write of csr, bcr, and aprom 1000 reserved 1001 reserved 1010 configuration read read of the configuration space 1011 configuration write write to the configuration space 1100 memory read multiple aliased to memory read 1101 dual address cycle not used 1110 memory read line aliased to memory read 1111 memory write invalidate aliased to memory write a d 3 1 - ad11 ad10 - ad8 a d 7 - ad2 ad1 ad0 don ? t care 0 dword index 00 34 am79c976 8/01/00 preliminary access is a memory cycle. devsel is asserted two clock cycles after the host has asserted frame . see figure 11 and figure 22. for compatibility with older members of the pcnet family of controllers, the 32 lowest addresses of the i/o or memory space claimed by the am79c976 device sup- port indirect addressing of internal registers. the am79c976 controller does not support burst transfers for access to these locations. when the host keeps frame asserted for a second data phase in this ad- dress range, the am79c976 controller will disconnect the transfer. however, the controller does support burst accesses to locations at offsets 32 and above. because of the side effects of reading the reset reg- ister at offset 14h or 18h (depending on the state of dwio (cmd2, bit 28)), locations at offsets less than 20h cannot be prefetched. the am79c976 controller supports fast back-to-back transactions to different targets. this is indicated by the fast back-to-back capable bit (pci status register, bit 7), which is hardwired to 1. the am79c976 controller is capable of detecting an i/o or a memory-mapped i/o cycle even when its address phase immediately fol- lows the data phase of a transaction to a different target, without any idle state in-between. there will be no con- tention on the devsel , trdy, and stop signals, since the am79c976 controller asserts devsel on the sec- ond clock after frame is asserted (medium timing). see figure 33 and figure 44. 6 frame clk ad irdy trdy c/be devsel stop idsel 1 23456 1010 par par par be data addr 7 22929b3 frame clk ad irdy trdy c/be devsel stop idsel 1 23456 1011 par par par be data addr 7 22929b4 the am79c976 controller will not assert devsel if it detects an address match, but the pci command is not of the correct type. in memory mapped i/o mode, the am79c976 controller aliases all accesses to the i/o re- sources of the command types memory read multiple and memory read line to the basic memory read command. all accesses of the type memory write and invalidate are aliased to the basic memory write com- mand. eight-bit, 16-bit, and 32-bit transactions are sup- ported. the am79c976 controller decodes all 32 address lines to determine which i/o resource is ac- cessed. the number of wait states added to slave transactions varies. typical values are shown in the table below: slave transactions transaction type read write memory-mapped transactions 90 i/o-mapped transactions 9 3 8/01/00 am79c976 35 preliminary !! frame clk ad irdy trdy c/be devsel stop par addr 0010 par 1 2345678 10 9 11 data par be 22929b5 36 am79c976 8/01/00 preliminary " #!$!! frame clk ad irdy trdy c/be devsel stop par addr 0111 par 1 2345678 10 9 11 data par be 22929b6 8/01/00 am79c976 37 preliminary %&' # the am79c976 device includes an interface to an op- tional expansion rom. the amount of pci address space claimed by this rom is determined by the con- tents of the rom configuration register, rom_cfg, which should normally be loaded from the serial ee- prom. the host must initialize the expansion rom base address register at offset 30h in the pci configuration space with a valid address before enabling the access to the device. the am79c976 controller will not react to any access to the expansion rom until both memen (pci command register, bit 1) and romen (pci ex- pansion rom base address register, bit 0) are set to 1. after the expansion rom is enabled, the am79c976 controller will assert devsel on all memory read ac- cesses to the memory space defined by the contents of the expansion rom base address register. the am79c976 controller aliases all accesses to the ex- pansion rom of the command types memory read multiple and memory read line to the basic memory read command. eight-bit, 16-bit, and 32-bit read trans- fers are supported. since setting memen also enables memory mapped access to the i/o resources, attention must be given the pci memory mapped i/o base address register before enabling access to the expansion rom. the host must set the pci memory mapped i/o base ad- dress register to a value that prevents the am79c976 controller from claiming any memory cycles not in- tended for it. the am79c976 controller will always read four bytes for every host expansion rom read access. since this takes more than 16 pci clock cycles, the am79c976 device will assert stop to force a pci bus retry. sub- sequent accesses will be retried until all four bytes have been read from the rom and stored in an internal tem- porary register. the timing of the access to the rom device is determined by the romtmg parameter (ctrl0, bits 11-8). note: the expansion rom must not be read when the am79c976 controller is running (when the run bit in cmd0 is set to 1). any access to the expansion rom clears the run bit and thereby abruptly stops all net- work and dma operations. when the host tries to write to the expansion rom, the am79c976 controller will claim the cycle. the write op- eration will have no effect. writes to the expansion rom are done through the bcr30 expansion bus data port. see the section on the expansion bus inter- face for more details. during the boot procedure, the system will try to find an expansion rom. a pci system assumes that an ex- pansion rom is present when it reads the rom signa- ture 55h (byte 0) and aah (byte 1). $( ! in addition to the normal completion of a transaction, there are three scenarios in which the am79c976 con- troller terminates a slave access for which it is the tar- get. if a slave access to the am79c976 device takes more than 16 pci clk cycles, the am79c976 device will generate a pci disconnect/retry cycle by asserting stop and deasserting trdy while keeping devsel asserted. this will free up the pci bus so that it can be used by other bus masters while the am79c976 device is busy. see figure 55. the am79c976 controller cannot service any slave ac- cess while it is reading the contents of the eeprom. simultaneous access is not allowed in order to avoid conflicts, since the eeprom is used to initialize some of the pci configuration space locations and user-se- lected bcrs and csrs. the eeprom read operation will always happen automatically following h_reset. (see the h_reset section for more details.) in addi- tion, the host can start the read operation by setting the pread bit (bcr19, bit 14). while the eeprom read is on-going, the am79c976 controller will disconnect any slave access where it is the target by asserting stop together with devsel , while driving trdy high. stop will stay asserted until the end of the cycle. note: the i/o and memory slave accesses will only be disconnected if they are enabled by setting the ioen or memen bit in the pci command register. without the enable bit set, the cycles will not be claimed at all. since h_reset clears the ioen and memen bits for the automatic eeprom read after h_reset, the dis- connect only applies to configuration cycles. the am79c976 device will also generate pci discon- nect/retry cycles when it is executing a blocking read access to an external phy register. 38 am79c976 8/01/00 preliminary )* (( $( + $ the am79c976 controller does not support burst ac- cess to the configuration space, the first 32 bytes of its i/o or memory space, or to the expansion bus. the host indicates a burst transaction by keeping frame asserted during the data phase. when the am79c976 controller sees frame and irdy asserted in the clock cycle before it wants to assert trdy , it also asserts stop at the same time. the transfer of the first data phase is still successful, since irdy and trdy are both asserted. see figure 66. ,* (( - . if the host is not yet ready when the am79c976 control- ler asserts trdy , the device will wait for the host to as- sert irdy . when the host asserts irdy and frame is still asserted, the am79c976 controller will finish the first data phase by deasserting trdy one clock later. at the same time, it will assert stop to signal a discon- nect to the host. stop will stay asserted until the host removes frame . see figure 77. frame clk ad irdy trdy c/be devsel stop 1 2345 cmd par par par be data addr 22929b7 frame clk ad irdy trdy c/be devsel stop 1 2345 be par par par be data 1st data 22929b8 8/01/00 am79c976 39 preliminary /* (( - . 0 $% ' when the am79c976 controller is not the current bus master, it samples the ad[31:0], c/be [3:0], and the par lines during the address phase of any pci com- mand for a parity error. when it detects an address par- ity error, the controller sets perr (pci status register, bit 15) to 1. when reporting of that error is enabled by setting serren (pci command register, bit 8) and perren (pci command register, bit 6) to 1, the am79c976 controller also drives the serr signal low for one clock cycle and sets serr (pci status register, bit 14) to 1. the assertion of serr follows the address phase by two clock cycles. the am79c976 controller will not assert devsel for a pci transaction that has an address parity error when perren and serren are set to 1. see figure 88. 1 0 $% ' during the data phase of an i/o write, memory-mapped i/o write, or configuration write command that selects the am79c976 controller as target, the device samples the ad[31:0] and c/be [3:0] lines for parity on the clock edge, and data is transferred as indicated by the asser- tion of irdy and trdy . par is sampled in the following clock cycle. if a parity error is detected and reporting of that error is enabled by setting perren (pci com- mand register, bit 6) to 1, perr is asserted one clock later. the parity error will always set perr (pci status register, bit 15) to 1 even when perren is cleared to 0. the am79c976 controller will finish a transaction that has a data parity error in the normal way by assert- ing trdy . the corrupted data will be written to the addressed location. figure 9 shows a transaction that suffered a parity error at the time data was transferred (clock 7, irdy and trdy are both asserted). perr is driven high at the beginning of the data phase and then drops low due to the parity error on clock 9, two clock cycles after the data was transferred. after perr is driven low, the am79c976 controller drives perr high for one clock cycle, since perr is a sustained tri-state signal. frame clk ad irdy trdy c/be devsel stop 1 23456 par be par par be data 1st data 22929b9 frame clk ad serr c/be devsel 1 2345 par par addr 1st data be cmd par 22929b10 40 am79c976 8/01/00 preliminary 2$(*0 $% ' master bus interface unit the master bus interface unit (biu) controls the acqui- sition of the pci bus and all accesses to the initializa- tion block, descriptor rings, and the receive and transmit buffer memory. table 3 shows the usage of pci commands by the am79c976 controller in master mode. (3 the am79c976 logic will determine when a dma transfer should be initiated. the first step in any am79c976 bus master transfer is to acquire ownership of the bus. this task is handled by synchronous logic within the biu. bus ownership is requested with the req signal and ownership is granted by the arbiter through the gnt signal. figure 10 shows the am79c976 controller bus acquisi- tion. req is asserted and the arbiter returns gnt while another bus master is transferring data. the am79c976 controller waits until the bus is idle (frame and irdy deasserted) before it starts driving ad[31:0] and c/be [3:0] on clock 5. frame is asserted at clock 5 indicating a valid address and command on ad[31:0] and c/be [3:0]. req is deasserted at the same time that frame is asserted. the am79c976 controller does not use address stepping which is reflected by adstep (bit 7) in the pci command register being hardwired to 0. # *# there are four primary types of dma transfers. the am79c976 controller uses non-burst as well as burst cycles for read and write access to the main memory. the am79c976 controller uses non-burst cycles to ac- cess descriptors when swstyle (bcr20, bits 7-0) is 0 or 2. all am79c976 controller non-burst read ac- cesses are of the pci command type memory read (type 6). note that during a non-burst read operation, all byte lanes will always be active. the am79c976 controller will internally discard unneeded bytes. frame clk ad irdy trdy c/be devsel par addr cmd par 1 2345678 10 9 data par be perr 22929b11 8/01/00 am79c976 41 preliminary table 3. pci commands 4 (3 the am79c976 controller typically performs more than one non-burst read transaction within a single bus mas- tership period. frame is dropped between consecu- tive non-burst read cycles. req , however, stays asserted until frame is asserted for the last transac- tion. the am79c976 controller supports zero wait- state read cycles. it asserts irdy immediately after the address phase and at the same time starts sampling devsel . figure 11 shows two non-burst read transac- tions. the first transaction has zero wait states. in the second transaction, the target extends the cycle by as- serting trdy one clock later. the am79c976 controller supports burst mode for all bus master read operations. to allow burst transfers in descriptor read operations, the am79c976 controller must be programmed to use swstyle 3, 4, or 5 (bcr20, bits 7-0). the biu chooses which pci command to use as fol- lows: when reading one dword, use memory read. when reading a block of more than one dword that does not cross a cache line, use memory read line. when reading a block that crosses a cache line boundary, use memory read multiple. c[3:0] command use 0000 interrupt acknowledge not used 0001 special cycle not used 0010 i/o read not used 0011 i/o write not used 0100 reserved 0101 reserved 0110 memory read read of the initialization block and descriptor rings read of the transmit buffer in non-burst mode 0111 memory write write to the descriptor rings and to the receive buffer 1000 reserved 1001 reserved 1010 configuration read not used 1011 configuration write not used 1100 memory read multiple read of descriptor or transmit buffer in burst mode 1101 dual address cycle used when required 1110 memory read line read of descriptor or transmit buffer in burst mode 1111 memory write invalidate burst write of 1 or more complete cache lines to the receive buffer 22929b12 frame clk ad irdy c/be req gnt 1 2345 cmd addr 42 am79c976 8/01/00 preliminary - the fifo thresholds should be greater than or equal to the cache line size to maximize the use of the mrl and mrm commands. if the pci bridge stops a transfer, the am79c976 device waits until the fifo threshold con- ditions are met before resuming the transfer. during the address phase of a burst access, ad[1:0] will both be 0 indicating a linear burst order. note that during a burst read operation, all byte lanes will always be active. the am79c976 controller will internally dis- card unneeded bytes. the am79c976 controller will always perform only a single burst read transaction per bus mastership pe- riod, where transaction is defined as one address phase and one or multiple data phases. the am79c976 controller supports zero wait state read cy- cles. it asserts irdy immediately after the address phase and at the same time starts sampling devsel . frame is deasserted when the next-to-last data phase is completed. the device may insert irdy wait states in the middle of a burst read transaction. figure 12 shows a typical burst read access. the am79c976 controller arbitrates for the bus, is granted access, reads three 32-bit words (dword) from the sys- tem memory, and then releases the bus. in the exam- ple, the memory system extends the data phase of each access by one wait state. the am79c976 controller uses non-burst cycles to write descriptors when swstyle (bcr20, bits 7-0) is 0 or 2. all am79c976 controller non-burst write ac- cesses are of the pci command type memory write (type 7). the byte enable signals indicate the byte lanes that have valid data.the am79c976 controller may perform more than one non-burst write transaction within a single bus mastership period. frame is dropped between consecutive non-burst write cycles. req , however, stays asserted until frame is asserted for the last transaction. the am79c976 supports zero wait state write cycles. (see the section descriptor dma transfers for the only exception.) it asserts irdy immediately after the address phase. figure 13 shows two non-burst write transactions. the first transaction has two wait states. the am79c976 device supports zero wait state non-burst write cycles. frame clk ad irdy trdy c/be devsel req gnt par devsel is sampled addr 0110 par 1 2345678 10 9 11 data addr data par par par 0000 0110 0000 22929b13 8/01/00 am79c976 43 preliminary frame clk ad irdy trdy c/be devsel req gnt par devsel is sampled addr 0000 1110 par 1 2345678 10 9 11 data data data par par par 22929b14 44 am79c976 8/01/00 preliminary - the am79c976 controller supports burst mode for all bus master write operations. to allow burst transfers in descriptor write operations, the am79c976 controller must be programmed to use swstyle 3, 4, or 5 (bcr20, bits 7-0). the controller uses the following rules to determine whether to use the pci memory write (mw) command or the memory write and invalidate (mwi) command for burst write transfers. ? when a transfer starts on a cache line boundary, and there is at least a cache line of data to trans- fer, use mwi. ? when a transfer does not start on a cache line boundary, use mw. (the external pci bridge should stop the transfer at the cache line bound- ary if it can make good use of the mwi com- mand.) ? stop the mwi transfer at a cache line boundary if there is less than 1 cache line of data left to transfer. the receive fifo threshold should be greater than or equal to the cache line size to maximize the use of the mwi command. if the pci bridge stops a transfer, the am79c976 device waits until the fifo threshold con- ditions are met before resuming the transfer. during the address phase of a burst write transfer ad[1:0] will both be 0 indicating a linear burst order. the byte enable signals indicate which byte lanes have valid data. the am79c976 controller will always perform a single burst write transaction per bus mastership period, where transaction is defined as one address phase and one or multiple data phases. the am79c976 controller supports zero wait state write cycles when using the memory write command. when using memory write and invalidate commands, the device may insert irdy wait states anywhere in the transaction. the device asserts irdy immediately after the address phase and at the same time starts sampling devsel . frame is deasserted when the next-to-last data phase is completed. figure 14 shows a typical burst write access. the am79c976 controller arbitrates for the bus, is granted access, and writes four 32-bit words (dwords) to the system memory and then releases the bus. in this ex- frame clk ad irdy trdy c/be devsel req gnt par devsel is sampled addr 0111 par 1 2345678 10 9 data addr data par par par be 0111 be 22929b15 8/01/00 am79c976 45 preliminary ample, the memory system extends the data phase of the first access by one wait state. the following three data phases take one clock cycle each, which is deter- mined by the timing of trdy . *# ! the biu has two programmable features that can im- prove the dma performance with pci bridges that do not automatically stop burst transfers to align them with cache line boundaries: 1. the burst alignment (ba) bit (ctrl0, bit 0). when this bit is set, if a burst transfer starts in the middle of a cache line, the transfer will stop at the first cache line boundary. 2. the burst limit register (ctrl0, bits 3:0). this 4- bit register limits the maximum length of a burst transfer. if the contents of this register are 0, the burst length is limited by the amount of data avail- able or by the amount of fifo space available. if the contents of this register are not zero, a burst transfer will end when the transfer has crossed the number of cache line boundaries equal to the con- tents of this register. ! when the am79c976 controller is a bus master, the cy- cles it produces on the pci bus may be terminated by the target in one of three different ways: disconnect with data transfer, disconnect without data transfer, and target abort. figure 15 shows a disconnection in which one last data transfer occurs after the target asserted stop . stop is asserted on clock 4 to start the termination se- quence. data is still transferred during this cycle, since both irdy and trdy are asserted. the am79c976 controller terminates the current transfer with the deas- sertion of frame on clock 5 and of irdy one clock later. it finally releases the bus on clock 7. the am79c976 controller will again request the bus after two clock cycles, if it wants to transfer more data. the starting address of the new transfer will be the address of the next non-transferred data. " frame clk ad irdy trdy c/be devsel req gnt 12345678 addr data data data be 0111 9 par par par par par data par devsel is sampled 22929b16 46 am79c976 8/01/00 preliminary )* (( +* figure 16 shows a target disconnect sequence during which no data is transferred. stop is asserted on clock 4 without trdy being asserted at the same time. the am79c976 controller terminates the access with the deassertion of frame on clock 5 and of irdy one clock cycle later. it finally releases the bus on clock 7. the am79c976 controller will again request the bus after two clock cycles to retry the last transfer. the starting address of the new transfer will be the address of the last non-transferred data. frame clk ad irdy trdy c/be devsel req gnt par devsel is sampled addr i 0000 0111 par 0111 23456789 11 10 par data stop addr i +8 data 1 22929b17 8/01/00 am79c976 47 preliminary ,* (( +* figure 17 shows a target abort sequence. the target asserts devsel for one clock. it then deasserts devsel and asserts stop on clock 4. a target can use the target abort sequence to indicate that it can- not service the data transfer and that it does not want the transaction to be retried. additionally, the am79c976 controller cannot make any assumption about the success of the previous data transfers in the current transaction. the am79c976 controller termi- nates the current transfer with the deassertion of frame on clock 5 and of irdy one clock cycle later. it finally releases the bus on clock 6. since data integrity is not guaranteed, the am79c976 controller cannot recover from a target abort event. the am79c976 controller will reset all csr locations to their stop_reset values. the bcr and pci configuration registers will not be cleared. any on-going network transmission is terminated with the current fcs invert- ed and appended at the next byte boundary. this guar- antees that the receiving station will drop the truncated frame. frame clk ad irdy trdy c/be devsel req gnt par devsel is sampled stop addr i 0000 0111 par 0111 23456789 11 10 addr i data par 1 22929b18 48 am79c976 8/01/00 preliminary / 5 rtabort (pci status register, bit 12) will be set to indicate that the am79c976 controller has received a target abort. in addition, sint (csr5, bit 11) will be set to 1. when sint is set, inta is asserted if the enable bit sinte (csr5, bit 10) is set to 1. this mechanism can be used to inform the driver of the system error. the host can read the pci status register to determine the exact cause of the interrupt. # ! there are three scenarios besides normal completion of a transaction where the am79c976 controller will terminate the cycles it produces on the pci bus. when the am79c976 controller performs multiple non- burst transactions, it keeps req asserted until the as- sertion of frame for the last transaction. when gnt is removed, the am79c976 controller will finish the cur- rent transaction and then release the bus. if it is not the last transaction, req will remain asserted to regain bus ownership as soon as possible. see figure 1818. when the am79c976 controller operates in burst mode, it only performs a single transaction per bus mastership period, where transaction is defined as one address phase and one or multiple data phases. the central arbiter can remove gnt at any time during the transaction. the am79c976 controller will ignore the deassertion of gnt and continue with data transfers, as long as the pci latency timer is not expired. when the latency timer is 0 and gnt is deasserted, the am79c976 controller will finish the current data phase, deassert frame , finish the last data phase, and re- lease the bus. it will immediately assert req to regain bus ownership as soon as possible. when the preemption occurs after the counter has counted down to 0, the am79c976 controller will finish the current data phase, deassert frame , finish the last data phase, and release the bus. note that it is im- portant for the host to program the pci latency timer according to the bus bandwidth requirement of the am79c976 controller. the host can determine this bus bandwidth requirement by reading the pci max_lat and min_gnt registers. frame clk ad irdy trdy c/be devsel req gnt par devsel is sampled 234567 addr 0000 0111 par par data stop 1 22929b19 8/01/00 am79c976 49 preliminary 10!' * - ( if the controller is executing a memory write and inval- idate instruction when preemption occurs, the control- ler will finish writing the current cache line before it releases the bus. figure 19 assumes that the pci latency timer has counted down to 0 on clock 7. # 5 the am79c976 controller will terminate its cycle with a master abort sequence if devsel is not asserted within 4 clocks after frame is asserted. master abort is treated as a fatal error by the am79c976 controller. the am79c976 controller will reset all csr locations to their stop_reset values. the bcr and pci con- figuration registers will not be cleared. any on-going network transmission is terminated in an orderly se- quence. the message will have the current fcs in- verted and appended at the next byte boundary to guarantee that the receiving station will treat the trans- mission either as a runt or as a corrupted frame. rmabort (in the pci status register, bit 13) will be set to indicate that the am79c976 controller has termi- nated its transaction with a master abort. in addition, sint (csr5, bit 11) will be set to 1. when sint is set, inta is asserted if the enable bit sinte (csr5, bit 10) is set to 1. this mechanism can be used to inform the driver of the system error. the host can read the pci status register to determine the exact cause of the in- terrupt. see figure 2020. frame clk ad irdy trdy c/be devsel req gnt 1 234567 be 0111 par par devsel is sampled par data addr 22929b20 50 am79c976 8/01/00 preliminary 20!' * ( frame clk ad irdy trdy c/be devsel par devsel is sampled addr be 0111 par 1 234 5 6 78 9 data par req data data data data par par par par gnt 22929b21 8/01/00 am79c976 51 preliminary 4# 5 0 $% ' during every data phase of a dma read operation, when the target indicates that the data is valid by as- serting trdy , the am79c976 controller samples the ad[31:0], c/be [3:0] and the par lines for a data parity error. when it detects a data parity error, the controller sets perr (pci status register, bit 15) to 1. when re- porting of that error is enabled by setting perren (pci command register, bit 6) to 1, the am79c976 controller also drives the perr signal low and sets dataperr (pci status register, bit 8) to 1. the asser- tion of perr follows the corrupted data/byte enables by two clock cycles and par by one clock cycle. figure 21 shows a transaction that has a parity error in the data phase. the am79c976 controller asserts perr on clock 8, two clock cycles after data is valid. the data on clock 5 is not checked for parity, since on a read access par is only required to be valid one clock after the target has asserted trdy . the am79c976 controller then drives perr high for one clock cycle, since perr is a sustained tri-state signal. during every data phase of a dma write operation, the am79c976 controller checks the perr input to see if the target reports a parity error. when it sees the perr input asserted, the controller sets perr (pci status register, bit 15) to 1. when perren (pci command register, bit 6) is set to 1, the am79c976 controller also sets dataperr (pci status register, bit 8) to 1. frame clk ad irdy trdy c/be devsel par devsel is sampled addr 0111 par 1 234 5 6 78 9 data par req gnt 0000 22929b22 52 am79c976 8/01/00 preliminary # $(*0 $% ' whenever the am79c976 controller is the current bus master and a data parity error occurs, sint (csr5, bit 11) will be set to 1. when sint is set, inta is asserted if the enable bit sinte (csr5, bit 10) is set to 1. this mechanism can be used to inform the driver of the sys- tem error. the host can read the pci status register to determine the exact cause of the interrupt. the setting of sint due to a data parity error is not dependent on the setting of perren (pci command register, bit 6). by default, a data parity error does not affect the state of the mac engine. the am79c976 controller treats the data in all bus master transfers that have a parity error as if nothing has happened. all network activity contin- ues. 6 (7*# during execution of the am79c976 controller bus mas- ter initialization procedure, the am79c976 controller will use a burst transfer of seven dwords to read the ini- tialization block. ad[1:0] is 0 during the address phase indicating a linear burst order. * ( '*# during descriptor read accesses, the byte enable sig- nals will indicate that all byte lanes are active. should some of the bytes not be needed, then the am79c976 controller will internally discard the extraneous informa- tion that was gathered during such a read. the settings of swstyle (bcr20, bits 7-0) affect the way the am79c976 controller performs descriptor read operations. because of the order in which the descriptor data must be read or written when swstyle is set to 0 or 2, all descriptor read operations are performed in non-burst mode. see figure 2222. frame clk ad irdy trdy c/be devsel par devsel is sampled addr be 0111 par 1 234 5 6 78 9 data par perr 22929b23 8/01/00 am79c976 53 preliminary * ( ' - # when swstyle is set to 3, 4, or 5 the descriptor en- tries are ordered to allow burst transfers, and the am79c976 controller will perform all descriptor read operations in burst mode. the device may read more than one descriptor in a single burst. see figure 23. frame clk ad irdy trdy c/be devsel req gnt par devsel is sampled md1 0000 0110 par par data data md0 0000 0110 par par 1 2345678 10 9 22929b24 54 am79c976 8/01/00 preliminary * ( ' # table 4 shows the descriptor read sequence. during descriptor write accesses, only the byte lanes which need to be written are enabled. the settings of swstyle (bcr20, bits 7-0) affect the way the am79c976 controller performs descriptor write operations. when swstyle is set to 0 or 2, all descriptor write op- erations are performed in non-burst mode. when swstyle is set to 3, 4, or 5, the descriptor en- tries are ordered to allow burst transfers. the am79c976 controller will perform all descriptor write operations in burst mode. see table 5 for the descriptor write sequence. table 4. descriptor read sequence frame clk ad irdy trdy c/be devsel req gnt 1 234567 md1 0000 0110 par par par data data par devsel is sampled 22929b25 swstyle bcr20 [7:0] ad bus sequence for rx descriptors ad bus sequence for tx descriptors 0 address = xxxx xx00h turn around cycle data idle address = xxxx xx04h turn around cycle data address = xxxx xx00h turn around cycle data idle address = xxxx xx04h turn around cycle data 2 address = xxxx xx04h turn around cycle data idle address = xxxx xx00h turn around cycle data address = xxxx xx04h turn around cycle data idle address = xxxx xx00h turn around cycle data 3 address = xxxx xx04h turn around cycle data data address = xxxx xx04h turn around cycle data data 4 address = xxxx xx04h turn around cycle data data address = xxxx xx00h turn around cycle data data data 5 address = xxxx xx08h turn around cycle data data data address = xxxx xx00h turn around cycle data data data data 8/01/00 am79c976 55 preliminary table 5. descriptor write sequence note: figure 24 assumes that the am79c976 control- ler is programmed to use 32-bit software structures (swstyle = 2, 3, 4, or 5). the byte enable signals for the second data transfer would be 0111b, if the device was programmed to use 16-bit software structures (swstyle = 0). swstyle bcr20[7: 0] ad bus sequence for rx descriptor ad bus sequence for tx descriptor 0 address = xxxx xx04h data idle address = xxxx xx00h data address = xxxx xx04h data idle address = xxxx xx00h data 2 address = xxxx xx08h data idle address = xxxx xx04h data address = xxxx xx08h data idle address = xxxx xx04h data 3 address = xxxx xx00h data data address = xxxx xx00h data data 4 address = xxxx xx00h data address = xxxx xx00h data 5 address = xxxx xx00h data address = xxxx xx00h data 56 am79c976 8/01/00 preliminary "* ( ' - # frame clk ad irdy trdy c/be devsel req gnt par devsel is sampled md2 0000 0111 par md1 0011 0111 par 1 2345678 10 9 data par par data 22929b26 8/01/00 am79c976 57 preliminary )* ( ' # *# am79c976 logic will determine when a fifo dma transfer is required. this transfer mode will be used for transfers of data to and from the am79c976 fifos. once the am79c976 biu has been granted bus mas- tership, it will perform a series of consecutive transfer cycles before relinquishing the bus. all transfers within the master cycle will be either read or write cycles, and all transfers will be transferred to contiguous, ascend- ing addresses. burst cycles are used whenever possi- ble. a burst transaction will start with an address phase, fol- lowed by one or more data phases. ad[1:0] will always be 0 during the address phase indicating a linear burst order. during fifo dma read operations, all byte lanes will always be active. the am79c976 controller will inter- nally discard unused bytes. during the first and the last data phases of a fifo dma burst write operation, one or more of the byte enable signals may be inactive. all other data phases will always write a complete dword. figure 26 shows the beginning of a fifo dma write with the beginning of the buffer not aligned to a dword boundary. the am79c976 controller starts off by writ- ing only three bytes during the first data phase. this op- eration aligns the address for all other data transfers to a 32-bit boundary so that the am79c976 controller can continue bursting full dwords. gnt req devsel trdy par c/be frame clk 35 par ad irdy devsel is sampled data 1 2 4 6 7 8 0110 0000 0011 md2 par data par 22929b27 58 am79c976 8/01/00 preliminary , if a receive buffer does not end on a dword boundary, the am79c976 controller will perform a non-dword write on the last transfer to the buffer. figure 27 shows the final three fifo dma transfers to a receive buffer. since there were only 9 bytes of space left in the re- ceive buffer, the am79c976 controller bursts three data phases. the first two data phases write a full dword, the last one only writes a single byte. frame clk ad irdy trdy c/be devsel req gnt 1 23456 0000 0111 par par par devsel is sampled 0001 par data data data add 22929b28 8/01/00 am79c976 59 preliminary / % note that the am79c976 controller will always perform a dword transfer as long as it owns the buffer space, even when there are less than four bytes to write. for example, if there is only one byte left for the current re- ceive frame, the am79c976 controller will write a full dword, containing the last byte of the receive frame in the least significant byte position (bswp is cleared to 0, csr3, bit 2). the content of the other three bytes is undefined. the message byte count in the receive descriptor always reflects the exact length of the re- ceived frame. in the normal dma mode (when the burst alignment bit = 0 and the burst limit register contents = 0) the am79c976 controller will continue transferring fifo data until the transmit fifo is filled to its high threshold (for read transfers) or the receive fifo is emptied to its low threshold (for write transfers), or until the am79c976 controller is preempted and the pci la- tency timer is expired. the host should use the values in the pci min_gnt and max_lat registers to deter- mine the value for the pci latency timer. in the burst alignment mode (when the burst alignment bit = 1) if a burst transfer starts in the middle of a cache line, the transfer will stop at the first cache line boundary. if the contents of the burst limit register are not zero, a burst transfer will end when the transfer has crossed the number of cache line boundaries equal to the con- tents of this register. the exact number of total transfer cycles in the bus mastership period is dependent on all of the following variables: the settings of the fifo watermarks, the conditions of the fifos, the latency of the system bus to the am79c976 controller ? s bus request, and the speed of bus operation. the trdy response time of the memory device will also affect the number of trans- fers, since the speed of the accesses will affect the state of the fifo. the general rule is that the longer the bus grant latency, the slower the bus transfer opera- tions; the slower the clock speed, the higher the trans- mit watermark; or the lower the receive watermark, the longer the total burst length will be. when a fifo dma burst operation is preempted, the am79c976 controller will not relinquish bus ownership until the pci latency timer expires. descriptor management unit the descriptor management unit (dmu) implements the automatic initialization procedure and manages the descriptors and buffers. 6 the am79c976 controller is initialized by a combina- tion of eeprom register writes, direct register writes from the pci bus and, for compatibility with older pcnet family products, dma reads from an initialization block in memory. the registers that must be programmed de- pend on the features that are required in a particular application. see user accessible registers on page 111 for more details. the format of the legacy initialization block depends on the programming of the swstyle register, as de- scribed in the initialization block section. the initialization block is read when the init bit in csr0 is set. the init bit should be set before or con- current with the strt bit to ensure correct operation. once the initialization block has been completely read in and internal registers have been updated, idon will be set in csr0, generating an interrupt (if iena is set). the am79c976 controller obtains the start address of the initialization block from the contents of csr1 (least significant 16 bits of address) and csr2 (most signifi- cant 16 bits of address). the host must write csr1 and csr2 before setting the init bit. the initialization block contains the user defined conditions for am79c976 op- eration, together with the base addresses and length information of the transmit and receive descriptor rings. frame clk ad irdy trdy c/be devsel req gnt 1 234567 0000 0111 par par par par devsel is sampled 1110 par data data data add 60 am79c976 8/01/00 preliminary - 6 earlier members of the pcnet family of controllers had to be re-initialized if the transmitter and/or the receiver were not turned on during the original initialization, and it was subsequently required to activate them, or if ei- ther section was shut off due to the detection of a mem- ory error, transmitter underflow, or transmit buffer error condition. this restriction does not apply to the am79c976 device. the memory error and transmit buffer error conditions cannot occur in the am79c976 controller and the transmit underflow condition does not stop the am79c976 controller ? s transmitter. for compatibility with other pcnet family devices, re- initialization may be done via the initialization block or by setting the stop bit in csr0, followed by writing to csr15, and then setting the strt bit in csr0. note that this form of restart will not perform the same in the am79c976 controller as in the c-lance device. in particular, setting the strt bit causes the am79c976 controller to reload the transmit and receive descriptor pointers with their respective base addresses. this means that the software must clear the descriptor own bits and reset its descriptor ring pointers before restarting the am79c976 controller. the reload of de- scriptor base addresses is performed in the c-lance device only after initialization, so that a restart of the c-lance without initialization leaves the c-lance pointing at the same descriptor locations as before the restart. ' following reset, the transmitter and receiver of the am79c976 controller are disabled, so no descriptor or data dma activity will occur. the receiver will process incoming frames to detect address matches, which are counted in the rcvmisspkts register. no transmits will occur except that pause frames may be sent (see flow control section). setting the run bit in cmd0 (equivalent to setting strt in csr0) causes the am79c976 controller to begin descriptor polling and normal transmit and re- ceive activity. clearing the run bit (equivalent to set- ting stop in csr0) causes the am79c976 controller to halt all transmit, receive, and dma transfer activities abruptly. the am79c976 controller offers suspend modes that allow stopping the device with orderly termination of all network activity. transmit and receive are controlled separately. setting the rx_fast_spnd bit in cmd0 suspends re- ceiver activity after the current frame being received by the mac is complete. if no frame is being received when rx_fast_spnd is set, the receiver is sus- pended immediately. after the receiver is suspended, the rx_suspended bit in stat0 is set and spnd- int interrupt bit in int0 is set. receive data and de- scriptor dma activity continues normally while the receiver is fast suspended. setting the rx_spnd bit in cmd0 suspends the re- ceiver in the same way as rx_fast_spnd, but the rx_suspened bit and spndint interrupt bit are only set after any frames in the receive fifo have been completely transferred into system memory and the corresponding descriptors updated. no receive data or descriptor dma activity will occur while the receiver is suspended. when the receiver is suspended, no frames will be re- ceived into the receive fifo, but frames will be checked for address match and the rcvmisspkts counter incremented appropriately, and frames will be checked for magic packet match if magic packet mode is enabled. setting the tx_fast_spnd bit in cmd0 suspends transmitter activity after the current frame being trans- mitted by the mac is complete. if no frame is being transmitted when tx_fast_spnd is set, the transmit- ter is suspended immediately. after the transmitter is suspended, the tx_suspended bit in stat0 is set and spndint interrupt bit in int0 is set. transmit de- scriptor and data dma activity continues normally while the transmitter is fast suspended. setting the tx_spnd bit in cmd0 suspends the trans- mitter in the same way as tx_fast_spnd, but the tx_suspended bit and spndint interrupt bit are only set after any frames in the transmit fifo have been completely transmitted. no transmit descriptor or data dma activity will occur while the transmitter is sus- pended. when the transmitter is suspended, no frames will be transmitted except for flow control frames (see flow control section). it is not meaningful to set both tx_spnd and tx_fast_spnd at the same time, nor is it meaningful to set both rx_spnd and rx_fast_spnd at the same time. doing so will cause unpredictable results. however, transmit and receive are independent of each other, so one may be suspended or fast suspended while the other is running, suspended or fast sus- pended. for compatibility with other pcnet family devices, set- ting the spnd bit in csr5 with fastspnde in csr7 cleared is equivalent to setting both tx_spnd and rx_spnd and clearing spnd with fastspnde cleared is equivalent to clearing both tx_spnd and rx_spnd. similarly, setting spnd with fastspnde set is equivalent to setting both tx_fast_spnd and rx_fast_spnd and clearing spnd with fastspnde set is equivalent to clearing both tx_fast_spnd and rx_fast_spnd. while equiva- lent, these methods are not identical, so software 8/01/00 am79c976 61 preliminary should not mix the csr5/csr7 method with the cmd0 method. for compatibility with other pcnet family devices, after the spnd bit in csr5 is set, it will read back a one only after the suspend operation is complete, that is, after both tx_suspended and rx_suspended in stat0 have been set. it is recommended that when software polls this register that a delay be inserted be- tween polls. continuous polling will reduce the bus bandwidth available to the am79c976 controller and will delay the completion of the suspend operation. it is recommended that software use the spndint in- terrupt to determine when the am79c976 controller has suspended after one or more suspend bits have been set. this results in the least competition for the pci bus and thus the shortest time from setting of a suspend bit until completion of the suspend operation. clearing the run bit in cmd0 will generate a pulse that will clear all the suspend command and status bits (tx_spnd, rx_spnd, tx_fast_spnd and rx_fast_spnd in cmd0, tx_suspended and rx_suspended in stat0, spnd in csr5 and drx and dtx in csr15). the rx_spnd or tx_spnd bits may then be set while run is cleared. when run is subsequently set, the suspend bit will remain set and the corresponding operation (transmit or receive) will be disabled. since the suspend bit will be cleared when run is cleared, this must be done each time run is set. since the suspend bits and run are in the same register (cmd0), the suspend bit may be set at the same time that run is set. for compatibility with other pcnet family devices, set- ting the stop bit in csr0 will also clear the spnd bit in csr5. while stop is set, the drx or dtx bits in csr15 may be set. when the strt bit in csr0 is sub- sequently set, the corresponding operation will be dis- abled. since the bits are all cleared when stop is set, csr15 must be written (either directly or indirectly via the dma initialization) each time before strt is set again. the suspend bits in cmd0 and stat0 are equivalent but not identical to the suspend bits in csr5, csr7 and csr15. software should use one set of bits or the other and not mix them. the spndint bit in int0 has no equivalent in the csr registers, so this bit may be used to detect the completion of a suspend operation initiated by the spnd bit in csr5. * ( '# ! descriptor management is accomplished through mes- sage descriptor entries organized as ring structures in memory. there are two descriptor rings, one for trans- mit and one for receive. each descriptor describes a single buffer. a frame may occupy one or more buffers. if multiple buffers are used, this is referred to as buffer chaining. * ( ' each descriptor ring must occupy a contiguous area of memory. during initialization, the user-defined base address for the transmit and receive descriptor rings, as well as the number of entries contained in the de- scriptor rings are set up. the programming of the soft- ware style (swstyle, bcr20, bits 7-0) affects the way the descriptor rings and their entries are arranged. when swstyle is at its default value of 0, the de- scriptor rings are backwards compatible with the am79c90 c-lance and the am79c96x pcnet-isa family. the descriptor ring base addresses must be aligned to 8-byte boundaries. each ring entry contains a subset of the three 32-bit transmit or receive mes- sage descriptors that are organized as four 16-bit structures (ssize32 (bcr20, bit 8) is set to 0). note that even though the am79c976 controller treats the descriptor entries as 16-bit structures, it will always perform 32-bit bus transfers to access the descriptor entries. the value of csr2, bits 15-8, is used as the upper 8-bits for all memory addresses during bus mas- ter transfers. when swstyle is set to 2, 3, or 4, the descriptor ring base addresses must be aligned to 16-byte bound- aries. each ring entry is organized as three 32-bit mes- sage descriptors (ssize32 (bcr20, bit 8) is set to 1). the fourth dword is reserved for user software pur- poses. when swstyle is set to 3, 4, or 5, the order of the message descriptors is optimized to allow read and write access in burst mode. when swstyle is set to 5, the descriptor ring base addresses must be aligned to a 32-byte boundary. each ring entry is organized as eight 32-bit message descriptors (ssize32 (bcr20, bit 8) is set to 1). descriptor ring lengths can be set up either by writing directly to the transmit and receive ring length registers (csr76, csr78) or by using the initialization block. if the initialization block is used to set up ring lengths, the ring lengths are restricted to powers of two that are less than or equal to 128 if swstyle is 0 or 512 if sw- style is 2 or 3. however, ring lengths of any size up to 65535 descriptors can be set up by writing directly to the transmit and receive ring length registers. the initialization block can not be used if swstyle is 4 or 5. the descriptor ring lengths must be initialized by writing directly to the appropriate registers. each ring entry contains the following information: 62 am79c976 8/01/00 preliminary to permit the queuing and de-queuing of message buffers, ownership of each buffer is allocated to either the am79c976 controller or the host. the own bit within the descriptor status information, either tmd or rmd, is used for this purpose. setting the own to 1 signifies that the am79c976 con- troller currently has ownership of this ring descriptor and its associated buffer. only the owner is permitted to relinquish ownership or to write to any field in the de- scriptor entry. a device that is not the current owner of a descriptor entry cannot assume ownership or change any field in the entry. a device may, however, read from a descriptor that it does not currently own. software should always read descriptor entries in sequential or- der. when software finds that the current descriptor is owned by the am79c976 controller, then the software must not read ahead to the next descriptor. the soft- ware should wait at a descriptor it does not own until the am79c976 controller sets own to 0 to release ownership to the software. (when lappen (csr3, bit 5) is set to 1, this rule is modified. see the lappen de- scription. at initialization, the base address of the receive de- scriptor ring is written to csr24 (lower 16 bits) and csr25 (upper 16 bits), and the base address of the transmit descriptor ring is written to csr30 and csr31. figure 28 illustrates the relationship between the initial- ization base address, the initialization block, the re- ceive and transmit descriptor ring base addresses, the receive and transmit descriptors, and the receive and transmit data buffers, when ssize32 is cleared to 0. 1,- 8# initialization block iadr[15:0] iadr[31:16] csr1 csr2 tdra[15:0] mod padr[15:0] padr[31:16] padr[47:32] ladrf[15:0] ladrf[31:16] ladrf[47:32] ladrf[63:48] rdra[15:0] rle res rdra[23:16] tle res tdra[23:16] rcv buffers rmdo rmd1 rmd2 rmd3 rcv descriptor ring n n n n 1st desc. 2nd desc. rmd0 xmt buffers tmd0 tmd1 tmd2 tmd3 xmt descriptor ring m m m m 1st desc. 2nd desc. tmd0 data buffer n data buffer 1 data buffer 2 data buffer m data buffer 1 data buffer 2 8/01/00 am79c976 63 preliminary note that in this mode the value of csr2, bits 15-8, is used as the upper 8-bits for all memory addresses dur- ing bus master transfers. figure 29 illustrates the relationship between the initial- ization base address, the initialization block, the re- ceive and transmit descriptor ring base addresses, the receive and transmit descriptors, and the receive and transmit data buffers, when ssize32 is set to 1. 2 - 8# 0 if there is no network channel activity and there is no pre- or post-receive or pre- or post-transmit activity being performed by the am79c976 controller, then the am79c976 controller will periodically poll the current receive and transmit descriptor entries in order to as- certain their ownership. if the txdpoll bit in csr4 is set, then the transmit polling function is disabled. the descriptor management unit (dmu) is responsible for these operations. the am79c976 controller stores internally the informa- tion from two or more receive descriptors and two or more transmit descriptors. polling operations depend on the ownership of the current and next receive and transmit descriptors. when the poll time has elapsed, if the current receive descriptor is not owned by the am79c976 controller or if the current receive descriptor is owned and the next receive descriptor is not owned, the unowned descrip- tor will be polled. depending on the software style, more than one descriptor may be read in a burst. if the txdpoll bit is not set and the poll time has elapsed, or whenever the tdmd bit is set, if the current transmit descriptor is not owned by the am79c976 controller, it will be polled. depending on the software style, more than one descriptor may be read in a burst. if either transmit or receive or both are suspended or disabled due to the setting of tx_spnd, rx_spnd, spnd, drx or dtx, the corresponding descriptors will not be polled. polling is not affected by fast suspend. initialization block csr1 csr2 rmd0 rmd1 rmd2 rmd3 rcv descriptor ring n n n n 1st desc. start 2nd desc. start rmd0 tmd0 tmd1 tmd2 tmd3 xmt descriptor ring m m m m 1st desc. start 2nd desc. start tmd0 data buffer n data buffer 1 data buffer 2 data buffer m data buffer 2 data buffer 1 padr[31:0] iadr[31:16] iadr[15:0] tle res rle res mode padr[47:32] res ladrf[31:0] ladrf[63:32] rdra[31:0] tdra[31:0] rcv buffers xmt buffers 64 am79c976 8/01/00 preliminary receive descriptor polling will continue even if transmit polling is disabled by setting txdpoll. if at least two receive descriptors are owned by the am79c976 con- troller there will be no descriptor polling if there is no network activity. the user may change the poll time value from the de- fault value by modifying the value in the transmit poll- ing interval register (csr47). the default value is 0000h, which corresponds to a polling interval of 65,536 x 3 erclk clock periods or 2.185 ms when erclk = 90 mhz. when the am79c976 controller is in the process of re- ceiving a frame and it does not own the next descriptor or if it is in the process of transmitting a frame that does not end in the current descriptor and it does not own the next descriptor, it switches to the chain polling mode in which the polling interval is determined by the chain polling interval register (csr49). thus, the device can be programmed to poll at a faster rate when it is about to run out of buffers. ! 0 if, after a transmit descriptor access, the am79c976 controller finds that the own bit of that descriptor is not set, the am79c976 controller resumes the poll time count and re-examines the same descriptor at the next expiration of the poll time count. if the own bit of the descriptor is set, but the start of packet (stp) bit is not set, the am79c976 controller will immediately request the bus in order to clear the own bit of this descriptor. after resetting the own bit of this descriptor, the am79c976 controller will again immediately request the bus in order to access the next descriptor in the ring. if the own bit is set and the buffer length is 0, the own bit will be cleared. the am79c976 controller skips buff- ers with length of 0, which differs from the c-lance device, which interprets a buffer length of 0 to mean a 4096-byte buffer. for the am79c976 device a zero length buffer is acceptable anywhere in the buffer chain. if the own bit and stp are set, the dma controller will start reading data from the current transmit buffer. if the next transmit descriptor is not already known to be owned, the am79c976 controller will interleave a read of this descriptor into the sequence of data dma oper- ations. if the next transmit descriptor has the own bit set, the am79c976 controller will complete reading the data from the current transmit buffer, clear the own bit in the current descriptor and advance the internal ring pointer to make the next transmit descriptor the new current transmit descriptor. the am79c976 controller returns ownership of trans- mit descriptors to the software when the dma transfer of data from system memory to the am79c976 control- ler ? s memory is complete. this is different from older devices in the pcnet family, which will not return the last transmit descriptor of a frame (the one with enp=1) until transmission of the frame is complete. the am79c976 controller does not return any status information in the transmit descriptor, it will only write to the own bit to clear it. normally, the driver will set all the own bits of a frame in reverse order so that the am79c976 controller will never encounter the situation where the current trans- mit descriptor has own=1 and enp=0 and the next transmit descriptor has own=0. older devices in the pcnet family treat this condition as a fatal error. the am79c976 controller allows this mode of operation to permit dma of the beginning of a frame before pro- cessing of the entire frame is complete. the number of bytes in the first buffer(s) should be less than the trans- mit start point or the rex_uflo bit in cmd3 should be set. when the am79c976 controller encounters the condi- tion of the current transmit descriptor ? s own=1 and enp=0 and the next transmit descriptor ? s own=0, it enters the chain polling mode. in this mode, polling of the descriptor will occur at intervals determined by the chain polling interval register (csr49). setting the tdmd bit will also cause a poll. chain polling may be disabled by setting the chdpoll bit in csr7 or cmd2. note that this will also disable chain polling for receive descriptors. if underflow occurs due to delays in setting the own bits or excessive bus latency, the transmitter will ap- pend an inverted fcs field to the frame and will incre- ment the xmtunderrunpkts counter. the frame may be retransmitted (if the rex_uflo bit in cmd3 is set) or discarded. if an error occurs in the transmission that causes the frame to be discarded (late collision, underflow or retry failure with the corresponding retry or retransmit option not enabled) before the entire frame has been trans- ferred or if the current transmit descriptor has its kill bit set, and if current transmit descriptor does not have its enp bit set, the am79c976 controller will skip over the rest of the frame which experienced the error. the am79c976 controller will clear the own bit for all de- scriptors with own = 1 and stp = 0 and continue in like manner until a descriptor with own = 0 (no more transmit frames in the ring) or own = 1 and stp = 1 (the first buffer of a new frame) is reached. at the end of any transmit operation, whether success- ful or with errors, the am79c976 controller will always perform another polling operation, unless the next transmit descriptor is already known to be owned. 8/01/00 am79c976 65 preliminary by default, whenever the dma controller finishes copy- ing a transmit frame from system memory, it sets the tint bit of csr0 to indicate that the buffers are no longer needed. this causes an interrupt signal if the iena bit of csr0 has been set and the tintm bit of csr3 is cleared. the am79c976 controller provides two modes to re- duce the number of transmit interrupts. if the contents of the delayed interrupt register is not zero, the inter- rupt to the cpu will be postponed until a programmable number of interrupt events have occurred or a program- mable amount of time has elapsed since the first inter- rupt event occurred. another mode, which is enabled by setting ltinten (csr5, bit 14) to 1, allows sup- pression of interrupts for transmissions of all but the last frame in a sequence. ( 0 if the am79c976 controller does not own both the cur- rent and the next receive descriptor, then the am79c976 controller will continue to poll according to the polling sequence described in the transmit polling section. if the receive descriptor ring length is one, then there is no next descriptor to be polled. if a poll operation has revealed that the current and the next receive descriptors belong to the am79c976 con- troller, then additional poll accesses are not necessary. future poll operations will not include receive descrip- tor accesses as long as the am79c976 controller re- tains ownership of the current and the next receive descriptors. when receive activity is present on the channel, the am79c976 controller waits until the number of bytes specified in the rcv_protect register (default 64) have been received. if the frame is accepted based on all active addressing schemes at that time, the dmu is notified that a frame has been received. as receive buffers become available in system mem- ory, the dma controller will copy frame data from the re- ceive fifo into system memory. the am79c976 controller will set the stp bit in the first descriptor of a frame. if the frame length exceeds the length of the cur- rent buffer, the am79c976 controller will pass owner- ship back to the system by writing 0s to the own and enp bits of the descriptor when the first buffer is full. this activity continues until the am79c976 controller recognizes the completion of the frame (the last byte of this receive message has been removed from the fifo). the am79c976 controller will subsequently up- date the current receive descriptor with the frame sta- tus (message byte count, vlan info, frame tag, error flags, etc.) and will set the enp bit to 1. the am79c976 controller will then advance the internal ring pointer to make the next receive descriptor the new current re- ceive descriptor. when the am79c976 controller has receive data in the fifo ready to write to system memory, either at the be- ginning of a new frame or in the middle of a frame that does not fit in the previous buffer, and it does not own the current receive descriptor, it will immediately poll it. if the own bit is still zero, polling of this descriptor will continue at a rate determined by the contents of the chpollint register (csr49). polling will occur imme- diately if the rdmd bit is set. if the driver does not provide the am79c976 controller with a descriptor in a timely fashion, the receive fifo will eventually overflow. subsequent frames will be dis- carded and the rcvmisspkts mib counter will be incre- mented. normal receive operation will resume when a descriptor is provided to the am79c976 controller and sufficient data has been dma ? ed from the am79c976 controller ? s receive fifo into the system memory. when the receive fifo is empty and the am79c976 device does not own two descriptors (current and next), the receive descriptor ring is polled at an interval by the contents of the txpollint register (csr47). when the am79c976 device owns two descriptors, the receive descriptor ring is not polled at all. setting lappen (cmd2, bit 2 or csr3, bit 5) to a 1 modifies the way the controller processes receive de- scriptors. the am79c976 controller will use the stp information to determine where it should begin writing a receive packet ? s data. note that while in this mode, the am79c976 controller can write intermediate packet data to buffers whose descriptors do not contain stp bits set to 1. following the write to the last descriptor used by a packet, the am79c976 controller will scan through the next descriptor entries to locate the next stp bit that is set to a 1. the am79c976 controller will begin writing the next packet ? s data to the buffer pointed to by that descriptor. note that because several descriptors may be allo- cated by the host for each packet and not all messages may need all of the descriptors that are allocated be- tween descriptors containing stp = 1, then some de- scriptors/buffers may be skipped in the ring. while performing the search for the next stp bit that is set to 1, the am79c976 controller will advance through the receive descriptor ring regardless of the state of own- ership bits. if any of the entries that are examined dur- ing this search indicate am79c976 controller ownership of the descriptor but also indicate stp = 0, then the am79c976 controller will reset the own bit to 0 in these entries. if a scanned entry indicates host ownership with stp = 0, then the am79c976 controller will not alter the entry, but will advance to the next entry. when the stp bit is found to be true, but the descriptor that contains this setting is not owned by the am79c976 controller, then the am79c976 controller 66 am79c976 8/01/00 preliminary will stop advancing through the ring entries and begin periodic polling of this entry. when the stp bit is found to be true, and the descriptor that contains this setting is owned by the am79c976 controller, then the am79c976 controller will stop advancing through the ring entries, store the descriptor information that it has just read, and wait for the next receive to arrive. this behavior allows the host software to pre-assign buffer space in such a manner that the header portion of a receive packet will always be written to a particular memory area, and the data portion of a receive packet will always be written to a separate memory area. the interrupt is generated when the header bytes have been written to the header memory area. software interrupt timer the am79c976 controller is equipped with a software programmable free-running interrupt timer. the timer is constantly running and will generate an interrupt stint (csr 7, bit 11) when stinite (csr 7, bit 10) is set to 1. after generating the interrupt, the software timer will load the value stored in stval and restart. the timer value stval (bcr31, bits 15-0) is interpreted as an unsigned number with a resolution of 10.24s. for in- stance, a value of 98 (62h) corresponds to 1.0 ms. the default value of stval is ffffh which corresponds to 0.671 seconds. a write to stval restarts the timer with the new contents of stval. media access control the media access control (mac) engine incorporates the essential protocol requirements for operation of an ethernet/ieee 802.3-compliant node and provides the interface between the fifo subsystem and the mii. this section describes operation of the mac engine when operating in half-duplex mode. the operation of the device in full-duplex mode is described in the sec- tion titled full-duplex operation . the mac engine is fully compliant to section 4 of ieee std 802.3, 1998 edition. the mac engine provides programmable enhanced features designed to minimize host supervision, bus utilization, and pre- or post-message processing. these features include the ability to disable retries after a collision, dynamic fcs generation on a frame-by- frame basis, automatic pad field insertion and deletion to enforce minimum frame size attributes, automatic re- transmission without reloading the fifo, and auto- matic deletion of collision fragments. the mac also provides a mechanism for automatically inserting, de- leting, and modifying ieee 802.3ac vlan tags. the two primary attributes of the mac engine are: ? framing (frame boundary delimitation, frame synchronization) ? addressing (source and destination address handling) ? error detection (physical medium transmission errors) media access management ? medium allocation (collision avoidance, except in full-duplex operation) ? contention resolution (collision handling, except in full-duplex operation) ! ( # *%(' the mac engine provides minimum frame size en- forcement for transmit and receive frames. when apad_xmt (csr4, bit 11) is set to 1, transmit mes- sages will be padded with sufficient bytes (containing 00h) to ensure that the receiving station will observe an information field (destination address, source address, length/type, data, and fcs) of 64 bytes. when astrp_rcv (csr4, bit 10) is set to 1, the receiver will automatically strip pad bytes from the received mes- sage by observing the value in the length field and by stripping excess bytes if this value is below the mini- mum data size (46 bytes). both features can be inde- pendently over-ridden to allow illegally short (less than 64 bytes of frame data) messages to be transmitted and/or received. the use of this feature reduces bus utilization because the pad bytes are not transferred into or out of main memory. the mac engine will autonomously handle the con- struction of the transmit frame. once the transmit fifo has been filled to the predetermined threshold (set by xmtsp in csr80) and access to the channel is cur- rently permitted, the mac engine will commence the 7-byte preamble sequence (10101010b, where first bit transmitted is a 1). the mac engine will subsequently append the start frame delimiter (sfd) byte (10101011b) followed by the serialized data from the transmit fifo. once the data has been transmitted, the mac engine will append the fcs (most significant bit first) which was computed on the entire data portion of the frame. the data portion of the frame consists of destination address, source address, length/type, and frame data. the user is responsible for the correct or- dering and content in each of these fields in the frame. the mac does not use the content in the length/type field unless apad_xmt (csr4, bit 11) is set and the data portion of the frame is shorter than 60 bytes. 8/01/00 am79c976 67 preliminary the receiver section of the mac engine will detect the incoming preamble sequence when the rx_dv signal is activated by the external phy. the mac will discard the preamble and begin searching for the sfd except in the case of 100base-t4, for which there is no pre- amble. in that case, the sfd will be the first two nibbles received. once the sfd is detected, all subsequent nibbles are treated as part of the frame. the mac en- gine will inspect the length field to ensure minimum frame size, strip unnecessary pad characters (if auto- matic pad stripping is enabled), and pass the remaining bytes through the receive fifo to the host. if pad strip- ping is performed, the mac engine will also strip the re- ceived fcs bytes, although normal fcs computation and checking will occur. note that apart from pad strip- ping, the frame will be passed unmodified to the host. if the length field has a value of 46 or greater, all frame bytes including fcs will be passed unmodified to the receive buffer, regardless of the actual frame length. if the frame terminates or suffers a collision before 64 bytes of information (after sfd) have been received, the mac engine will automatically delete the frame from the receive fifo, without host intervention. the am79c976 controller has the ability to accept runt packets for diagnostic purposes and proprietary net- works. * . the first 6 bytes of information after sfd will be inter- preted as the destination address field. the mac en- gine provides facilities for physical (unicast), logical (multicast), and broadcast address reception. ! the mac engine provides several facilities which count and recover from errors on the medium. in addition, it protects the network from gross errors due to inability of the host to keep pace with the mac engine activity. on completion of transmission, the mac engine up- dates various counters that are described in the statis- tics counters section. the host cpu can read these counters at any time for network management pur- poses. the mac engine also attempts to prevent the creation of any network error due to the inability of the host to service the mac engine. during transmission, if the host fails to keep the transmit fifo filled sufficiently, causing an underflow, the mac engine will guarantee the message is sent with an invalid fcs, which will cause the receiver to reject the message. the mac engine can be programmed to try to transmit the same frame again after a fifo underflow or exces- sive collision error. the status of each receive message is available in the appropriate receive message descriptor (rmd). all received frames are passed to the host regardless of any error. during the reception, the fcs is generated on every nibble (including the dribbling bits) coming from the mii, although the internally saved fcs value is only up- dated on each byte boundary. the mac engine will ig- nore an extra nibble at the end of a message, which corresponds to dribbling bits on the network medium. a framing or alignment error is reported to the user if an fcs error is detected and there is an extra nibble in the message. if there is an extra nibble but no fcs error, no framing error is reported. # (( # ! the basic requirement for all stations on the network is to provide fairness of channel allocation. the ieee 802.3/ethernet protocols define a media access mech- anism which permits all stations to access the channel with equality. any node can attempt to contend for the channel by waiting for a predetermined time (inter packet gap) after the last activity, before transmitting on the media. the channel is a multidrop communica- tions media (with various topological configurations permitted), which allows a single station to transmit and all other stations to receive. if two nodes simulta- neously contend for the channel, their signals will inter- act causing loss of data, defined as a collision. it is the responsibility of the mac to attempt to avoid and to re- cover from collisions. " ## the ieee/ansi 802.3 standard (iso/iec 8802-3 1990) requires that the csma/cd mac monitor the medium for traffic by watching for carrier activity. when carrier is detected, the media is considered busy, and the mac should defer to the existing message. the iso 8802-3 (ieee/ansi 802.3) standard allows an optional two-part deferral after a receive message. see ansi/ieee std 802.3-1993 edition, 4.2.3.2.1: note: it is possible for the pls carrier sense indication to fail to be asserted during a collision on the media. if the deference process simply times the inter-frame gap based on this indication, it is possible for a short in- terframe gap to be generated, leading to a potential re- ception failure of a subsequent frame. to enhance system robustness, the following optional measures, as specified in 4.2.8, are recommended when inter- frame-spacingpart1 is other than 0: 1. upon completing a transmission, start timing the in- terrupted gap, as soon as transmitting and carrier sense are both false. 2. when timing an inter-frame gap following reception, reset the inter-frame gap timing if carrier sense be- comes true during the first 2/3 of the inter-frame gap timing interval. during the final 1/3 of the interval, 68 am79c976 8/01/00 preliminary the timer shall not be reset to ensure fair access to the medium. an initial period shorter than 2/3 of the interval is permissible including 0. the mac engine implements the optional receive two part deferral algorithm, with an interframespacing- part1 (ifs1) time of 60 bit times and an inter- framespacingpart 2 time of 36 bit times. the am79c976 controller will perform the two-part de- ferral algorithm as specified in clause 4.2.8 of ieee std 802.3 (process deference). the inter packet gap (ipg) timer will start timing the 96-bit interframespac- ing after the receive carrier is deasserted. during the first part deferral (interframespacingpart1 - ifs1), the am79c976 controller will defer any pending transmit frame and respond to the receive message. if carrier sense or collision is detected during the first part of the gap, the ipg counter will be cleared to 0 contin- uously until carrier sense and collision are both deas- serted, at which point the ipg counter will resume the 96-bit time count once again. once the ipg counter reaches the ifs1 count (60-bit times), the am79c976 controller will not defer to a receive frame if a transmit frame is pending. instead, when the ipg count reaches 96-bit times, the transmitter will start transmitting, which will cause a collision. the am79c976 controller will complete the preamble (64-bit) and jam (32-bit) se- quence before ceasing transmission and invoking the random backoff algorithm. the am79c976 controller allows the user to program both the ipg and the first part deferral (interframe- spacingpart1 - ifs1) through csr125. the user can change the ipg value from its default of 96-bit times to compensate for delays through the external phy de- vice. changing ifs1 will alter the period for which the am79c976 mac engine will defer to incoming receive frames. caution: care must be exercised when altering these parameters . undesirable network activity could result! this transmit two-part deferral algorithm is imple- mented as an option which can be disabled using the dxmt2pd bit in csr3. when dxmt2pd is set to 1, the ifs1 register is ignored, and the value 0 is used for the inter framespacingpart1 parameter. however, the ipg value is still valid. when the am79c976 device operates in full-duplex mode, the ipg timer starts counting when tx_en is de-asserted. crs is ignored in full-duplex mode. $# % # ! &$%!' during the time period immediately after a transmission has been completed, an external transceiver operating in the 10 mb/s half-duplex mode should generate an sqe test signal on the col pin within 0.6 s to 1.6 ss after the transmission ceases. therefore, when the am79c976 controller is operating in half-duplex mode, the ipg counter ignores the col signal during the first 40-bit times of the inter-packet gap. this 40-bit times is the time period in which the sqe test message is ex- pected. the sqe test was originally designed to check the in- tegrity of the collision detection mechanism indepen- dently of the transmit and receive capabilities of the physical layer. however, mii-based phy devices de- tect collisions by sensing receptions that occur during transmissions, a process that does not require a sepa- rate level-sensing collision detection mechanism. colli- sion detection is therefore dependent on the health of the receive channel. since the link monitor function checks the health of the receive channel, the sqe test is not very useful for mii-based devices. therefore, the am79c976 device does not report or count sqe test failures. (## )# collision detection is performed and reported to the mac engine via the col input pin. since the col sig- nal is not required to be synchronized with tx_clk, the col signal must be asserted for at least three tx_clk cycles in order to be detected reliably. if a collision is detected before the complete preamble/ sfd sequence has been transmitted, the mac engine will complete the preamble/sfd before appending the jam sequence. if a collision is detected after the pream- ble/sfd has been completed, but prior to 512 bits being transmitted, the mac engine will abort the trans- mission and append the jam sequence immediately. the jam sequence is a 32-bit all zeros pattern. the mac engine will attempt to transmit a frame a total of 16 times (initial attempt plus 15 retries) due to nor- mal collisions (those within the slot time). detection of collision will cause the transmission to be rescheduled to a time determined by the random backoff algorithm. if a single retry was required, the xmtonecollision counter will be incremented. if more than one retry was required, the xmtmultiplecollision counter will be incre- mented. if all 16 attempts experienced collisions, the xmtexcessivecollision counter will be incremented. after an excessive collision error, if rex_rtry (cmd3, bit 18) is cleared to 0, the transmit message will be flushed from the fifo. if the rex_rtry bit is set to 1, the transmitter will not flush the transmit mes- sage from the fifo. instead, it will clear the back-off logic and will restart the transmission process, treating the data in the fifo as a new frame. if retries have been disabled by setting the drty bit in csr15, the mac engine will abandon transmission of the frame on detection of the first collision. in this case, xmtexcessivecollision counter will be incremented, and the transmit message will be flushed from the fifo. 8/01/00 am79c976 69 preliminary if a collision is detected after 512-bit times have been transmitted, the collision is termed a late collision. the mac engine will abort the transmission, append the jam sequence, and increment the xmtlatecollision counter. if rtry_lcol (cmd3, bit 16) is set to 1, the retry logic treats late collisions just like normal colli- sions. however, if the rtry_lcol bit is cleared to 0, no retry attempt will be scheduled on detection of a late collision. in this case, the transmit message will be flushed from the fifo. the iso 8802-3 (ieee/ansi 802.3) standard requires use of a ? truncated binary exponential backoff ? algo- rithm, which provides a controlled pseudo random mechanism to enforce the collision backoff interval, be- fore retransmission is attempted. see ansi/ieee std 802.3-1990 edition, 4.2.3.2.5: ?at the end of enforcing a collision (jamming), the csma/cd sublayer delays before attempting to re- transmit the frame. the delay is an integer multiple of slot time. the number of slot times to delay be- fore the nth retransmission attempt is chosen as a uniformly distributed random integer r in the range: 0 r < 2 k where k = min (n,10). ? the am79c976 controller provides an alternative algo- rithm, which suspends the counting of the slot time/ipg during the time that receive carrier sense is detected. this aids in networks where large numbers of nodes are present, and numerous nodes can be in collision. it effectively accelerates the increase in the backoff time in busy networks and allows nodes not involved in the collision to access the channel, while the colliding nodes await a reduction in channel activity. once chan- nel activity is reduced, the nodes resolving the collision time-out their slot time counters as normal. this modified backoff algorithm is enabled when emba (csr3, bit 3) is set to 1. transmit operation the transmit operation and features of the am79c976 controller are controlled by programmable options. the am79c976 controller provides a large transmit fifo to provide frame buffering for increased system latency, automatic retransmission with no fifo reload, and au- tomatic transmit padding. ! ( 0 !! automatic transmit features such as retry on collision, fcs generation/transmission, and pad field insertion can all be programmed to provide flexibility in the (re-) transmission of messages. disable retry on collision (drty) is controlled by the drty bit of the mode register (csr15) in the initializa- tion block. automatic pad field insertion is controlled by the apad_xmt bit in csr4. the disable fcs generation/transmission feature can be programmed as a static feature or dynamically on a frame-by-frame basis. rex_rtry (cmd3, bit 18) and rex_uflo (cmd3, bit 17) can be programmed to cause the transmitter to automatically restart the transmission process instead of discarding a frame that experiences an excessive collisions or underflow error. in this case the retrans- mission will not begin until the entire frame has been loaded into the transmit fifo. the rtry_lcol bit (cmd3, bit 16) can be programmed either to drop a frame after a late collision or to treat late collisions just like normal collisions. transmit fifo watermark (xmtfw) in csr80 sets the point at which the controller requests more data from the transmit buffers for the fifo. a minimum of xmtfw empty spaces must be available in the trans- mit fifo before the controller will request the system bus in order to transfer transmit frame data into the transmit fifo. transmit start point (xmtsp) in csr80 sets the point when the transmitter actually attempts to transmit a frame onto the media. a minimum of xmtsp bytes must be written to the transmit fifo for the current frame before transmission of the current frame will be- gin. (when automatically padded packets are being sent, it is conceivable that the xmtsp is not reached when all of the data has been transferred to the fifo. in this case, the transmission will begin when all of the frame data has been placed into the transmit fifo.) the default value of xmtsp is 01b, meaning there has to be 64 bytes in the transmit fifo to start a transmis- sion. in order to ensure that collisions occurring within 512- bit times from the start of transmission (including pre- amble) will be automatically retried with no host inter- vention, the transmit fifo ensures that data contained within the fifo will not be overwritten until at least 64 bytes (512 bits) of preamble plus address, length, and data fields have been transmitted onto the network without encountering a collision. if the rex_rtry bit or the rex_uflo bit is set, the transmit data will not be overwritten until the frame has been either transmit- ted or discarded. ! (09 transmit frames can be automatically padded to extend them to 64 data bytes (excluding preamble). this al- lows the minimum frame size of 64 bytes (512 bits) for ieee 802.3/ethernet to be guaranteed with no software intervention from the host/controlling process. setting the apad_xmt bit in csr4 enables the automatic padding feature. the pad is placed between the llc 70 am79c976 8/01/00 preliminary data field and fcs field in the ieee 802.3 frame. fcs is always added if the frame is padded, regardless of the state of dxmtfcs (csr15, bit 3) or add_fcs (tmd1, bit 29). the transmit frame will be padded by bytes with the value of 00h. the default value of apad_xmt is 0 after h_reset, which will disable au- tomatic pad generation. if automatic pad generation is disabled, the software is responsible for insuring that the minimum frame size requirement is met. the hardware can reliably transmit frames ranging in size from 16 to 65536 octets. it is the responsibility of upper layer software to cor- rectly define the actual length/type field contained in the message to correspond to the total number of llc data bytes encapsulated in the frame (length/type field as defined in the ieee 802.3 standard). the length value contained in the message is not used by the am79c976 controller to compute the actual number of pad bytes to be inserted. the am79c976 controller will append pad bytes dependent on the actual number of bits transmitted onto the network. once the last data byte of the frame has completed, prior to appending the fcs, the am79c976 controller will check to ensure that 544 bits have been transmitted. if not, pad bytes are added to extend the frame size to this value, and the fcs is then added. see figure 3030. . 4 114 - :%%% 14 ;*! the 544 bit count is derived from the following: minimum frame size (excluding preamble/sfd, including fcs) 64 bytes 512 bits preamble/sfd size 8 bytes 64 bits fcs size 4 bytes 32 bits at the point that fcs is to be appended, the transmitted frame should contain: preamble/sfd + (min frame size - fcs) 64 + (512-32) = 544 bits a minimum length transmit frame from the am79c976 controller, therefore, will be 576 bits, after the fcs is appended. ! 9 automatic generation and transmission of fcs for a transmit frame depends on the value of dxmtfcs (csr15, bit 3). if dxmtfcs is cleared to 0, the trans- mitter will generate and append the fcs to the trans- mitted frame. if the transmitter modifies the frame data because of automatic padding or vlan tag manipula- tion, the fcs will be appended by the am79c976 con- troller regardless of the state of dxmtfcs or add_fcs (tmd1, bit 29). note that the calculated fcs is transmitted most significant bit first. the default value of dxmtfcs is 0 after h_reset. when dxmtfcs is set to 1, the add_fcs (tmd1, bit 29) allows the automatic generation and transmission of fcs on a frame-by-frame basis. when dxmtfcs is set to 1, a valid fcs field is appended only to those frames whose tx descriptors have their add_fcs bits set to 1. if a frame is split into more than one buffer, the add_fcs bit is ignored in all descriptors except for the first. ! % the am79c976 transmitter detects the following error conditions and increments the appropriate error counters when they occur: late collision errors can only occur when the device is operating in half-duplex mode. loss of carrier and transmit fifo underflow errors are possible when the device is operating in half- or full-duplex mode. when an error occurs in the middle of a multi-buffer frame transmission, the appropriate error counter will be incremented, and the transmission will be aborted with an inverted fcs field appended to the frame. the own bit(s) in the current and subsequent descriptor(s) will be cleared until the stp (the next frame) is found. preamble 1010....1010 sfd 10101011 destination address source address length/ type llc data pad fcs 4 bytes 46 ? 1500 bytes 2 bytes 6 bytes 6 bytes 8 bits 56 bits 8/01/00 am79c976 71 preliminary if rex_uflo (cmd3, bit 7) is set, the transmitter will not flush the frame data from the transmit fifo after a transmit fifo underflow error occurs. instead, it will wait until the entire frame has been copied into the transmit fifo, and then it will restart the transmission process. ( the xmtlosscarrier counter is incremented if transmit is attempted when the link_stat bit in the stat0 reg- ister is 0. (## a late collision will be detected when the device is op- erating in half-duplex mode and a collision condition occurs after one slot time (512 bit times) after the trans- mit process was initiated (first bit of preamble com- menced). when it detects a late collision, the am79c976 controller will increment the xmtlatecolli- sion counter. if rtry_lcol (cmd3, bit 16) is cleared to 0, the controller will abandon the transmit process for that frame, and process the next transmit frame in the ring. if the rtry_lcol bit is set to 1, transmission at- tempts that incur late collisions will be retried up to a maximum of 16 attempts. * +#, an underflow error occurs when the transmitter runs out of data from the transmit fifo in the middle of a transmission. when this happens, an inverted fcs is appended to the frame so that the intended receiver will ignore the frame, and the xmtunderrunpkts counter is incremented. if rex_uflo (cmd3, bit 17) is set to 1, the transmitter will then wait until the entire frame has been loaded into the transmit fifo, and then it will re- start the transmission of the same frame. if the rex_uflo is cleared to 0, the transmitter will not at- tempt to retransmit the aborted frame. receive operation the receive operation and features of the am79c976 controller are controlled by programmable options. the am79c976 controller uses a large receive fifo to pro- vide frame buffering for increased system latency, au- tomatic flushing of collision fragments (runt packets), automatic receive pad stripping, and a variety of ad- dress match options. ( ( 0 !! automatic pad field stripping is enabled by setting the astrp_rcv bit in csr4. this can provide flexibility in the reception of messages using the ieee 802.3 frame format. the device can be programmed to accept all receive frames regardless of destination address by setting the prom bit in csr15. acceptance of unicast and broad- cast frames can be individually turned off by setting the drcvpa or drcvbc bits in csr15. the physical ad- dress register (csr12 to csr14) stores the address that the am79c976 controller compares to the destina- tion address of the incoming frame for a unicast ad- dress match. the logical address filter register (csr8 to csr11) serves as a hash filter for multicast address match. the point at which the controller will start to transfer data from the receive fifo to buffer memory is con- trolled by the rcvfw bits in csr80. the default es- tablished during h_reset is 01b, which sets the watermark flag at 64 bytes filled. for test purposes, the am79c976 controller can be programmed to accept runt packets of 12 bytes or larger by setting rpa in csr124. #(+ the am79c976 controller supports three types of ad- dress matching: unicast, multicast, and broadcast. the normal address matching procedure can be modified by programming three bits in csr15, the mode register (prom, drcvpa, and drcvbc). if the first bit received after the sfd (the least signifi- cant bit of the first byte of the destination address field) is 0, the frame is unicast, which indicates that the frame is meant to be received by a single node. if the first bit received is 1, the frame is multicast, which indicates that the frame is meant to be received by a group of nodes. if the destination address field contains all 1s, the frame is broadcast, which is a special type of multi- cast. frames with the broadcast address in the destina- tion address field are meant to be received by all nodes on the local area network. when a unicast frame arrives at the am79c976 con- troller, the controller will accept the frame if the destina- tion address field of the incoming frame exactly matches the 6-byte station address stored in the phys- ical address registers (padr, csr12 to csr14). the byte ordering is such that the first byte received from the network (after the sfd) must match the least signif- icant byte of csr12 (padr[7:0]), and the sixth byte re- ceived must match the most significant byte of csr14 (padr[47:40]). when drcvpa (csr15, bit 13) is set to 1, the am79c976 controller will not accept unicast frames. if the incoming frame is multicast, the am79c976 con- troller performs a calculation on the contents of the destination address field to determine whether or not to accept the frame. this calculation is explained in the section that describes the logical address filter (ladrf). when all bits of the ladrf registers are 0, no multicast frames are accepted, except for broadcast frames. 72 am79c976 8/01/00 preliminary although broadcast frames are classified as special multicast frames, they are treated differently by the am79c976 controller hardware. broadcast frames are always accepted, except when drcvbc (csr15, bit 14) is set. drcvbc overrides a logical address match. if drcvbc is set to 1, broadcast frames are not ac- cepted even if the logical address filter is pro- grammed in such a way that a broadcast frame would pass the hash filter. none of the address filtering described above applies when the am79c976 controller is operating in the pro- miscuous mode. in the promiscuous mode, all properly formed packets are received, regardless of the con- tents of their destination address fields. the promiscu- ous mode overrides the disable receive broadcast bit (drcvbc bit am79c976 in the mode register) and the disable receive physical address bit (drcvpa, csr15, bit 13). the am79c976 controller operates in promiscuous mode when prom (csr15, bit 15) is set. in addition, the am79c976 controller provides the ex- ternal address detection interface (eadi) to allow ex- ternal address filtering. see the external address detection interface section for further details. the receive descriptor entry rmd1 contains three bits that indicate which method of address matching caused the am79c976 controller to accept the frame. note that these indicator bits are not available when the am79c976 controller is programmed to use 16-bit structures for the descriptor entries (bcr20, bit 7-0, swstyle is set to 0). pam (rmd1, bit 22) is set by the am79c976 controller when it accepts the received frame due to a match of the frame ? s destination address with the content of the physical address register. lafm (rmd1, bit 21) is set by the am79c976 control- ler when it accepts the received frame based on the value in the logical address filter register. bam (rmd1, bit 20) is set by the am79c976 controller when it accepts the received frame because the frame ? s destination address is of the type ? broadcast ? . only bam, but not lafm, will be set when a broadcast frame is received, even if the logical address filter is programmed in such a way that a broadcast frame would pass the hash filter. when the am79c976 controller operates in promiscu- ous mode and none of the three match bits is set, it is an indication that the am79c976 controller only ac- cepted the frame because it was in promiscuous mode. when the am79c976 controller is not programmed to be in promiscuous mode, but the eadi interface is used and when none of the three match bits is set, it is an in- dication that the am79c976 controller only accepted the frame because it was not rejected by driving the ear pin low during the receive protect time. the length of receive protect period can be programmed in the receive protect register. see table 6 for receive address matches. table 6. receive address match ! (0 '' during reception of an ieee 802.3 frame, the pad field can be stripped automatically. setting astrp_rcv (csr4, bit 0) to 1 enables the automatic pad stripping feature. the pad field will be stripped before the frame is passed to the fifo, thus preserving fifo space for additional frames. the fcs field will also be stripped, since it is computed at the transmitting station based on the data and pad field characters, and will be invalid for a receive frame that has had the pad characters stripped. the number of bytes to be stripped is calculated from the embedded length field (as defined in the iso 8802- 3 (ieee/ansi 802.3) definition) contained in the frame. the length indicates the actual number of llc data bytes contained in the message. any received frame which contains a length field less than 46 bytes will have the pad field stripped (if astrp_rcv is set). receive frames which have a length field of 46 bytes or greater will be passed to the host unmodified. figure 31 shows the byte/bit ordering of the received length field for an ieee 802.3-compatible frame format. pam lafm bam comment 000 frame accepted due to prom = 1 or no eadi reject 1 0 0 physical address match 010 logical address filter match; frame is not of type broadcast 0 0 1 broadcast frame 8/01/00 am79c976 73 preliminary %%%14 !< + ! since any valid ethernet type field value will always be greater than a normal ieee 802.3 length field ( ? 46), the am79c976 controller will not attempt to strip valid ethernet frames. note that for some network protocols, the value passed in the ethernet type and/or ieee 802.3 length field is not compliant with either standard and may cause problems if pad stripping is enabled . ( +(7 reception and checking of the received fcs is per- formed automatically by the am79c976 controller. note that if the automatic pad stripping feature is en- abled, the fcs for padded frames will be verified against the value computed for the incoming bit stream including pad characters, but the fcs value for a pad- ded frame will not be passed to the host. if an fcs error is detected in any frame, the error will be reported in the crc bit in the receive descriptor. ( %&(' exception conditions for frame reception fall into two categories, i.e., those conditions which are the result of normal network operation, and those which occur due to abnormal network and/or host related events. normal exception events are caused by collisions, which can distort and truncate received frames. frames shorter than 64 bytes will, by default, be dis- carded. these fragments will be discarded regardless of whether the receive frame was the first (or only) frame in the fifo or if the receive frame was queued behind a previously received message. there are two control bits that can be used to cause the mac to override normal behavior and accept all frames that pass address match, regardless of the frame length. setting the runt packet accept (rpa) bit (cmd2, bit 19) causes the mac to accept runt packets when the device is operating in either half- or full-du- plex mode. setting full-duplex runt packet accept (fdrpa, cmd2, bit 20) causes the mac to accept runt packets when the device is operating in full-duplex mode. (when the value of rpa is 1, runt packets are accepted regardless of the duplex mode or the value of fdrpa.) in either case, there is a minimum frame size of 16 bytes. frames shorter than this may not be ac- cepted, regardless of the value of rpa or fdrpa. abnormal network conditions include: these error conditions are reported in the correspond- ing receive descriptors. the rcvfcserrors, rcvalign- menterrors, or rcvmisspkts counter is also incremented when one of these events occurs. statistics counters in order to provide network management information with minimum host cpu overhead, the am79c976 de- vice automatically maintains a set of 32-bit controller statistics counters. these counters are mapped di- preamble 1010....1010 sfd 10101011 destination address source address length llc data pad fcs 4 bytes 46 ? 1500 bytes 2 bytes 6 bytes 6 bytes 8 bits 56 bits start of frame at time = 0 increasing time bit 0 bit 7 bit 0 bit 7 most significant byte least significant byte 1 ? 1500 bytes 45 ? 0 bytes 74 am79c976 8/01/00 preliminary rectly into pci memory space and can not be accessed indirectly through the rap and rdp registers. to simplify the use of software debuggers, the counter logic is designed so that the statistics counters can be accessed one, two, or four bytes at a time. when a por- tion of a statistics counter is read, the entire 32 bits of the counter is loaded into an internal holding register in a single atomic operation. when the cpu reads one or more bytes from the same counter, the data are read from the holding register rather than from the counter. the holding register is updated when either a read ac- cess is made to a different counter or a byte of the same counter is read for a second time. write access to statistics counters is provided for de- bugging purposes only. no holding register is used for write accesses. writing one or two bytes at a time to a statistics counter while the network is active can cause unpredictable results. the contents of the entire set of statistics counters can be cleared to zero by setting the init_mib bit (cmd3, bit 25). the counters will be cleared within approxi- mately 55 erclk cycles after the init_mib bit is set. ( ( the receive statistics counters are defined and the management information base (mib) objects that they support are listed in table 7. for these counters, the definition of a valid frame de- pends on the state of the jumbo and vsize bits (cmd3, bits 21 and 20) as follows: if jumbo = 1, valid frames are frames that are be- tween 64 and 65536 bytes in length and have a correct fcs value. frames longer than 65536 bytes may not be handled properly. if jumbo = 0 and vsize = 0, valid frames are frames that are between 64 and 1518 bytes in length and have a correct fcs value. if jumbo = 0 and vsize = 1, valid frames are frames that are between 64 and 1522 bytes in length and have a correct fcs value. in table 7, the offset column gives the offset with re- spect to the value stored in the read-only mib offset register, which is located at offset 28h in the memory address space allocated to the am79c976 device. the actual address of a particular counter is the sum of the following quantities: ! " #"$ % & "% ' table 7. receive statistics counters offset (hex) receive counter name mib object supported description of counter/comments 00 rcvmisspkts rmon etherstatsdropevents rmon etherhistorydropevents mib-ii ifindiscards e-like dot3statsinternalmacreceiveerrors the number of times a receive packet was dropped due to lack of resources. this is the number of times a packet was dropped due to receive fifo overflow. this count does not include undersize, oversize, misaligned or bad fcs packets. 04 rcvoctets rmon etherstatsoctets rmon etherhistoryoctets mib-ii ifinoctets the total number of octets of data received including octets from invalid frames. this does not include the preamble but does include the fcs bits. the rcvoctets counter is incremented whenever the receiver receives an octet. 08 rcvbroadcastpkts rmon etherstatsbroadcastpkts rmon etherhistorybroadcastpkts ext-mib-ii ifinbroadcastpkts the total number of valid frames received that are addressed to a broadcast address. this counter does not include errored broadcast packets or valid multicast packets. 0c rcvmulticastpkts rmon etherstatsmulticastpkts rmon etherhistorymulticastpkts ext-mib-ii ifinmulticastpkts the total number of valid frames received that are addressed to a multicast address. this counter does not include errored multicast packets or valid broadcast packets. 8/01/00 am79c976 75 preliminary 10 rcvundersizepkts rmon etherstatsundersizepkts rmon etherhistoryundersizepkts the total number of valid frames received that are less than 64 bytes long (including the fcs) and do not have any error. sfd must be received so that the fcs can be calculated. 14 rcvoversizepkts rmon etherstatsoversizepkts rmon etherhistoryoversizepkts e-like mib dot3statsframetoolongs the total number of packets received that are greater than 1518 (1522 when vlan set) bytes long (including the fcs) and do not have any error. sfd must be received so that the fcs can be calculated. 18 rcvfragments rmon etherstatsfragments rmon etherhistoryfragments the number of packets received that are less than 64 bytes (not including the preamble or sfd) and have either an fcs error or an alignment error. 1c rcvjabbers rmon etherstatsjabbers rmon etherhistoryjabbers the number of packets received that are greater than 1518 (1522 when vlan set) bytes long and have either an fcs error or an alignment error. 20 rcvunicastpkts mib-ii ifinucastpkts the number of valid frames received that are not addressed to a multicast address or a broadcast address. this counter does not include errored unicast packets. 24 rcvalignmenterrors e-like mib dot3statsalignmenterrors the number of packets received that are between 64 and 1518 (1522 when vlan set) bytes (excluding preamble/sfd but including fcs), inclusive, and have a bad fcs with non-integral number of bytes. 28 rcvfcserrors e-like mib dot3statsfcserrors the total number of packets received that are between 64 and 1518 (1522 when vlan set) bytes (excluding preamble/sfd but including fcs), inclusive, and have a bad fcs with an integral number of bytes. this counter will also count packets with a correct fcs if rx_er occurs when valid carrier rx_dv is present. 2c rcvgoodoctets rmon hostinoctets rmon hosttimeinoctets the total number of bytes received by a port. bytes are 8-bit quantities received after the sfd. this does not include preamble or bytes from erroneous packets, but does include the fcs. 30 rcvmacctrl 802.3x amaccontrolframesreceived the total number of valid frames received with a lengthortype field value equal to 8808h. 34 rcvflowctrl 802.3x apausemacctrlframesreceived the total number of valid frames received with (1) a lengthortype field value equal to 8808h and (2) an opcode equal to 1. 40 rcvpkts64octets rmon etherstatspkts64octets the total number of packets (including error packets) that are 64 bytes long. 44 rcvpkts65to127octets rmon etherstatspkts65to127octets the total number of packets (including error packets) that are 65 bytes to 127 bytes long, inclusive. offset (hex) receive counter name mib object supported description of counter/comments 76 am79c976 8/01/00 preliminary ! ( table 8 describes the statistics counters associated with the transmitter and lists the mib objects that these counters support. in this table the offset column gives the offset with re- spect to the value stored in the read-only mib offset register, which is located at offset 28h in the memory address space allocated to the am79c976 device. the actual address of a particular counter is the sum of the following quantities: ! " #"$ % & "% ( table 8. transmit statistics counters 48 rcvpkts128to255octets rmon etherstatspkts128to255octets the total number of packets (including error packets) that are 128 bytes to 255 bytes long, inclusive. 4c rcvpkts256to511octets rmon etherstatspkts256to511octets the total number of packets (including error packets) that are 256 bytes to 511 bytes long, inclusive. 50 rcvpkts512to1023octets rmon etherstatspkts512to1023octets the total number of packets (including error packets) that are 512 bytes to 1023 bytes long, inclusive 54 rcvpkts1024to1518octets rmon etherstatspkts1024to1518octets the total number of packets (including error packets) that are 1024 bytes to 1518 (1522 when vlan set) bytes long, inclusive. 58 rcvunsupportedopcodes 802.3x an unsupportedopcodesreceived the total number of valid frames received with (1) a lengthortype field value equal to 8808h and (2) an opcode not equal to 1. 5c rcvsymbolerrors the number of times when valid carrier (crs) was present and there was at least one occurrence of an invalid data symbol (rx_er). this counter is incremented only once per valid carrier event (once per frame), and if a collision is present, this counter must not be incremented. offset (hex) receive counter name mib object supported description of counter/comments offset (hex) transmit counter name mib object supported description of counter/comments 60 xmtunderrunpkts rmon etherstatsdropevents rmon etherhistorydropevents mib-ii ifoutdiscards e-like dot3statsinternalmactranmsiterrors the number of times a packet was dropped due to transmit fifo underrun. 64 xmtoctets rmon etherstatsoctets rmon etherhistoryoctets rmon hostoutoctets rmon hosttimeoutoctets mib-ii ifoutoctets the total number of octets of data transmitted. this does not include the preamble but does include the fcs bits. the xmtoctets counter is incremented whenever the transmitter transmits an octet. 8/01/00 am79c976 77 preliminary 68 xmtpackets rmon etherstatspkts rmon etherhistorypkts rmon hostoutpkts rmon hosttimeoutpkts bridge-mib dot1dtpportoutframes the number of packets transmitted. this does not include packets transmitted with errors (i.e., collision fragments and partial packets due to transmit fifo under runs). 6c xmtbroadcastpkts rmon etherstatsbroadcastpkts rmon etherhistorybroadcastpkts rmon hostoutbroadcastpkts rmon hosttimeoutbroadcastpkts ext-mib-ii ifoutbroadcastpkts the number of valid frames transmitted that are addressed to a broadcast address. this counter does not include errored broadcast packets or valid multicast packets. 70 xmtmulticastpkts rmon etherstatsmulticastpkts rmon etherhistorymulticastpkts rmon hostoutmulticastpkts rmon hosttimeoutmulticastpkts ext-mib-ii ifoutmulticastpkts the number of valid frames transmitted that are addressed to a multicast address. this counter does not include errored multicast packets or valid broadcast packets. 74 xmtcollisions rmon etherstatscollisions rmon etherhistorycollisions the number of collisions that occur during transmission attempts. collisions that occur while the device is not transmitting (i.e., receive collisions) are not identifiable and therefore not counted. 78 xmtunicastpkts mib-ii ifoutucastpkts the number of valid frames transmitted that are not addressed to a multicast or a broadcast address. this counter does not include errored unicast packets. 7c xmtonecollision e-like dot3statssinglecollisionframes the number of packets successfully transmitted after experiencing one collision. 80 xmtmultiplecollision e-like dot3statsmultiplecollsionframes the number of packets successfully transmitted after experiencing more than one collision. 84 xmtdeferredtransmit e-like dot3statsdeferredtransmissions the number of packets for which the first transmission attempt on the network is delayed because the medium is busy. 88 xmtlatecollision e-like dot3statslatecollisions the number of late collisions that occur. a late collision is defined as a collision that occurs more than 512 bit times after the transmission starts. the 512- bit interval is measured from the start of preamble. 8c xmtexcessivedefer the number of excessive deferrals that occur. an excessive deferral occurs when a transmission is deferred for more than 3036 byte times in normal mode or 3044 byte times in vlan mode. 90 xmtlosscarrier the number of transmit attempts made when the link_stat bit in the stat0 register is 0. 94 xmtexcessivecollision e-like dot3statsexcessivecollisions the number of packets that are not transmitted because the packet experienced 16 unsuccessful transmission attempts (the first attempt plus 15 retries). offset (hex) transmit counter name mib object supported description of counter/comments 78 am79c976 8/01/00 preliminary vlan support virtual bridged local area network (vlan) tags are defined in ieee std 802.3ac-1998. a vlan tag is a 4-byte quantity that is inserted between the source address field and the length/type field of a basic 802.3 mac frame. the vlan tag consists of a length/type field that contains the value 8100h and a 16-bit tag control information (tci) field. the tci field is further divided into a 3-bit user priority field, a 1-bit canonical format indicator (cfi), and a 12-bit vlan identifier. a frame that has no vlan tag is said to be untagged. a frame with a vlan tag whose vlan identifier field contains the value 0 is said to be priority-tagged. a frame with a vlan tag with a non-zero vlan identifier field is said to be vlan-tagged. the format of a vlan-tagged frame is shown in figure 32. 98 xmtbackpressure the total number of back pressure collisions generated. 9c xmtflowctrl pausemacctrlframestransmitted the total number of pause packets generated and transmitted by the controller hardware. a0 xmtpkts64octets rmon etherstatspkts64octets the total number of packets (excluding error packets) that are 64 bytes long. a4 xmtpkts65to127octets rmon etherstatspkts65to127octets the total number of packets transmitted (excluding error packets) that are 65 bytes to 127 bytes long, inclusive. a8 xmtpkts128to255octets rmon etherstatspkts128to255octets the total number of packets transmitted (excluding error packets) that are 128 bytes to 255 bytes long, inclusive. ac xmtpkts256to511octets rmon etherstatspkts256to511octets the total number of packets transmitted (excluding error packets) that are 256 bytes to 511 bytes long, inclusive. b0 xmtpkts512to1023octets rmon etherstatspkts512to1023octets the total number of packets transmitted (excluding error packets) that are 512 bytes to 1023 bytes long, inclusive b4 xmtpkts1024to1518octets rmon etherstatspkts1024to1518octets the total number of packets transmitted (excluding error packets) that are 1024 bytes to 1518 (1522 when vlan set) bytes long, inclusive. b8 xmtoversizepkts the total number of packets transmitted (excluding error packets) that are longer than 1518 (1522 when vlan set) bytes. offset (hex) transmit counter name mib object supported description of counter/comments 8/01/00 am79c976 79 preliminary =< - !! the am79c976 device includes several features that can simplify the processing of ieee 802.3ac vlan- tagged frames. - $. while the maximum frame size for ieee 802.3 frames without vlan tags is 1518 bytes, the maximum frame size for vlan-tagged frames is 1522 bytes. the vlan frame size bit (vsize, cmd3, bit 20) determines the maximum frame size. when vsize is set to 1 the max- imum frame size is 1522 bytes. otherwise, the maxi- mum frame size is 1518 bytes. the maximum frame size is used for determining when to increment the xmtoversizepkts, xmtpkts1024to1518octets, xmtexcessivedefer, rcvpkts1024to1518octets, and rcvoversizepkts mib counters. # - the admit only vlan (vlonly) bit in the command1 register can be programmed to reject any frame that is not vlan-tagged. when vlonly is set, untagged or priority-tagged frames will be flushed from the receive fifo and will not be copied into system memory. only frames with a length/type field equal to 8100h and a non-zero vlan id field will be received. the vlan id field consists of bits [11:0] of the 15th and 16th bytes of the frame. - when the swstyle field in csr58 contains the value 4 or 5, vlan tag information can be passed between the host cpu and the network medium through trans- mit or receive descriptors. the transmitter can be pro- grammed to insert or delete a vlan tag or to modify the tci field of a vlan tag. this feature allows vlan software to control the vlan tag of a frame without modifying data in transmit buffers. the receiver can de- termine whether a frame is untagged, priority-tagged, or vlan-tagged, and it can copy the tci field of the vlan tag into the receive descriptor the tag control command (tcc) is a 2-bit field in the transmit descriptor that determines whether the trans- mitter will insert, delete, or modify a vlan tag or trans- mit the data from the transmit buffers unaltered. the encoding of the tcc field is shown in table 9. if the transmitter adds, deletes, or modifies a vlan tag, it will append a valid fcs field to the frame, regardless of the state of the disable transmit fcs (dxmtfcs) bit in csr15. when swstyle is 4 or 5, the receiver examines each incoming frame and writes the frame ? s vlan classifica- tion into the tag type (tt) field of the receive descrip- tor. if the frame contains a vlan tag, the receiver will copy the tci field of tag into the tci field of the receive descriptor. the encoding of the tt field is shown in table 10. preamble sfd destination address source address length/type = 8100h tag control information mac client length/type mac client data frame check sequence 7 octets 1 octet 6 octets 6 octets 2 octets 2 octets 2 octets 42-1500 octets 4 octets vlan id canonical fmt indicator user priority 0 11 13 15 80 am79c976 8/01/00 preliminary table 9. vlan tag control command table 10. vlan tag type loopback operation loopback is a mode of operation intended for system diagnostics. in this mode, the transmitter and receiver are both operating at the same time so that the control- ler receives its own transmissions. the controller pro- vides two basic types of loopback. in internal loopback mode, the transmitted data is looped back to the re- ceiver inside the controller without actually transmitting any data to the external network. the receiver will move the received data to the next receive buffer, where it can be examined by software. alternatively, in external loopback mode, data can be transmitted to and received from the external network. the external loopback through the mii requires a two- step operation. the external phy must be placed into a loop-back mode by writing to the phy access regis- ter. then the am79c976 controller must be placed into an external loopback mode by setting exloop (cmd2, bit 3). the internal loopback through the mii is controlled by inloop (cmd2, bit 4). when set to 1, this bit will cause the internal portion of the mii data port to loop- back on itself. the mii management port (mdc, mdio) is unaffected by the inloop bit. the internal mii interface is mapped in the following way: )*+,-./ 0 )*+,-./ )1 2 0 )1 2 )134 0 )1*5 )134 6 0 )13 &'7 7'8 # 0 during the internal loopback, the tx_en and txd pins will be active. internal loopback should not be used on a live network because collisions will not be handled correctly. the wire should be disconnected or the phy isolated before using internal loopback. # ( <'5(7 all transmit and receive function programming, such as automatic transmit padding and receive pad stripping, operates identically in loopback as in normal operation. runt packet accept is internally enabled regardless of the state of the rpa bit in csr124 when any loopback mode is invoked. this is for backwards compatibility with the c-lance (am79c90) software. the c-lance controller and the half-duplex members of the pcnet family of devices place certain restrictions on fcs generation and checking, and on testing multi- cast address detection. since the am79c976 controller has two fcs generators, these restrictions do not apply to the am79c976 controller. on receive, the am79c976 controller provides true fcs status. the descriptor for a frame with an fcs error will have the fcs bit (rmd1, bit 27) set to 1. the fcs generator on the transmit side can still be disabled by setting dxmt- fcs (csr15, bit 3) to 1. in internal loopback operation, the am79c976 control- ler provides a special mode to test the collision logic. when fcoll (csr15, bit 4) is set to 1, a collision is forced during every transmission attempt. this will re- sult in a retry error. full-duplex operation the am79c976 controller supports full-duplex opera- tion on both network interfaces. full-duplex operation allows simultaneous transmit and receive activity on the txd[3:0] and rxd[3:0] pins of the mii port. full-duplex operation is enabled by the fden bit located in bcr9 for all ports. full-duplex operation is also enabled through auto-negotiation when danas (bcr 32, bit 7) is not enabled on the mii port and the asel bit is set, and both the external phy and its link partner are ca- pable of auto-negotiation and full-duplex operation. when operating in full-duplex mode, the following changes to the device operation are made: the mac engine changes for full-duplex operation are as follows: * - tcc (tmd2[17:16]) action 00 transmit data in buffer unaltered 01 delete tag header 10 insert tag header containing tci field from descriptor. 11 replace tci field from buffer with tci data from descriptor. tt (rmd1[19:18]) description 00 reserved 01 frame is untagged 10 frame is priority-tagged 11 frame is vlan-tagged 8/01/00 am79c976 81 preliminary ? transmission is not deferred while receive is active. ? the ipg counter which governs transmit deferral during the ipg between back-to-back transmits is started when transmit activity for the first packet ends, instead of when transmit and car- rier activity ends. "& -*'&< 7 <%*'' the am79c976 controller provides bits in each of the led status registers (bcr4, bcr5, bcr6, bcr7) to display the full-duplex link status. if the fdlse bit (bit 8) is set, a value of 1 will be sent to the associated led- out bit when in full-duplex. media independent interface the am79c976 controller fully supports the mii according to the ieee 802.3 standard. this reconcili- ation sublayer interface allows a variety of phys (100base-tx, 100base-fx, 100base-t4, 100base-t2, 10base-t, etc.) to be attached to the am79c976 mac engine without future upgrade prob- lems. the mii interface is a 4-bit (nibble) wide data path interface that runs at 25 mhz for 100-mbps networks or 2.5 mhz for 10-mbps networks. the interface consists of two independent data paths, receive (rxd(3:0)) and transmit (txd(3:0)), control signals for each data path (rx_er, rx_dv, tx_en), network status signals (col, crs), clocks (rx_clk, tx_clk) for each data path, and a two-wire management interface (mdc and mdio). see figure 3333. the transmit and receive paths in the am79c976 con- troller's mac are independent. the tx_clk and rx_clk need not run at the same frequency. tx_clk can slow down or stop without affecting receive and vice versa. it is only necessary to respect the minimum clock high and low time specifications when switching tx_clk or rx_clk. this facilitates operation with phys that use mii signaling but do not adhere to 802.3 mii specifications. # ! ( the mii transmit clock is generated by the external phy and is sent to the am79c976 controller on the tx_clk input pin. the clock can run at 25 mhz or 2.5 mhz, depending on the speed of the network to which the external phy is attached. the data is a nibble-wide (4 bits) data path, txd(3:0), from the am79c976 con- troller to the external phy and is synchronous with the rising edge of tx_clk. the transmit process starts when the am79c976 controller asserts tx_en, which indicates to the external phy that the data on txd(3:0) is valid. ieee std 802.3 provides a mechanism for signalling unrecoverable errors through the mii to the external phy with the tx_er output pin. the external phy will respond to this error by generating a tx coding error on the current transmitted frame. the am79c976 control- ler does not use this method of signaling errors on the transmit side. instead if the am79c976 controller de- tects a transmit error, it will invert the fcs to generate an invalid fcs. since the am79c976 controller does not implement the tx_er function, the tx_er pin on the external phy device should be connected to vss. #( ( the mii receive clock is also generated by the external phy and is sent to the am79c976 controller on the rx_clk input pin. the clock will be the same fre- quency as the tx_clk but will be out of phase and can run at 25 mhz or 2.5 mhz, depending on the speed of the network to which the external phy is attached. 82 am79c976 8/01/00 preliminary # '( the receive process starts when rx_dv is asserted. rx_dv must remain asserted until the end of the re- ceive frame. if the external phy device detects errors in the currently received frame, it asserts the rx_er signal. rx_er can be used to signal special conditions out of band when rx_dv is not asserted. two defined out-of-band conditions for this are the 100base-tx signaling of bad start of frame delimiter and the 100base-t4 indication of illegal code group before the receiver has synchronized with the incoming data. the am79c976 controller will not respond to these condi- tions. all out of band conditions are currently treated as null events. certain in-band non-ieee 802.3-compli- ant flow control sequences may cause erratic behavior for the am79c976 controller. consult the switch/ bridge/router/hub manual to disable the in-band flow control sequences if they are being used. # 87 ( the mii also provides the crs (carrier sense) and col (collision sense) signals that are required for ieee 802.3 operation. carrier sense is used to detect non-idle activity on the network for the purpose of inter- frame spacing timing in half-duplex mode. collision sense is used to indicate that simultaneous transmis- sion has occurred in a half-duplex network. ## !( the mii provides a two-wire management interface so that the am79c976 controller can control external phy devices and receive status from them. the am79c976 controller offers direct hardware sup- port of the external phy device without software inter- vention. the device automatically uses the mii management interface to read auto-negotiation infor- mation from the external phy device and configures the mac accordingly. the controller also provides the host cpu indirect access to the external phy through the mii control, address, and data registers (bcr32, 33, 34). with software support the am79c976 controller can support up to 31 external phys attached to the mii management interface. two independent state machines use the mii manage- ment interface to poll external phy devices: the net- work port manager and the auto-poll state machine. the network port manager coordinates the auto-nego- tiation process, while the auto-poll state machine inter- rupts the host cpu when it detects changes in user- selected phy registers. the network port manager sends a management frame to the default phy about once every 900 ms to determine auto-negotiation results and the current link status. the network port manager uses the auto-nego- tiation results to set the mac ? s speed, duplex mode, and flow control ability. changes detected by the net- work port manager affect the operation of the mac and mib counters. for example, if link failure is detected, the transmitter will increment the xmtlosscarrier counter each time it attempts to transmit a frame. the auto-poll state machine periodically sends man- agement frames to poll the status register of the default phy device plus up to 5 user-selected phy registers and interrupts the host processor if it detects a change in any of these registers. the auto-poll state machine does not change the state of the mac engine. ## !! the format of an mii management frame is defined in clause 22 of ieee std 802.3. the start of an mii man- 4 rxd(3:0) rx_dv rx_er rx_clk 4 txd(3:0) tx_en am79c976 mii interface col crs receive signals transmit signals management port signals network status signals tx_clk mdio mdc 8/01/00 am79c976 83 preliminary agement frame is a preamble of 32 ones that guaran- tees that all of the external phys are synchronized on the same interface. (see figure 3434.) loss of syn- chronization is possible due to the hot-plugging capa- bility of the exposed mii. the preamble can be suppressed as described below if the external phy is designed to accept frames with no preamble. "!!+#(( the preamble (if present) is followed by a start field (st) and an operation field (op). the operation field (op) indicates whether the am79c976 controller is ini- tiating a read or write operation. this field is followed by the external phy address (phyad) and the register address (regad). the phy address of 1fh is re- served and should not be used. the register address field is followed by a bus turn- around field. during a read operation, the bus turn- around field is used to determine if the external phy is responding correctly to the read request or not. the am79c976 controller will tri-state the mdio for both mdc cycles. during the second cycle of a read operation, if the ex- ternal phy is synchronized to the am79c976 control- ler, the external phy will drive a 0. if the external phy does not drive a 0, the am79c976 controller will signal a mreint (csr7, bit 9) interrupt, if mreinte (csr7, bit 8) is set to a 1. this interrupt indicates that the am79c976 controller had an mii management frame read error and that the data read is not valid. during a write access the am79c976 controller drives a 1 for the first bit time of the turnaround field and a 0 for the second bit time. after the turn around field comes the data field. for a write access the am79c976 controller fills this field with data to be written to the phy device. for a read ac- cess the external phy device fills this field with data from the selected register. the last field of the mii management frame is an idle field that is necessary to give ample time for drivers to turn off before the next access. mii management frames transmitted through the mdio pin are synchronized with the rising edge of the man- agement data clock (mdc). the am79c976 controller will drive the mdc to 0 and tri-state the mdio anytime the mii management port is not active. to help to speed up the reading and writing of the mii management frames to the external phy, the mdc can be sped up to 10 mhz by setting the fmdc bits in bcr32. the ieee 802.3 specification requires use of the 2.5-mhz clock rate, but 5 mhz and 10 mhz are available for the user. the intended applications are that the 10-mhz clock rate can be used for a single ex- ternal phy on an adapter card or motherboard. the 5-mhz clock rate can be used for an exposed mii with one external phy attached. the 2.5-mhz clock rate is intended to be used when multiple external phys are connected to the mii management port or if compli- ance to the ieee 802.3u standard is required. . 0(( %&0.> the host cpu can indirectly read and write external phy registers through the phy access register or, for compatibility with other pcnet family devices, through bcr33 and bcr34. to write to a phy register the host cpu puts the regis- ter data into the phy_data field of the phy access register, specifies the address of the external phy de- vice in the phy_addr field and the phy register num- ber in the phy_reg_addr field, and sets the phy_wr_cmd bit. the am79c976 device provides two types of read ac- cess to external phy registers, blocking and non-block- ing. if a blocking read access is used, the device will generate pci disconnect/retry cycles if the host cpu attempts to read the phy access register while the mii management frame is being processed. if a non- blocking read is used, the phy access register can be read at any time, and the phy_cmd_done bit in that register indicates whether or not phy_data field con- tains valid data. preamble 1111....1111 op 10 rd 01 wr phy address register address ta z0 rd 10 wr data 2 bits 5 bits 5 bits 2 bits 32 bits st 01 2 bits 16 bits 1 bit idle z 84 am79c976 8/01/00 preliminary to generate a non-blocking read from a phy register the host cpu specifies the address of the external phy device in the phy_addr field and the phy register number in the phy_reg_addr field of the phy ac- cess register and sets the phy_nblk_rd_cmd bit. the host cpu can then poll the register until the phy_cmd_done bit is 1, or it can wait for the mii management command complete interrupt (mccint in the int0 register). when the phy_cmd_done bit is 1, the phy_data field contains the data read from the specified external phy register. if an error occurs in the read operation, the mii management read error in- terrupt (mreint) bit in the interrupt0 register is set, and if the corresponding enable bit is set (mreinte in the interrupt enable register), the host cpu is inter- rupted. to generate a blocking read, the host cpu uses the same procedure as it does for a non-blocking read, ex- cept that it sets the phy_blk_rd_cmd bit rather than the phy_nblk_rd_cmd bit, and it can poll the phy access register until the phy_cmd_done bit is set. the host cpu must not set both the phy_blk_rd_cmd bit and the phy_nblk_rd_cmd bit at the same time. the host cpu must not attempt a second phy register access until the first access is complete. when the ac- cess is complete, the phy_cmd_done bit in the phy access register and the mii management command complete interrupt (mccint) bit in the interrupt reg- ister will be set to 1, and if the corresponding enable bit is set, the host cpu will be interrupted. the host can either wait for this interrupt, or it can use some other method to guarantee that it waits for a long enough time. note that with a 2.5 mhz mdc clock it takes about 27 s to transmit a management frame with a pream- ble. however, if the auto-poll or port manager ma- chines are active, there may be a delay in sending a host generated management frame while other frames are sent. under these conditions, the host should al- ways check for command completion. for an mii management frame transmitted as the re- sult of a host cpu access to the phy access register, preamble suppression is controlled by the preamble suppression bit (pre_sup) in the phy access regis- ter. if this bit is set to 1 the preamble will be sup- pressed. otherwise, the frame will include a preamble. the host cpu should only set the preamble suppres- sion bit when accessing a register in a phy device that is known to be able to accept management frames without preambles. for phy devices that comply with clause 22 of ieee std 802.3, bit 6 of phy register 1 is fixed at 1 if the phy will accept management frames with the preamble suppressed. mii management frames transmitted as the result of a host cpu accesses to the legacy bcr33 and bcr34 registers are always sent with preambles. see appendix b, mii management registers, for de- scriptions of the standard registers that are found in ieee 802.3 compatible devices. -0#(+ as defined in the ieee 802.3 standard, the external phy attached to the am79c976 controller ? s mii has no way of communicating important timely status informa- tion back to the am79c976 controller. unless it polls the external phy ? s status register, the am79c976 con- troller has no way of knowing that an external phy has undergone a change in status. although it is possible for the host cpu to poll registers in external phy de- vices, the am79c976 controller simplifies this process by implementing an automatic polling function that pe- riodically polls up to 6 user-selected phy registers and interrupts the host cpu if the contents of any of these registers change. the automatic polling of phy registers is controlled by six 16-bit auto-poll registers, autopoll0 to autopoll5. by writing to the auto-poll registers, the user can independently define the phy addresses and register numbers for six external phy registers. the registers are not restricted to a single phy device. in the auto-poll registers there is an enable bit for each of the selected phy registers. when the host cpu sets one of these enable bits, the auto-poll logic reads the corresponding phy register and stores the result in the corresponding auto-poll data register. (there is one auto-poll data register for each of the six phy regis- ters.) thereafter, at each polling interval, the auto-poll logic compares the current contents of the selected phy register with the corresponding auto-poll data register. if it detects a change, it sets the mii manage- ment auto-poll interrupt (mapint) in the interrupt reg- ister, which causes an interrupt to the host cpu (if that interrupt is enabled). note that when the host cpu writes to one of the auto- poll registers the contents of the associated auto-poll data register are considered to be invalid during the next polling cycle so that the next polling cycle updates the appropriate auto-poll data register without caus- ing an interrupt. when the contents of one of the selected phy regis- ters changes, the corresponding auto-poll data regis- ter is updated so that another interrupt will occur when the data changes again. auto-poll register 0 differs from the other auto-poll registers in several ways. the phy address (ap_phy0_addr) field of this register defines the de- fault phy address that is used by both the auto-poll state machine and the network port manager. the 8/01/00 am79c976 85 preliminary register number field is fixed at 1 (which corresponds to the external phy status register), and the register is al- ways enabled. this means that if the auto-poll state machine is enabled, it will always poll register 1 of the default phy and will interrupt the host cpu when it de- tects a change in that register. in addition to the phy address, register number, and enable bit, the auto-poll registers contain two other control bits for each of the 5 user-selected registers. these bits are the preamble suppression (ap_pre_sup) and default phy (ap_dflt_phy) bits. if the preamble suppression bit is set, the auto-poll sends management frames to the corresponding regis- ter with no preamble field. the host cpu should only set the preamble suppression bit for registers in phy devices that are known to be able to accept manage- ment frames without preambles. for phy devices that comply with clause 22 of ieee std 802.3, bit 6 of phy register 1 is fixed at 1 if the phy will accept manage- ment frames with the preamble suppressed. if the default phy bit (ap_dflt_phy) is set, the cor- responding preamble suppression bit and phy ad- dress field are ignored. in this case the auto-poll state machine uses the default phy address from the ap_phy0_addr field, and suppresses the preamble if the network port manager logic has determined that the default phy device accepts management frames with no preamble. if the network port manager logic has not determined that the default phy device ac- cepts management frames with no preamble, the auto- poll state machine does not suppress the preamble when accessing the selected register. the auto-poll state machine is enabled when the auto- poll external phy (apep) bit (cmd3, bit 24) is set to 1. if apep is cleared to 0, the auto-poll machine does not poll any phy registers regardless of the state of the en- able bits in the auto-poll registers. the apep bit has no effect on the network port manager, which may poll the default phy even when the state of the apep bit is 0. the auto-poll ? s frequency of generating mii manage- ment frames can be adjusted by setting of the apdw bits (bcr32, bits 10-8). the delay can be adjusted from 0 mdc periods to 2048 mdc periods. 870# the am79c976 controller is unique in that it does not require software intervention to control and configure an external phy attached to the mii. this feature was included to ensure backwards compatibility with exist- ing software drivers. the am79c976 controller will op- erate with existing pcnet drivers from revision 2.5 upward (although older drivers will report incorrect sta- tistics for the am79c976 device). the heart of this au- tomatic configuration system is the network port manager. the network port manager initiates auto-negotiation in the external phy when necessary and monitors the re- sults. when auto-negotiation is complete, the network port manager sets up the mac to be consistent with the negotiated configuration. the network port man- ager auto-negotiation sequence requires that the exter- nal phy respond to the auto-negotiation request within 4 seconds. otherwise, system software will be required to properly control and configure the external phy at- tached to the mii. after auto negotiation is complete, the network port manager generates mii management frames about once every 900 ms to monitor the status of the external phy. the network port manager is enabled when the dis- able port manager (dispm) bit (cmd3, bit 14) is cleared to 0. auto-negotiation the external phy and its link partner may have one or more of the following capabilities: 100base-t4, 100base-tx full-/half-duplex, 10base-t full-/half- duplex, and mac control pause frame processing. during the auto-negotiation process the two phy de- vices exchange information about their capabilities and then select the best mode of operation that is common to both devices. the modes of operation are prioritized according to the order shown in table 11 (with the high- est priority shown at the top of the table). table 11. auto-negotiation capabilities auto-negotiation goes further by providing a message- based communication scheme called, next pages , be- fore connecting to the link partner. the network port manager does not support this feature. however, the host cpu can disable the network port manager and manage next pages by accessing the phy device through the phy access register. the host cpu can disable the network port manager by setting the dis- able port manager (dispm) bit (cmd3, bit 14) to 1. (the dispm bit corresponds to the disable auto-nego- tiation auto setup (danas) bit in bcr32 of older pcnet family devices.) network speed physical network type 200 mbps 100base-x, full duplex 100 mbps 100base-t4, half duplex 100 mbps 100base-x, half duplex 20 mbps 10base-t, full duplex 10 mbps 10base-t, half duplex 86 am79c976 8/01/00 preliminary to control the auto-negotiation process, the network port manager generates mii management frames to execute the procedure described below. (see appen- dix b, mii management registers, for the mii register bit descriptions.) the network port manager is held in the idle state while h_reset is asserted, while the eeprom is being read and while the dispm bit is set. when none of these conditions are true, the network port manager proceeds through the following steps: 1. if xphyrst is set, write to the phy ? s control reg- ister (r0) to set the soft reset bit and cause the phy to reset. the network port manager then peri- odically reads the phy ? s control register (r0) until the reset is complete. 2. if xphyrst is not set or after the phy reset is com- plete, the phy ? s status register (r1) is read. 3. if the phy ? s auto-negotiation ability bit (r1, bit 3) is 0 or if the xphyane bit in the control2 register is 0, write to the phy ? s control register (r0) to dis- able auto-negotiation and set the speed and duplex mode to the values specified by the xphysp and xphyfd bits in the control2 register ? and ? ed with the appropriate bits from the phy's technology ability field. then proceed to step 8. 4. otherwise write to the auto-negotiation advertise- ment register (r4). bits a0 to a5 of technology ability field of r4 are taken from bits 15 to 11 in r1. bit a6 of the technology ability field indicates the mac's ability to respond to mac control pause frames. this bit is set equal to the value of the ne- gotiate pause ability (npa) bit in the flow control register. the next page, acknowledge, and re- mote fault bits are set to 0, and the selector field is set to 00001 to indicate ieee std 802.3. 5. write to the control register (r0) to restart auto- negotiation. 6. poll r1 until the auto-negotiation complete bit is set to 1. 7. read the auto-negotiation link partner ability reg- ister (r5). set the mac's speed, duplex mode, and pause ability to the highest priority mode that is common to both phy devices. 8. poll r1 until the link status bit is 1. if link status is not found to be 1 after two polls at 900 ms intervals, go back to step 1. 9. poll r1 at intervals of about 900 ms until the link status bit is 0. go to step 8. when auto-negotiation is complete, the network port manager examines the mf preamble suppression bit in phy register 1. if this bit is set, the network port manager suppresses preambles on all frames that it sends until one of the following events occurs: & *!" 9 "*, :; < " = !>? a complete bit description of the mii and auto- negotiation registers can be found in appendix b. the network port manager is not disabled when the mdio pin is held low when the mii management inter- face is idle. if no phy is connected, reads of the exter- nal phy's registers will result in read errors, causing the mreint interrupt to be asserted. - +# '0.>* ( the mii management interface (mdc and mdio) can be used to manage more than one external phy de- vice. the external phy devices may or may not be con- nected to the am79c976 controller ? s mii bus. for example, two phy devices can be connected to the am79c976 controller ? s mii bus so that the mac can communicate over either a twisted-pair cable or a fiber- optic link. conversely, several am79c976 controllers may share a single integrated circuit that contains sev- eral phy devices with separate mii busses but with only one mii management bus. in this case, the mii management interface of one am79c976 controller could be used to manage phy devices connected to different am79c976 controllers. if more than one phy device is connected to the mii bus, only one phy device is allowed to be enabled at any one time. since the network port manager can not detect the presence of more than one phy on the mii bus, the host cpu is responsible for making sure that only one phy is enabled. the host cpu can use the phy access register to set the isolate bit in the con- trol register (register 0, bit 10) of any phy that needs to be disabled. ' +### !( the port manager normally sets up the speed, duplex mode, and flow control (pause) ability of the mac based on the results of auto-negotiation. however, it is possible to operate the am79c976 device with no mii management interface connection, in which case the port manager is not able to start the auto-negotiation process or set up the mac-based on auto-negotiation results. this may happen if the am79c976 controller is connected to a multi-phy device that has only one mii management interface that is shared among several phys. if the am79c976 controller is operating without a mii management interface connection to its external phy, the host cpu can force the mac into the desired state by setting the dispm bit in cmd3 register to 1 to dis- able the port manager, then writing to the following bits: 8/01/00 am79c976 87 preliminary 1. force_fd (cmd3, bit 12), 2. force_speed (ctrl2, bits 18-16), 3. force_link_stat (cmd3, bit 11), and 4. force pause ability (fpa, flow_control, bit 20). these bits set up the duplex mode, speed, and flow control ability in the mac and put the mac into the link pass state. regulating network traffic the am79c976 device provides two hardware mecha- nisms for regulating network traffic: 802.3x flow con- trol and collision-based back pressure. 802.3x flow control applies to full-duplex operation only, while back pressure applies to half-duplex operation only. 802.3x flow control works by sending and receiving mac control pause frames, which cause the receiving sta- tion to postpone transmissions for a time determined by the contents of the pause frame. back pressure forces collisions to occur when other nodes attempt to trans- mit, thereby preventing other nodes from transmitting for periods of times determined by the back-off algo- rithm. #0 ! the format of a mac control pause frame is shown in table 12. when a network station that supports ieee 802.3x flow control receives a pause frame, it must suspend transmissions after the end of any frame that was being transmitted when the pause frame arrived. the length of time for which the station must suspend transmis- sions is given in the request_operand field of the pause frame. this pause time is given in units of slot times. for 10-mbps and 100-mbps 802.3 networks, one slot time is 512 bit times. the request_operand field is in- terpreted as big-endian data--octet 17 is the most sig- nificant byte and octet 18 is the least significant byte. (70 the am79c976 device supports collision-based back pressure for congestion control when the device is op- erating in half-duplex mode. back pressure is enabled when the device is operating in half duplex mode and either the flow control command bit (fccmd, flow_control, bit 16) is set or the fc pin enable bit (fcpen, flow_control, bit 17) is set and the fc pin is asserted. when the mac begins receiving a frame that passes the address matching criteria and if back pressure is enabled, the mac will intentionally cause a collision by transmitting a ? phantom ? frame consisting of a continu- ous stream of alternating 1s and 0s. the length of the phantom frame is 568 bits so that it will be interpreted as a runt frame. back pressure does not affect the transmission of a frame. the mac will only force a collision when it be- gins to receive a new frame. the generation of a back-pressure collision causes the xmtbackpressure mib counter to increment. %5 ( traffic regulation can be controlled either by external hardware or by cpu commands. traffic regulation is af- fected by the following: * = 9 < !39 !34< 9 "*< = ! 9)!< :8# !& 3 4 ! & 94!&< ! & 9!&< the duplex mode affects the type of traffic regulation that is used. in full-duplex mode the fc pin and the fcpen, fccmd, and fixp bits control the transmis- sion of pause frames. in half-duplex mode the same pin and bits control the assertion of back pressure. also, in half-duplex mode the am79c976 device does not respond to received pause frames. the am79c976 device includes support for two styles of full-duplex flow control. in one style, which is similar to an xon-xoff protocol, a pause frame whose request_operand field (bytes 17 and 18) contains 0ffffh is sent to prevent the link partner from transmit- ting. later, a pause frame whose request_operand field contains 0 is sent to allow the link partner to resume transmissions. this style of flow control is selected by clearing the fixed length pause bit (fixp) to 0. table 12. mac control pause frame format octet numbers field name value 1-6 destination address 01-80-c2-00-00-01 7-12 source address sender ? s physical address 13-14 length/type 88-08 15-16 mac control opcode 00-01 17-18 request_operand pause time measured in slot times 19-60 pad zeros 61-64 fcs fcs 88 am79c976 8/01/00 preliminary for the other style of flow control, a single pause frame is sent to halt transmissions for a predetermined period of time. the contents of the request_operand field of this frame are taken from the pause length register. this style of flow control is selected by setting the fixed length pause bit (fixp) to 1. .8 ( the flow control pin (fc) allows external hardware to cause pause frames to be transmitted or back pressure to be asserted. the use of the fc pin for traffic regula- tion is enabled by the fc pin enable bit (enfc). when fcpen is cleared to 0, the signal on the fc pin is ig- nored. otherwise, back pressure is enabled when fc is high and the device is operating in half-duplex mode, and pause frames are sent at fc pin signal transitions when the device is operating in full-duplex mode. in full-duplex mode with the fc pin enable bit (fcpen) =1, the actions that occur at low-to-high and high-to- low transitions of the fc pin depend on the value of the fixed length pause bit (fixp). if fixp is 1, a low-to- high transition causes a pause frame to be sent with its request_operand field contents taken from the pause length register. in this case high-to-low transitions of the fc pin are ignored. if fixp is 0, a low-to-high transition sends a pause frame whose request_operand field contains 0ffffh, while a high-to-low transition sends a pause frame whose request_operand field contains 0. the effects of the fc pin are summarized in table 13. 8 ( for software control of traffic regulation the flow con- trol command bit (fccmd) mimics the fc pin. in half-duplex mode, back pressure is enabled when fccmd is set to 1, and it is disabled when fccmd is cleared to 0. in full-duplex mode, the act of setting fccmd to 1 causes a pause frame to be sent. the contents of the request_operand field of the frame depend on the state of the fixp bit. if fixp is 1, the contents of the request_operand field are copied from the pause length register. if fixp is 0, the contents of the request_operand field are set to 0ffffh. in full-duplex mode, if fixp is 0, the act of clearing fccmd to 0 causes a pause frame to be sent with its request_operand field cleared to 0. if fixp is set to 1, the fccmd bit is self-clearing--the cpu does not have to write to the am79c976 device to clear the fccmd bit. this allows the cpu to use a sin- gle write access to cause a pause frame to be sent with a predetermined request_operand field. table 13. fc pin functions fc pin transition fcpen fixp duplex mode action x 0 x x no action 0 to 1 1 x half enable back pressure 1 to 0 1 x half disable back pressure 0 to 1 1 1 full send pause frame with request operand equal to the contents of the pause length register 1 to 0 1 1 full no action 0 to 1 1 0 full send pause frame with request operand equal to 0ffffh. 1 to 0 1 0 full send pause frame with request operand equal to 0000h. 8/01/00 am79c976 89 preliminary the effects of the fccmd bit are summarized in table 14. 0 !! +0 < + when the host cpu changes the contents of the pause length register, it must make sure that no pause frame is transmitted while the register is being updated. if the host cpu can not control the state of the fc pin, it can clear the fcpen pin so that the fc pin will be ig- nored. it can then poll the pause_pending bit in the status0 register until that bit is 0. when fcpen and pause_pending are both 0, it is safe to write to the pause length register. 0%!(' the ability to respond to received pause frames, or pause ability, is controlled independently from the transmission of pause frames. when pause ability is enabled, the receipt of a pause frame causes the de- vice to stop transmitting for a time period that is deter- mined by the contents of the pause frame. pause ability is enabled by negotiate pause ability (npa, flow_control, bit 19) and force pause ability (fpa, flow_control, bit 20). if the fpa bit is set, pause ability is enabled regardless of the pause ability state of the link partner. if the npa bit is set and the fpa bit is not set, pause ability is enabled only if the auto-negotiation process determines that the link part- ner also supports 802.3x flow control. the auto-polling state machine is extended to read the external phy status registers at register locations 1, 4, and 5. (the contents of these registers are defined in the ieee p802.3u specification.) from register 1 the state machine obtains the link status and auto-negotia- tion status as well as jabber and remote fault indica- tions. if auto negotiation is complete, the logic uses the technology ability fields of the auto-negotiation adver- tisement register (register 4) and the auto-negotiation link partner ability register (register 5) to determine the network speed and duplex mode and the flow con- trol status. the mac device will be put into the speed and duplex mode for the highest common ability that the phy and its link partner share. if full-duplex mode is selected and the pause bits are set in both register 4 and register 5, pause ability will be enabled so that the mac will be able to respond to mac control pause frames as described in the ieee p802.3x specification. a mac control pause frame is any valid frame with the following: & @ "& 6 @ .:#(.# a#..#..#.:b & $ @ ((#.(b &"& @ ...: if such a frame is received while pause ability is en- abled, the mac device will wait until the end of the frame currently being transmitted (if any) and then stop transmitting for a time equal to the value of the request_operand field (octets 17 and 18) multiplied by 512-bit times. if another mac control pause frame is received before the pause timer has timed out, the pause timer will be reloaded from the request_operand field of the new frame so that the new frame overrides the earlier one. received mac control pause frames are handled completely by the am79c976 hardware. they are not passed on to the host computer. however, mac con- trol frames with opcodes not equal to 0001h are treated as normal frames, except that their reception causes the unsupported opcodes counter to be incremented. since the host computer does not receive mac control pause frames, 32-bit mib counters have been added to record the following: "& !& 3 delayed interrupts to reduce the host cpu interrupt service overhead the am79c976 device can be programmed to postpone the interrupt to the host cpu until either a programma- ble number of receive or transmit interrupt events have occurred or a programmable amount of time has table 14. fccmd bit functions fccmd transition fixp duplex mode action 0 to 1 x half enable back pressure 1 to 0 x half disable back pressure 0 to 1 1 full send pause frame with request operand equal to the contents of the pause length register. automatically clear fccmd to 0. 1 to 0 1 full no action. (fccmd is cleared automatically when fixp = 1.) 0 to 1 0 full send pause frame with request operand equal to 0ffffh. 1 to 0 0 full send pause frame with request operand equal to 0000h. 90 am79c976 8/01/00 preliminary elapsed since the first interrupt event occurred. the use of the delayed interrupt register allows the inter- rupt service routine to process several events at one time without having to return control back to the oper- ating system between events. a receive interrupt event occurs when receive inter- rupts are enabled, and the am79c976 device has com- pleted the reception of a frame and has updated the frame ? s descriptors. a receive interrupt event causes the receive interrupt (rint) bit in csr0 to be set if it is not already set. similarly, a transmit interrupt event occurs when transmit interrupts are enabled, and the am79c976 device has copied a transmit frame ? s data to the transmit fifo and has updated the frame ? s de- scriptors. a transmit interrupt event causes the trans- mit interrupt (tint) bit in csr0 to be set if it is not already set. note that frame receptions or transmis- sions affect the interrupt event counter only when re- ceive or transmit interrupts are enabled. the delayed interrupt register contains the 5-bit event count field and the 11-bit maximum delay time field. each time the host cpu clears the rint or tint bit, the contents of the event count field are loaded into an internal interrupt event counter, the contents of the maximum delay time field are loaded into an internal interrupt event timer, and the interrupt event timer is disabled. each time a receive or transmit interrupt event occurs, the interrupt event counter is decre- mented by 1 and the interrupt event timer is enabled, or if it has already been enabled, it continues to count down. once the interrupt event timer has been en- abled, it decrements by 1 every 10 microseconds. when either the interrupt event counter or the interrupt event timer reaches zero, the inta pin is asserted. external address detection interface the eadi is provided to allow external address filtering and to provide a receive frame tag word for propri- etary routing information. this feature is typically uti- lized by terminal servers, switches and/or router products. the eadi interface can be used in conjunc- tion with external logic to capture the packet destination address from the mii input data stream as it arrives at the am79c976 controller, to compare the captured ad- dress with a table of stored addresses or identifiers, and then to determine whether or not the am79c976 controller should accept the packet. the eadi consists of the external address reject (ear ), start frame-byte delimiter (sfbd), receive frame tag data (rxfrtgd), and receive frame tag enable (rxfrtge) pins. the sfbd pin indicates two types of information to the external logic--the start of the frame and byte bound- aries. the first low-to-high transition on the sfbd pin after the assertion of the rx_dv signal indicates that the first nibble of the destination address field of the in- coming frame is available on the rxd[3:0] pins. there- after, sfbd toggles with each rx_clk pulse so that sfbd is high when the least significant nibble of frame date is present on the rxd[3:0] lines and low when the most significant nibble is present. sfbd stays low when rx_dv is not asserted (which indicates that the receiver is idle). note that the sfbd signal is available on any led pin. to direct the sfbd signal to one of the led pins, the sfbde and ledpol bits should be set to 1 and the pse bit should be cleared to 0 in the appropriate led register. the sfbde bit directs the sfbd signal to the pin, the ledpol bit sets the polarity to active high and enables the totem-pole driver, and the pse bit disables the led pulse stretcher logic. if the system needs all four leds as well as the eadi function, the am79c976 controller can be programmed to use the shared pin for the led function, and the ex- ternal logic can be designed to generate the sfbd sig- nal by searching for the 11010101b start frame delimiter (sfd) pattern in the rcd[3:0] data. the external address detection logic can use the ear input to indicate whether or not the incoming frame should be accepted. if the ear signal remains high during the receive protect time, the frame will be ac- cepted and copied into host system memory. the re- ceive protect time is a period of time measured from the receipt of the sfd field of a frame. the length of the re- ceive protect time is programmable through the re- ceive protect register. a frame is accepted if it passes either the internal ad- dress match criteria or the external address match cri- teria. if the internal address logic is disabled, the acceptance of a frame depends entirely on the external address match logic. if the external address match logic is disabled, the acceptance of a frame depends entirely on the internal address match logic. internal address match is disabled when prom (csr15, bit 15) is cleared to 0, drcvbc (csr15, bit 14) and drcvpa (csr15, bit 13) are set to 1, and the logical address filter registers (csr8 to csr11) are programmed to all zeros. external address matching can be disabled by holding the ear pin low. there is no programmable bit that causes the am79c976 device to ignore the state of the ear pin. the eadi logic only samples ear from 2 nibble times after sfd until the end of the receive protect time. (see the receive protect register section.) the frame will be accepted if ear has not been asserted during this window. ear must have a pulse width of at least two bit times plus 10 ns. 8/01/00 am79c976 91 preliminary %& *( (?( ! receive frame tagging is a feature that allows the ex- ternal address detection logic to pass an identification code or tag to the am79c976 controller to be placed in the rx descriptor corresponding to a received frame. the external logic can shift this tag in as a serial bit stream on the receive frame tag data (rxfrtgd) pin. it uses the receive frame tag enable (rxfrtge) pin to indicate when the tag data is valid. the clock sig- nal for shifting in the tag data is rx_clk. see figure 3535. if the software style (swstyle) field in bcr20 con- tains the value 2 or 3, the receive frame tag can be up to 15 bits long. in this case the tag data is sampled on the low-to-high transition of rx_clk whenever rx- frtge is high. if swstlye = 5, the receive frame tag can be up to 32 bits long. in this case, the tag data is sampled on both edges of rx_clk so that the entire tag can be shifted in 16 rx_clk cycles or less, de- pending on the length of the tag. if swstyle is 0 or 4, receive frame tagging is not supported. in those cases the descriptor space is allocated to other func- tions. if swstyle = 5, tag bits are shifted in the order b31, b15, b30, b14, ? , b0, where b0 is the least significant bit of the tag. this sequence allows the external logic to be simplified slightly if the system design requires a frame tag of fewer than 17 bits. in this case the external logic can use only one clock edge to shift in the data. since the am79c976 device samples the rxfrtgd pin on both edges of rx_clk, the same data will ap- pear in the upper and lower halves of the frame tag field in the descriptor. if swstyle = 2 or 3, tag bits are shifted in the order b14, b13, ... , b0. because of the order in which frame tag bits are shifted in, if the tag is shorter than 15 bits, the tag data will be placed in the least significant portion of the receive frame tag field of the rx descriptor, and the most sig- nificant bits of the field will be cleared to zeros. rxfrtge need not be a continuous signal. it can tog- gle on and off so that the tag data can be shifted in at a slower rate than the frequency of rx_clk. the length of the frame tag is determined by the number of rx_clk cycles during which rxfrtge is asserted before the end of the frame arrives (with a maximum of 15 bits for swstyle 2 or 3 or a maximum of 32 bits for swstyle 5). the last bit of the receive frame tag must be shifted into the rxfrtgd input at least one rx_clk cycle before rx_dv is de-asserted. the receive frame tagging feature is enabled by the rxfrtagen bit in the command1 register. when this bit is cleared to 0, the receive frame tag field of the rx descriptor will be filled with zeros. )#( ! external memory interface the am79c976 controller contains an external mem- ory interface that supports flash (or eprom) devices as boot devices, as well as ssram for frame data stor- age. the controller provides read and write access to flash or eprom. no glue logic is required for the memory interface. the am79c976 device contains a built-in self test sys- tem (mbist) that can be programmed to run a diag- nostics test on the external ssram. the external ssram is organized around a 32-bit data bus. the memory can be as large as 1m x 32 bits. the memory devices can be either jedec standard pipe- line burst synchronous static ram devices (pb-ss- ram) or zbt ? synchronous static ram (zbt- ssram) with pipelined outputs. the sram_type field of the control1 register must be initialized to indicate which type of ssram is actually used. rx_clk rx_dv miirxfrtge miirxfrtgd sf/bd 92 am79c976 8/01/00 preliminary the contents of the sram_type field are defined in table 15. the width of the flash memory (or eprom) is 8 bits. the memory can be as large as 16m x 8 bits. the external memory bus uses the same address, data, and control pins to access both flash and ssram memory, but it has separate chip select (or chip enable) pins so that only one device can be se- lected at a time. flcs selects the flash memory, while erce selects the ssram. the flash memory must not be accessed when the am79c976 controller is run- ning (when the run bit in cmd0 is set to 1). any ac- cess to the flash memory clears the run bit and thereby abruptly stops all network and dma opera- tions. era[19:0] provides 20 bits of address for the ssram and the lower 20 bits of address for the flash memory. the higher 4 bits of address for the flash memory are shared with bits [11:8] of the ssram data bus (erd[11:8]). the lower 8 bits of the external memory data bus erd[7:0] are used by both the ssram and the flash. the high order 20 bits of the external mem- ory data bus erd[31:12] are used only by the ssram. the output enable signal for the flash (floe ) shares a pin with the ssram address advance signal (eradv). figure 36 shows how the ssram and flash can be connected to the am79c976 controller. %&' #-* ((( the am79c976 controller supports eprom or flash as an expansion rom boot device. both are config- ured using the same methods and operate the same. see figure 3636. see the previous section on expan- sion rom transfers for the pci timing and functional description of the transfer method. ,%&# + table 15. sram_type field encoding sram_type[1:0] external memory type 00 reserved 01 zbt 10 reserved 11 pipelined burst erclk eroe a[19:0] dq[7:0] oe cs l4 controller flash a[23:20] we ssram clk a[16:0] ce1 or ce2 d[31:0] oe gw or r/w adv adsp or cen ce era[19:0] erd[31:0] erwe/flwe eradv/floe eradsp/cen erce flcs 8 20 4 17 20 [11:8] [7:0] a17 8/01/00 am79c976 93 preliminary the am79c976 controller will always read four bytes for every host expansion rom read access. the inter- face to the expansion bus is timed by an internal signal called romclk, which runs at one fourth of the fre- quency of the external memory interface clock (er- clk). thus, when the clock select pins are configured so that erclk runs at 90 mhz; romclk runs at 22.5 mhz. the time that the am79c976 controller waits for data to be valid is programmable. romtmg (ctrl0, bits 8-11 or bcr18, bits 15-12) defines the time from when the am79c976 controller drives era[19:0] with the expan- sion rom address to when the am79c976 controller latches in the data on the erd[7:0] inputs. the register value specifies the time in number of romclk cycles. when romtmg is set to nine (the default value), erd[7:0] is sampled with the next rising edge of rom- clk ten cycles after era[19:0] was driven with a new address value. the clock edge that is used to sample the data is also the clock edge that generates the next expansion rom address. all four bytes of expansion rom data are stored in holding registers. because expansion rom accesses take longer than 16 pci bus clock cycles, the pci access will be discon- nected with no data transfer after 15 clocks. subse- quent accesses will be retried until all four bytes have been read from the expansion rom. the timing diagram in figure 37 assumes the default programming of romtmg (1001b = 9 clk). after reading the first byte, the am79c976 controller reads in three more bytes by incrementing the lower portion of the rom address. the pci bus logic generates discon- nect/retry cycles until all 32 bits are ready to be trans- ferred over the pci bus. when the host tries to perform a burst read of the expansion rom, the am79c976 controller will disconnect the access at the second data phase. /%&' # 3( the host must program the expansion rom base ad- dress register (rombase) in the pci configuration space before the first access to the expansion rom. the am79c976 controller will not react to any access to the expansion rom until both memen (pci com- mand register, bit 1) and romen (pci expansion rom base address register, bit 0) are set to 1. the amount of memory space that the am79c976 de- vice will claim for the expansion rom depends on the contents of the expansion rom configuration register (rom_cfg), which should be loaded from the ee- prom. this register is included in the am79c976 de- vice so that the controller can accommodate roms of different sizes without wasting memory space. the rom occupies a block of memory space that is some power of two between 2k and 16m in size. if the rom requires 2 n bytes of address space, bits 1 through n-1 of the expansion rom base address register in pci configuration space (rombase) should appear to be wired to 0. the contents of the expansion rom config- uration register (rom_cfg) determine how many bits of the configuration space register are forced to 0. bits [15:1] of rom_cfg correspond to bits [23:9] of rombase and bit 0 of rom_cfg corresponds to bit 0 of rombase. if a bit in rom_cfg is set to 0, the corresponding bit in rombase is fixed at zero. if a bit in rom_cfg is set to 1, the corresponding bit in rom- romclk era[19:0] erd[7:0] flcs floe flwe 94 am79c976 8/01/00 preliminary base can be programmed to 0 or 1 through pci con- figuration space accesses to rombase. bit 0 of rom_cfg controls bit 0 of rombase. if bit 0 of rom_cfg is 0, the host cpu cannot write to bit 0 of rombase. this bit is the address decode enable bit. when this bit is fixed at 0, it will appear to the host cpu that the rom base address register and, therefore, the expansion rom does not exist. if bit 0 of rom_cfg is set to 1, the host cpu is able to read and write bit 0 of rombase. as an example, if the expansion rom occupies 2 16 (65536) bytes, bits 15:9 of rombase should be fixed at 0. since bits 15:9 of rombase are controlled by bits 7:1 of rom_cfg, bits 7:1 of rom_cfg should be cleared to 0 and bits 15:8 should be set to 1. to make rombase accessible to the host cpu, bit 0 of rom_cfg should be set to 1. therefore, rom_cfg should be set to ff01h. if the host cpu writes all 1s to the rombase register and then reads back the con- tents of rombase, the result would be ffff0001h. after the host cpu has written to the expansion rom base address register in pci configuration space to map the rom into pci memory space and to enable accesses to the rom, the address output to the expan- sion rom will be the offset from the address on the pci bus to rombase. the am79c976 controller aliases all accesses to the expansion rom of the command types memory read multiple and memory read line to the basic memory read command. since setting memen also enables memory mapped access to the i/o resources, attention must be given to the pci memory mapped i/o base address register, before enabling access to the expansion rom. the host must set the pci memory mapped i/o base ad- dress register to a value that prevents the am79c976 controller from claiming any memory cycles not in- tended for it. during the boot procedure, the system will try to find an expansion rom. a pci system assumes that an ex- pansion rom is present when it reads the rom signa- ture 55h (byte 0) and aah (byte 1). * ( +(( in addition to mapping the flash memory into pci ad- dress space, the am79c976 controller provides an in- direct read/write data path for programming the flash memory. the flash is accessed by first writing the memory address to the flash address register, and then reading or writing the flash data register. for software compatibility with older pcnet devices, the flash device can also be accessed by a read or write to the expansion bus data port (bcr30). the user must load the upper address epaddru (bcr 29, bits 3-0). epaddru is not needed if the flash size is 64k or less, but still must be programmed. the user will then load the lower 16 bits of address, epaddrl (bcr 28, bits 15-0). # /!" a read to the flash data register will start a read cycle on the external memory interface. the am79c976 controller will drive erd[11:8] with the 4 most signifi- cant address bits at the same time that it drives era[19:0] with the 20 least significant bits. the flcs pin is driven low for the value romtmg + 1. figure 38 assumes that romtmg is set to nine. erd[7:0] is sampled with the next rising edge of clk ten clock cycles after era[19:0] was driven with a new address value. this pci slave access to the flash/ eprom will result in a retry for the very first access. subsequent accesses may give a retry or not, depend- ing on whether or not the data is present and valid. the access time is dependent on the romtmg bits (ctrl0, bits 11-8, or bcr18, bits 15-12) and can be tuned for the particular memory device used. this access mechanism using bcr28, 29, and 30 dif- fers from the expansion rom access mechanism since only one byte is read in this manner, instead of the 4 bytes in an expansion rom access. if the lower address auto increment (laainc) bit (flash_addr, bit 31 or bcr29, bit 14) is set, the ebaddrl address will be incremented and a continu- ous series of reads from the expansion data port (flash_data or ebdata, bcr30) is possible. the upper address field, ebaddru, is not automatically incremented when the lower address field, ebaddrl rolls over. the flash write procedure is almost identical to the read access, except that the am79c976 controller will not drive floe low. the flcs and flwe signals are driven low for the value romtmg again. the write to the flash port is a posted write and will not result in a retry to the pci, unless the host tries to write a new value before the previous write is complete. then the host will experience a retry. see figure 3939. 8/01/00 am79c976 95 preliminary 1 +!%&' *0 2 + 3( # the am79c976 controller uses external ssram for re- ceive and transmit fifos. the size of the ssram can be up to 4 mbytes, organized as 1m x 32 bits. the size of the ssram is indicated by the contents of the ssram size register (or bcr25). sram_size should be loaded from the eeprom. the ssram is programmed in units of 512-byte pages. to specify how much of the ssram is allocated to transmit and how much is allocated to receive, the user should program sram_bnd register (or bcr26, bits 15-0) with the page boundary where the receive buffer begins. the sram_bnd is also programmed in units of 512-byte pages. the transmit buffer space starts at 0000h. it is up to the user or the software driver to split up the memory for transmit or receive; there is no de- faulted value. the minimum ssram size required is four 512-byte pages for each transmit and receive queue, which limits the ssram size to be at least 4 kbytes. the sram_bnd upon h_reset will be reset to 0000h. sram_bnd must be programmed to a non- zero value if the transmitter is enabled. sram_bnd should be programmed to a value larger than the max- imum frame size to use the automatic retransmission options, rex_uflo, rex_rtry, and rtry_lcol, or if the transmit fifo start point, xmtsp, is set to full frame. (xmtsp is ctrl1, bits 17-16, or csr80, bits 11-10.) the am79c976 controller does not allow software di- agnostic access to the sram as do older devices in the pcnet family. the am79c976 controller provides soft- ware access to an internal memory built-in self-test (mbist) controller which runs extensive, at-speed romclk era[19:0] flcs floe erd[7:0] flwe romclk era[19:0] flcs floe erd[7:0] flwe 96 am79c976 8/01/00 preliminary tests on the external sram, internal sram access logic, and the pc board interconnect. the mbist controller can determine the size of the ex- ternal sram and verify its operation using the following procedure: 1. program sram_size to the minimum allowed value of 4. 2. write dm_start and dm_fail_stop (write datambist bits 63:56 with 0x28). the remainder of the datambist register ignores writes so it may be written with arbitrary data or not written at all. 3. read dm_done (datambist bit 63) and dm_error (datambist bit 62) until dm_done is set. 4. if dm_error is set, the memory is defective; re- port the error and exit. 5. program sram_size to the maximum value of 0x8000 and repeat steps 2 and 3. 6. if dm_error is zero, report the current value of sram_size as the ssram size. 7. if dm_error is set, program sram_size to one- half the maximum (0x4000) and repeat steps 2 and 3. 8. repeat, using the binary search algorithm, until the sram size has been determined. eeprom interface the am79c976 device includes an interface to an op- tional 16-bit word-oriented 93cxx-compatible serial eeprom that supports automatic address increment- ing (sequential read). this eeprom can be used for storing initial values for am79c976 registers. the con- tents of this eeprom are automatically loaded into the selected registers after a reset operation or whenever the host cpu requests an eerom read operation. note that if the eeprom is not included in the system, the mac address (and magic packet information, if needed) must be initialized by the host cpu. the am79c976 device automatically detects the size of the eeprom. when the eeprom decodes a read command, it drives its do pin low when the a0 address bit is written to the di pin. the am79c976 device uses this fact to detect the number of bits in the eeprom address and from this determines the eeprom size. data in the eeprom are interpreted as three-byte entries that contain register address and register data so that the system designer can choose which regis- ters will automatically be loaded. in a typical system, the eeprom would be used to initialize the device ? s ieee 802 physical address, the pci subsystem vendor id, led configuration, ssram configuration, and other hardware configuration information. for compatibility with older pcnet family software the address prom space should be loaded from the eeprom. see the address prom space section for details. only the memory-mapped registers can be loaded from the eeprom. while the csrs and bcrs are not memory-mapped, all useful bits in the csrs and bcrs are aliased into memory-mapped registers so that all useful bits can be loaded from the eeprom. most of the memory-mapped registers are 32 bits wide and occupy 4 bytes of memory space each. for exam- ple, the cmd2 register is located at offset 50h from the memory base address. its least significant 16 bits can be accessed at offset 50h, and its most significant 16 bits can be accessed at offset 52h. register data are loaded from the eeprom 16 bits at a time, so that the high order bits of a register are loaded independently from the low order bits. the eeprom access register gives the host cpu di- rect access to the interface pins so that it can read from or write to the eeprom. ! (%%0 # ' after the trailing edge of the reset signal or after the pread bit in bcr19 is set, the am79c976 device be- gins to read data from the eeprom. data from the ee- prom are interpreted as a string of 3-byte entries. each entry contains a 1-byte register address and a 2-byte register data field. the register address field contains the offset of the target register divided by 2. the initialization logic writes the contents of the register data field into the register selected by the register ad- dress byte. since eeprom data are loaded two bytes at a time, the least significant bit of the target register offset is omitted from the address field. only bits 8:1 are in- cluded. therefore, the register address byte contains the offset of the target register divided by two. for ex- ample, the control2 register (ctrl2) is a 32-bit regis- ter located at offset 70h (relative to the contents of the memory-mapped i/o base address register). there- fore, the byte stream 38h, 02h, 05h would cause the value 0205h to be loaded into bits [15:0] of ctrl2, and 39h, 00h, 03h would cause the value 0003h to be loaded into bits [31:16] of the same register. if the value of the address byte is 0ffh, the following 2-byte field is interpreted as a 16-bit crc code rather than as register data. the crc code covers all eeprom data up to and including the address byte of the entry containing the crc. all eeprom data after the crc code word are ignored. the crc code used is crc-16, which is based on the generator polynomial x 16 + x 15 + x 2 + 1. the eeprom must contain data for an odd number of registers so that the crc is aligned on a 16-bit word 8/01/00 am79c976 97 preliminary boundary in the eeprom. if an even number of regis- ters need to be loaded from the eeprom, two dupli- cate entries for the same register can be included so that the crc is aligned properly. for full compatibility with legacy magic packet soft- ware, the eeprom should initialize both the aprom area (offset 0-0fh) and the padr register. data are shifted into or out of the eeprom most sig- nificant bit first. figure 41 shows the mapping of the 3-byte entries into the 16-bit word-oriented eeprom. if the am79c976 device detects a crc error in the ee- prom or fails to detect the presence of an eeprom, it restores all registers to their default values and clears the pvalid bit in bcr19 to indicate the error. "4%%0 #*! "%%0 #%$0 & *&&+:c-(/ *&&+'-./ 3 : * % :a' & *&&+:c-(/ *&&+'-./ . +:c-(/ +'-./ % . &* : *&&+:c-(/ *&&+'-./ d : &* a *&&+:c-(/ *&&+'-./ d . &* , *&&+:c-(/ *&&+'-./ &* ; *&&+:c-(/ *&&+'-./ : % - 98 am79c976 8/01/00 preliminary note: all registers are restored to their default values, not just those registers that were altered by the ee- prom read operation. if the am79c976 device detects a correct crc code, it sets the pvalid bit to 1 to indicate that the registers have been successfully initialized. the cpu can initiate an automatic eeprom read op- eration at any time by setting the pread bit in bcr19 to 1. the cpu cannot access any am79c976 register while an automatic eeprom read operation is in progress. if the cpu attempts to access a register during this time, the am79c976 controller will terminate the access at- tempt by asserting devsel and stop while trdy is not asserted, a combination that indicates that the initi- ator must disconnect and retry the access at a later time. the automatic read operation takes about 180 s for each 16-bit register that is initialized plus 180 s for the crc code word. !!" when the address field of an eeprom instruction is shifted in through the di pin of the eeprom, the eeprom drives its do pin low when the a0 bit ap- pears on the di pin. the am79c976 controller makes use of this feature to detect the presence of an eeprom. when the device attempts to read the first word from the eeprom and if the eedo pin is not driven low before the 15th eesk clock cycle, the device assumes that there is no eeprom present. * the user can directly access the port through the eeprom access register (bcr19). this register con- tains bits that can be used to control the interface pins. by performing an appropriate sequence of accesses to bcr19, the user can effectively write to and read from the eeprom. this feature may be used by a system configuration utility to program hardware configuration information into the eeprom. !!" (( (# # the eeprom interface logic first shifts each 16-bit word from the eeprom most significant bit first into an internal holding register. then it shifts the word through the crc logic least significant bit first, effectively swap- ping the bytes. therefore, the data shown in figure 42 are processed by the crc logic in the following order: data[15:8], adr1, adr2, data[7:0], data[7:0], data[15:8], ... . " 8 led support the am79c976 controller can support up to four leds. led outputs led0 , led1 , and led2 allow for direct connection of an led and its supporting pull-up device. in applications that want to use the pin to drive an led and also have an eeprom, it might be necessary to buffer the led3 circuit from the eeprom connection. when an led circuit is directly connected to the eedo/led3 /rxfrtgd pin, then it is not possible for most eeprom devices to sink enough i ol to maintain a valid low level on the eedo input to the am79c976 controller. use of buffering can be avoided if a low power led is used. each led can be programmed through a bcr register to indicate one or more of the following network statuses or activities: collision status, full-duplex link data[15:8] adr1 adr2 data[7:0] data[7:0] data[15:8] data[15:8] adr3 . . . data[15:8] adr1 crc logic 15 0 15 0 holding register + + + ... x 2 x 15 x 16 eeprom am79c976 controller 8/01/00 am79c976 99 preliminary status, receive match, receive status, magic packet, transmit status, and start frame/byte delimiter. the led pins can be configured to operate in either open-drain mode (active low) or in totem-pole mode (active high). the output can be stretched to allow the human eye to recognize even short events that last only several microseconds. after h_reset, the four led outputs are configured as shown in table 16. for each led register, each of the status signals is and ? d with its enable signal, and these signals are all or ? d together to form a combined status signal. each led pin combined status signal can be programmed to run to a pulse stretcher, which consists of a 3-bit shift register clocked at 38 hz (26 ms). the data input of each shift register is normally at logic 0. the or gate output for each led register asynchronously sets all three bits of its shift register when the output becomes asserted. the inverted output of each shift register is used to control an led pin. thus, the pulse stretcher provides 2 to 3 clocks of stretched led output, or 52 ms to 78 ms. see figure 4343. b " <%*< ( power savings mode 08# !'' the am79c976 controller supports power manage- ment as defined in the pci bus power management in- terface specification v1.1 and network device class power management reference specification v1.0. these specifications define the network device power states, pci power management interface including the capabilities data structure and power management registers block definitions, power management events, and onnow network wake-up events. in addition, the am79c976 controller supports legacy power manage- ment schemes, such as remote wake-up (rwu) mode. the rwu mode can accommodate systems that sleep with pci bus power off or on and the pci clock running or stopped. the rwu pin can drive the cpu's system management interrupt (smi) line or a system power controller. the general scheme for the am79c976 controller power management is that when a wake-up event is detected, a signal is generated to cause hardware ex- ternal to the am79c976 device to put the computer into the working (s0) mode. the am79c976 device sup- ports three types of wake-up events: " ! 0 * 0 ! " * the am79c976 device supports two types of wake-up control mechanisms: table 16. led default configuration led output indication driver mode pulse stretch led0 link status open drain - active low enabled led1 activity open drain - active low enabled led2 speed open drain - active low enabled led3 coll open drain - active low enabled col cole fdls fdlse lnks lnkse rcv rcve rcvm rcvme xmt xmte to pulse stretcher mr_speed_sel 100e mps mpse 22929b-45 100 am79c976 8/01/00 preliminary ! % ! " # 9 4 < 0# d 9 < 0# all three wake-up events and both control mechanisms support wake-up from any power state including d3 cold (pci bus power off and clock stopped). figure 44 shows the relationship between these wake-up events and the various outputs used to signal to the external hardware. "" 8( * ! , + $0 the system software enables the pme pin by setting the pme_en bit in the pmcsr register (pci configura- tion registers, offset 48h, bit 8) to 1. when a wake-up event is detected, the am79c976 device sets the pme_status bit in the pmcsr register (pci configu- ration registers, offset 48h, bit 15). setting this bit causes the pme signal to be asserted. assertion of the pme signal causes external hardware to wake up the cpu. the system software then reads the pmcsr register of every pci device in the system to determine which device asserted the pme signal. when the software determines that the signal came from the am79c976 device, it writes to the device ? s pmcsr to put the device into power state d0. the soft- ware then writes a 0 to the pme_status bit to clear the bit and turn off the pme signal, and it calls the de- vice ? s software driver to tell it that the device is now in state d0. the system software can clear the pme_status bit either before, after, or at the same time that it puts the device back into the d0 state. mpdetect mppen_ee pg mpen_ee mpint led wumi magic packet link change lcmode_ee link change mpmat lcdet d r q q set clr pmat1 d q q set clr d q q set clr d q q set clr pmat pattern match input pattern pme_status pme status pme_en mpmat pme_en_ovr lcevent pme rwu s r q q set clr por por h_reset por por data from pci bus mppen_sw mpen_sw pmat0 pattern match ram (pmr) pmat_mode lcmode_sw 8/01/00 am79c976 101 preliminary the type of wake-up is configured by software using the bits lcmode_sw, pmat_mode, mpen_sw and mppen_sw in the cmd7 register. these bits are only reset by the power-on reset (por) and are not loaded from the eeprom so that they will maintain value across pci bus resets and eeprom read operations. + + $0 the rwu wake-up mechanism is used by systems that do not have software support for the pci bus power management interface. the wake-up may be config- ured and controlled completely in hardware, using the eeprom to load am79c976 controller registers and using the pg pin to enable wake-up. alternatively, if the pci bus power is never removed, wake-up may be con- figured and enabled by software. to accommodate systems with hardware that connects pme to the system power control logic running soft- ware that is not aware of the pci bus power manage- ment interface, the rwu signal may be routed to the pme pin by setting the pme_en_ovr bit (cmd3, bit 4). this is typically set by the eeprom. the rwu wake-up is configured by using the bits lcmode_ee, mpen_ee, mppen_ee, pme_en_ovr, rwu_pol, rwu_driver and rwu_gate in the cmd3 register. these bits are reset by h_reset and may be loaded from the eeprom. the pattern match wake-up event is not supported by the rwu wake-up mechanism. for legacy system support, the magic packet wake-up event may be routed to the inta pin or to any of the four led pins. ( link change detect is one of the wake-up events that is defined by the onnow specification and is supported by the rwu mode. link change detect mode is set when the lcmode_ee bit (cmd3, bit 5) is set either by software or loaded through the eeprom or when the lcmode_sw bit (cmd7, bit 0) is set by software. when this bit is set, any change in the link status will cause the lc_det bit (stat0, bit 10) to be set. when the lc_det bit is set, the rwu pin will be asserted and the pme_status bit (pmcsr register, bit 15) will be set. if either the pme_en bit (pmcsr, bit 8) or the pme_en_ovr bit (cmd3, bit 4) are set, then the pme signal will also be asserted. the am79c976 controller may be configured to enter link change detect mode immediately upon initial power-up, regardless of the presence or absence of pci bus power. this is accomplished by setting the lcmode_ee bit from the eeprom. " " a magic packet is a frame that is addressed to the am79c976 controller and contains a data sequence made up of 16 consecutive copies of the device ? s phys- ical address (padr[47:0]) anywhere in its data field. the frame must also cause an address match. by de- fault, it must be a physical address match, but if the mpplba bit (cmd3, bit 9) is set, logical and broadcast address matches are also accepted. regardless of the setting of mpplba, the sequence in the data field of the frame must be 16 repetitions of the am79c976 de- vice ? s physical address (padr[47:0]). magic packet mode is enabled by setting the mpen_sw bit (cmd7, bit 1) or the mpen_ee bit (cmd3, bit 6). alternatively, magic packet mode may be enabled by setting the mppen_sw bit (cmd7, bit 2) or the mppen_ee bit (cmd3, bit 8) and deasserting the pg pin. magic packet mode is disabled by clearing the enable bit(s) or, if only mppen_ee and/or mppen_sw are set, by asserting pg. the am79c976 controller may be configured to enter magic packet mode immediately upon initial power-up if pci bus power is off. this is accomplished by setting the mppen_ee bit from the eeprom and enabling magic packet mode by the deassertion of pg. enabling magic packet mode has a similar effect to that of suspending both transmit and receive. after the fifos have emptied, no frames will be transmitted or received until magic packet mode is disabled. the wumi output will be asserted when magic packet mode is enabled. when the am79c976 controller detects a magic packet frame, it sets the mp_det bit (stat0, bit 11), the mpint bit (int0, bit 13), and the pme_status bit (pmcsr, bit 15). the rwu pin will also be asserted and if the pme_en or the pme_en_ovr bits are set, then the pme signal will be asserted as well. if intren (cmd0, bit 1) and mpinten (inten0, bit 13) are set to 1, inta will be asserted. any one of the four led pins can be programmed to indicate that a magic packet frame has been received. mpse (led0-3, bit 9) must be set to 1 to enable that function. note: the polarity of the led pin can be programmed to be active high by setting ledpol (led0-3, bit 14) to 1. once a magic packet frame is detected, the am79c976 controller will discard the frame internally, but will not resume normal transmit and receive opera- tions until magic packet mode is disabled. once both of these events has occurred, indicating that the system has detected the magic packet and is awake, the con- troller will continue polling receive and transmit de- scriptor rings where it left off. it is not necessary to re-initialize the device. if the part is re-initialized, the in- 102 am79c976 8/01/00 preliminary ternal pointers to the current descriptors will be lost, and the am79c976 controller will not start where it left off. if magic packet mode is disabled by the assertion of pg, then in order to immediately re-enable magic packet mode, the pg pin must remain asserted for at least 200 ns before it is deasserted. if magic packet mode is disabled by clearing the register bits, then it may be immediately re-enabled by setting mpen_ee or mpen_sw back to 1. the pci bus interface clock (clk) is not required to be running while the device is operating in magic packet mode. either of the inta , the led pins, rwu, or the pme signal may be used to indicate the receipt of a magic packet frame when the clk is stopped. , " " in the onnow pattern match mode, the am79c976 controller compares the incoming packets with up to eight patterns stored in the pattern match ram (pmr). the stored patterns can be compared with part or all of incoming packets, depending on the pattern length and the way the pmr is programmed. when a pattern match has been detected, then pmat_det bit (stat0, bit 12) is set. this causes the pme_status bit (pmcsr, bit 15) to be set, which in turn will assert the pme pin if the pme_en bit (pmcsr, bit 8) is set. pattern match mode is enabled by setting the pmat_mode bit (cmd7,bit 3).the run bit (cmd0, bit 0) and rx.suspend bit (cmd0, bit 3) must also be set. if using the legacy registers, strt (csr0, bit 1) and spnd (csr5, bit 0) must be set. because pattern match mode must be configured by software, it is not possible to enable pattern match mode directly from the eeprom. " " &"' the pmr is organized as an array of 64 words by 40 bits as shown in figure 45. the pmr is programmed indirectly through the pmat0 and pmat1 registers. for compatibility with legacy controllers, the pmr may also be programmed through bcr45, bcr46, and bcr47. pattern match mode must be disabled (pmat_mode bit cleared) to allow reading or writing the pmr. a write access to the pmr begins with a write to the pmat0 register. bits 6:0 of pmat0 specify the address in the pmr and bits 31:8 contain the data to be written to bits 23:0 of the specified address in the pmr. this is followed by a write to the pmat1 register, with bits 15:0 of pmat1 containing the data to be written to bits 39:24 of the specified address in the pmr. the actual write to the pmr occurs when pmat1 is written. a read access to the pmr also begins with a write to the pmat0 register. bits 6:0 of pmat0 specify the ad- dress in the pmr to be read and the remaining bits of pmat0 are ignored. this write is followed by a read of pmat0, which returns bits 23:0 of pmr in bit positions 31:8 and a read of pmat1, which returns bits 39:24 of pmr in bit positions 15:0. these reads may be done in any order. the first two 40-bit words in the pmr serve as pointers and contain enable bits for the eight possible match patterns. the remainder of the ram contains the match patterns and associated match pattern control bits. byte 0 of the first word contains the pattern enable bits. any bit position set in this byte enables the corre- sponding match pattern in the pmr. as an example, if bit 3 is set, then pattern 3 is enabled for matching. bytes 1 to 4 in the first word are pointers to the begin- ning of the patterns 0 to 3, and bytes 1 to 4 in the sec- ond word are pointers to the beginning of the patterns 4 to 7, respectively. byte 0 of the second word has no function associated with it. byte 0 of words 2 to 63 is the control field of the pmr. bit 7 of this field is the end of pattern (eop) bit. when this bit is set, it indi- cates the end of a pattern in the pmr. bits 6-4 of the control field byte are the skip bits. the value of the skip field indicates the number of the dwords to be skipped before the pattern in this pmr word is compared with data from the incoming frame. a maximum of seven dwords may be skipped. bits 3-0 of the control field byte are the mask bits. these bits correspond to the pattern match bytes 3-0 of the same pmr word (pmr bytes 4-1). if bit n of this field is 0, then byte n of the corresponding pattern word is ignored. if this field is programmed to 3, then bytes 0 and 1 of the pattern match field (bytes 2 and 1 of the word) are used and bytes 3 and 2 are ignored in the pattern matching operation. the contents of the pmr are not affected by any reset. the contents are undefined after a power-up reset (por). 8/01/00 am79c976 103 preliminary ")0#(+# ieee 1149.1 (1990) test access port interface an ieee 1149.1-compatible boundary scan test ac- cess port is provided for board-level continuity test and diagnostics. all digital input, output, and input/output pins are tested. the following paragraphs summarize the ieee 1149.1-compatible test functions imple- mented in the am79c976 controller. $( ( the boundary scan test circuit requires four pins (tck, tms, tdi and tdo), defined as the test access port (tap). it includes a finite state machine (fsm), an in- struction register, a data register array. internal pull-up resistors are provided for the tdi, tck, and tms pins. 0 #(+ the tap engine is a 16-state finite state machine (fsm), driven by the test clock (tck), and the test mode select (tms) pins. the fsm is reset when tms and tdi are high for five tck periods. '' ( in addition to the minimum ieee 1149.1 requirements (bypass, extest, and sample instructions), three additional instructions (idcode, tribyp, and set- byp) are provided to further ease board-level testing. all unused instruction codes are reserved. see table 17 for a summary of supported instructions. bcr bit number bcr 47 bcr 46 bcr45 15 8 7 0 15 8 7 0 15 8 pmat1 pmat0 15 8 7 0 31 24 23 16 15 8 pmr_b4 pmr_b3 pmr_b2 pmr_b1 pmr_b0 pattern match ram address pattern match ram bit number 39 32 31 24 23 16 15 8 7 0 comments 0 p3 pointer p2 pointer p1 pointer p0 pointer pattern enable bits first address 1 p7 pointer p6 pointer p5 pointer p4 pointer x second address 2 data byte 3 data byte 2 data byte1 data byte 0 pattern control start pattern p 1 2+n data byte 4n+3 date byte 4n+2 data byte 4n+1 data byte 4n+0 pattern control end pattern p 1 j data byte 3 data byte 2 data byte 1 data byte 0 pattern control start pattern p k j+m data byte 4m+3 data byte 4m+2 data byte 4m+1 data byte 4m+0 pattern control end pattern p k 7 6 5 4 3 2 1 0 eop skip mask 104 am79c976 8/01/00 preliminary instruction register and decoding logic after the tap fsm is reset, the idcode instruction is always invoked. the decoding logic gives signals to con- trol the data flow in the data registers according to the current instruction. $( each boundary scan register (bsr) cell has two stages. a flip-flop and a latch are used for the serial shift stage and the parallel output stage, respectively. there are four possible operation modes in the bsr cell shown in table 18. +* other data registers are the following: 1. bypass register (1 bit) 2. device id register (32 bits) (table 19). . note: the content of the device id register is the same as the content of csr88. reset there are five different types of reset operations that may be performed on the am79c976 device, h_reset, ee_reset, s_reset, stop, and por. the following is a description of each type of reset operation. .@%% hardware reset (h_reset) is an am79c976 reset operation that has been created by the proper asser- tion of the rst pin of the am79c976 device while the pg pin is high. when the minimum pulse width timing as specified in the rst pin description has been satis- fied, then an internal reset operation will be performed. h_reset will program most of the csr and bcr reg- isters to their default value. note that there are several csr and bcr registers that are undefined after h_reset. see the sections on the individual registers for details. h_reset will clear most of the registers in the pci configuration space. h_reset will reset the internal state machines. following the end of the h_reset op- eration, the am79c976 controller will attempt to read the eeprom device through the eeprom interface. h_reset will clear dwio (bcr18, bit 7) and the am79c976 controller will be in 16-bit i/o mode after the reset operation. a dword write operation to the rdp (i/o offset 10h) must be performed to set the device into 32-bit i/o mode. %%@%% prior to starting a read of the serial eeprom, the am79c976 controller resets all the registers that can be programmed from the eeprom. this provides a consistent starting point for register programming. ee_reset is also generated following eeprom read if the eeprom crc check fails. table 17. ieee 1149.1 supported instruction summary instruction name instruc- tion code description mode selected data register extest 0000 external te s t test bsr idcode 0001 id code inspection normal id reg sample 0010 sample boundary normal bsr tribyp 0011 force float normal bypass setbyp 0100 control boundary to 1/0 te s t b y p a s s bypass 1111 bypass scan normal bypass table 18. bsr mode of operation : a , ; table 19. device id register bits 31-28 version bits 27-12 part number: 0010 0110 0010 1000b (2628h) bits 11-1 manufacturer id. the 11 bit manufacturer id code for amd is 00000000001 in accordance with jedec publication 106-a. bit 0 always a logic 1 8/01/00 am79c976 105 preliminary @%% s_reset is provided for compatibility with previous pcnet family devices. s_reset occurs when the host cpu reads the reset register, which is located at offset 14h if the device is operating in word i/o mode or at off- set 18h in dword i/o mode. s_reset has the same effect as setting stop except that s_reset resets some control and status regis- ter (csr) bits that stop does not change. see the de- scriptions of individual control and status registers for details about which bits are affected. s_reset does not trigger an automatic eeprom read sequence. new software should not use s_reset. it should be replaced by a combination of clearing the run bit in the cmd0 register followed by explicit setting or clear- ing of control bits as required. 0 a stop reset is generated by the assertion of the stop bit in csr0. writing a 1 to the stop bit of csr0, when the stop bit currently has a value of 0, will initiate a stop reset. if the stop bit is already a 1, then writ- ing a 1 to the stop bit will not generate a stop reset. stop will reset all or some portions of csr0, 3, and 4 to default values. for the identity of individual csrs and bit locations that are affected by stop, see the in- dividual csr register descriptions. stop will not affect any of the bcr and pci configuration space locations. stop will reset the internal state machines. following the end of the stop operation, the am79c976 control- ler will not attempt to read the eeprom device. stop terminates all network activity abruptly. the host can use the suspend mode (spnd, csr5, bit 0) to ter- minate all network activity in an orderly sequence be- fore setting the stop bit. 08 power on reset (por) is generated when the am79c976 controller is powered up. por generates a hardware reset (h_reset). in addition, it clears some bits that h_reset does not affect. %&0.> the am79c976 controller provides the phy_rst pin which may be connected to the reset input of an exter- nal phy. the polarity of phy_rst is determined by the phy_rst_pol bit in cmd3 (rst_pol in csr116). the phy_rst pin will assert at the start of the read of the serial eeprom and will deassert at least 240s (the duration of the read of two bytes from the ee- prom) before the end of the serial eeprom read, providing time for the phy to recover from the reset. the phy_rst_pol bit may be programmed from the serial eeprom. the default value is zero, correspond- ing to an active high phy_rst signal. if an active low phy_rst is required, the cmd3 register should be the first register programmed from the serial eeprom. the duration of the assertion of phy_rst depends on the number of registers programmed by the serial eeprom. each register requires at least 240 s. the time to program the cmd3 register and any registers programmed before cmd3 should be ignored in the calculation of phy_rst duration if the phy_rst_pol bit is programmed to 1. if the number of registers programmed from the serial eeprom results in phy_rst being too short, the read-only register at offset 0x28 may be used for pad- ding. specify the address as 0x14 with arbitrary data and repeat as many times as necessary to achieve the required phy_rst duration. if the serial eeprom is not used, the phy may be reset by bios or driver software by programming the correct phy_rst_pol value, disabling the internal port manager by setting the dispm bit, disabling the auto-poll logic by clearing the apep bit and then set- ting the reset_phy bit. all these bits are in the cmd3 register. the phy_rst will be asserted as long as reset_phy remains set. if the phy requires a recov- ery time after reset, the software must provide the delay after clearing the reset_phy bit before access- ing the phy ? s registers or enabling the am79c976 con- troller's port manager and/or auto-poll logic. 106 am79c976 8/01/00 preliminary software access 0 the am79c976 controller implements the 256-byte configuration space as defined by the pci specification revision 2.1. the 64-byte header includes all registers required to identify the am79c976 controller and its function. additionally, the optional pci power manage- ment interface registers are implemented at location 44h - 4bh. the layout of the am79c976 pci configura- tion space is shown in table 20. the pci configuration registers are accessible only by configuration cycles. all multi-byte numeric fields follow little endian byte ordering. all write accesses to re- served locations have no effect; reads from these loca- tions will return a data value of 0. ( the am79c976 controller requires 4k bytes of memory address space for access to all the various internal reg- isters as well as access to some setup information stored in an external serial eeprom. for compatibility with previous pcnet family devices, the lower 32 bytes of the register space are also mapped into i/o space, but some functions of the am79c976 controller (such as network statistics) are only available in memory space. the am79c976 controller supports mapping the ad- dress space to both i/o and memory space. the value in the pci i/o base address register determines the start address of the i/o address space. the register is typically programmed by the pci configuration utility after system power-up. the pci configuration utility must also set the ioen bit in the pci command register to enable i/o accesses to the am79c976 controller. for memory mapped i/o access, the pci memory mapped i/o base address register controls the start table 20. pci configuration space layout 31 24 23 16 15 8 7 0 offset device id vendor id 00h status command 04h base-class sub-class programming if revision id 08h reserved header type latency timer cache line size 0ch i/o base address 10h memory-mapped i/o base address 14h reserved 18h reserved 1ch reserved 20h reserved 24h reserved 28h subsystem id subsystem vendor id 2ch expansion rom base address 30h reserved cap-ptr 34h reserved 38h max_lat min_gnt interrupt pin interrupt line 3ch reserved 40h pmc nxt_itm_ptr cap_id 44h data_reg pmcsr_bse pmcsr 48h reserved . . reserved fch 8/01/00 am79c976 107 preliminary address of the memory space. the memen bit in the pci command register must also be set to enable the mode. both base address registers can be active at the same time. the am79c976 controller requires that the memory space that it claims must be within the 32-bit address space. the am79c976 controller supports two modes for ac- cessing the i/o resources. for backwards compatibility with amd ? s 16-bit ethernet controllers, word i/o is the default mode after power up. the device can be config- ured to dword i/o mode by software. */ the am79c976 controller registers are divided into three groups: memory-mapped registers, control and status registers (csrs), and bus control registers (bcrs). the csrs and bcrs are included in the am79c976 device for software compatibility with older pcnet family controllers that do not have the memory- mapped register group. the csrs and bcrs are ad- dressed indirectly through the register address port (rap), register data port (rdp), and bcr data port (bdp) so that a large number of functions can be con- trolled through a small amount of i/o space. all csr and bcr functions can be accessed more ef- ficiently through the memory-mapped registers. the memory-mapped registers are directly addressed as offsets from the address stored in the memory mapped i/o base address register, which is located in pci configuration space. the control and status registers (csr) are used to configure the ethernet mac engine and to obtain sta- tus information. the bus control registers (bcr) are used to configure the bus interface unit and the leds. both sets of registers are accessed using indirect ad- dressing. the csr and bcr share a common register address port (rap). there are, however, separate data ports. the register data port (rdp) is used to access a csr. the bcr data port (bdp) is used to access a bcr. in order to access a particular csr location, the rap should first be written with the appropriate csr ad- dress. the rdp will then point to the selected csr. a read of the rdp will yield the selected csr data. a write to the rdp will write to the selected csr. in order to access a particular bcr location, the rap should first be written with the appropriate bcr address. the bdp will then point to the selected bcr. a read of the bdp will yield the selected bcr data. a write to the bdp will write to the selected bcr. once the rap has been written with a value, the rap value remains unchanged until another rap write oc- curs, or until an h_reset or s_reset occurs. rap is cleared to all 0s when an h_reset or s_reset oc- curs. rap is unaffected by setting the stop bit. " $ software written for early pcnet family products ex- pects the 48-bit ieee mac address to be found in a small external prom that occupies the first 16 bytes of the controller ? s i/o address space. the software copies this address from the prom into the initialization block in host memory. for compatibility with this software the am79c976 controller contains 16-bytes of read/write memory starting at offset 0 in the device ? s i/o or mem- ory address space. this 16 bytes of space is known as the address prom space (aprom). if compatibility with this software is required, the eeprom should load the data shown in table 21 into the address prom space. the order of bytes in the mac address is such that the first byte transmitted is located at offset 0. cpu access to the aprom space is controlled by the aprom write enable (apromwe) bit (bcr2, bit 8). if this bit is cleared to 0, the host cpu can not write to the aprom space. however, the aprom space can be loaded from the eeprom regardless of the state of apromwe. a read of the reset register creates an internal soft- ware reset (s_reset) pulse in the am79c976 control- ler. the effect of this reset is the same as that of setting the stop bit, except that s_reset clears some bits that are not affected by setting stop. this register exists for backward compatibility with ear- lier pcnet family devices. it should not be used in new software. the ne2100 lance-based family of ethernet cards requires that a write access to the reset register fol- lows each read access to the reset register. the am79c976 controller does not have a similar require- ment. the write access is not required and does not have any effect. table 21. address prom space contents offset contents 00h-05h mac address 06h-0bh 00 00 00 00 00 00h 0ch-0dh check sum of bytes 0-11 and bytes 14-15 0eh-0fh ascii ? w ? (57h) 108 am79c976 8/01/00 preliminary */ " after h_reset, the am79c976 controller is pro- grammed to operate in word i/o mode. dwio (bcr18, bit 7) will be cleared to 0. table 22 shows how the 32 bytes of address space are used in word i/o mode. all i/o resources must be accessed in word quantities and on word addresses. the address prom locations can also be read in byte quantities. the only allowed dword operation is a write access to the rdp, which switches the device to dword i/o mode. a read access other than those listed in table 22 will yield undefined data, and a write operation may cause unexpected re- programming of the am79c976 control registers. table 23 shows legal i/o accesses in word i/o mode. note: * the offset of a mib counter is the value con- tained in the mib offset register plus the offset shown in table 7 or table 8. # */ " the am79c976 controller can be configured to operate in dword (32-bit) i/o mode. the software can invoke the dwio mode by performing a dword write access to the i/o location at offset 10h (rdp). the data of the write access must be such that it does not affect the in- tended operation of the am79c976 controller. setting the device into 32-bit i/o mode is usually the first oper- ation after h_reset or s_reset. the rap register will point to csr0 at that time. writing a value of 0 to csr0 is a safe operation. dwio (bcr18, bit 7) will be set to 1 as an indication that the am79c976 controller operates in 32-bit i/o mode. note: even though the i/o resource mapping changes when the i/o mode setting changes, the rdp location offset is the same for both modes. once the dwio bit has been set to 1, only h_reset can clear it to 0. the dwio mode setting is unaffected by s_reset or set- ting of the stop bit. table 24 shows how the 32 bytes of address space are used in dword i/o mode. all i/o resources must be accessed in dword quanti- ties and on dword addresses. a read access other than listed in table 25 will yield undefined data, and a write operation may cause unexpected reprogramming of the am79c976 control registers. dwio mode applies to both i/o- and memory-mapped accesses. either a 32-bit i/o write to offset 10h relative to the contents of the i/o base address register (bar) or a 32-bit memory write to offset 10h relative to the contents of the memory bar puts the device into dwio mode. once in dwio mode, the offsets of the rap, reset, and bdp registers are 14h, 18h, and 1ch relative to the contents of either the i/o bar or the memory bar. for example, in dwio mode the bdp register can be read either by an i/o read from offset 1ch relative to the contents of the i/o bar or by a memory read from off- set 1ch relative to the contents of the memory bar. dwio mode affects only the locations between 0 and 1fh, which include the rap, reset, and bdp registers. registers at offset 20h and above are directly ac- cessed in memory space by byte address and are un- affected by dwio. the dwio bit is also located at bit 28 of the cmd2 reg- ister and can be set or cleared by software regardless of its current setting. table 22. i/o map in word i/o mode (dwio = 0) offset no. of bytes register 00h - 0fh 16 aprom 10h 2 rdp 12h 2 rap (shared by rdp and bdp) 14h 2 reset register 16h 2 bdp 18h - 1fh 8 reserved 20h-1ffh 224 memory-mapped registers * 256 mib counters 8/01/00 am79c976 109 preliminary table 23. legal i/o accesses in word i/o mode (dwio = 0) ad[4:0] be [3:0] type comment 0xx00 1110 rd byte read of aprom location 0h, 4h, 8h or ch 0xx01 1101 rd byte read of aprom location 1h, 5h, 9h or dh 0xx10 1011 rd byte read of aprom location 2h, 6h, ah or eh 0xx11 0111 rd byte read of aprom location 3h, 7h, bh or fh 0xx00 1100 rd word read of aprom locations 1h (msb) and 0h (lsb), 5h and 4h, 8h and 9h or ch and dh 0xx10 0011 rd word read of aprom locations 3h (msb) and 2h (lsb), 7h and 6h, bh and ah or fh and eh 10000 1100 rd word read of rdp 10010 0011 rd word read of rap 10100 1100 rd word read of reset register 10110 0011 rd word read of bdp 0xx00 1100 wr word write to aprom locations 1h (msb) and 0h (lsb), 5h and 4h, 8h and 9h or ch and dh 0xx10 0011 wr word write to aprom locations 3h (msb) and 2h (lsb), 7h and 6h, bh and ah or fh and eh 10000 1100 wr word write to rdp 10010 0011 wr word write to rap 10100 1100 wr word write to reset register 10110 0011 wr word write to bdp 10000 0000 wr dword write to rdp, switches device to dword i/o mode table 24. i/o map in dword i/o mode (dwio = 1) offset no. of bytes register 00h - 0fh 16 aprom 10h 4 rdp 14h 4 rap (shared by rdp and bdp) 18h 4 reset register 1ch 4 bdp 20h-1ffh 224 memory-mapped registers 200h-2ffh 256 mib counters table 25. legal i/o accesses in double word i/o mode (dwio =1) ad[4:0] % [3:0] type comment 0xx00 0000 rd dword read of aprom locations 3h (msb) to 0h (lsb), 7h to 4h, bh to 8h or fh to ch 0xx00 0000 wr dword write to aprom locations 3h (msb) to 0h (lsb), 7h to 4h, bh to 8h or fh to ch 10000 0000 wr dword write to rdp 10100 0000 wr dword write to rap 11000 0000 wr dword write to reset register 10000 0000 rd dword read of rdp 110 am79c976 8/01/00 preliminary 10100 0000 rd dword read of rap 11000 0000 rd dword read of reset register table 25. legal i/o accesses in double word i/o mode (dwio =1) 8/01/00 am79c976 111 preliminary user accessible registers the am79c976 controller has four types of user regis- ters: the pci configuration registers, the memory- mapped registers, the control and status registers (csrs), and the bus control registers (bcrs). the csrs and bcrs are included for software compatibility with older pcnet family devices. however, all csr and bcr functions can be accessed more efficiently through the memory-mapped registers. software writ- ten for the am79c976 device and future pcnet family devices does not have to access any csr or bcr. the am79c976 controller implements all pcnet-isa (am79c960) registers, all c-lance (am79c90) regis- ters, all pcnet-fast (am79c971) registers, plus a number of additional registers. the am79c976 csrs are compatible upon power up with both the pcnet-isa csrs and all of the c-lance csrs. the pci configuration registers and the memory- mapped registers can be accessed in any data width. the csrs and bcrs must be accessed according to the i/o mode that is currently selected. when wio mode is selected, all csr and bcr locations are de- fined to be 16 bits in width. when dwio mode is se- lected, all these register locations are defined to be 32 bits in width, with the upper 16 bits of most register lo- cations marked as reserved locations with undefined values. when performing register write operations in dwio mode, the upper 16 bits should always be written as zeros. when performing register read operations in dwio mode, the upper 16 bits of i/o resources should always be regarded as having undefined values, ex- cept for csr88. the am79c976 controller ? s registers can be divided into several functional groups: pci configuration alias registers, pci configuration registers, setup registers, running registers, and test registers. the pci configuration alias registers are typically pro- grammed through the eeprom read operation. in this way, they are initialized before the bios accesses the pci configuration registers. this group includes the max_lat_a, min_gnt_a, pcidata0 - 7, pmc_a, sid_a, svid_a and vid_a registers and the rom_cfg register. the pci configuration registers are accessed by the system bios software to configure the am79c976 controller. these registers include the memory base address register, the expansion rom base address register, the interrupt line register, the pci command register, the pci status register and the pmc register. typically, device information will also be read from the sid, svid and vid registers. the setup registers include most of the remaining memory mapped registers. the programming of these is typically divided between the eeprom and the driver software. many of these registers are optional and need not be initialized unless the associated func- tion is used. typically, the sram_size, sram_bnd and padr registers are initialized from the eeprom. the driver initializes the badr, badx, rcv_ring_len, xmt_ring_len and ladrf registers. the cmd2, cmd3, ctrl0, ctrl1 and ctrl2 registers are typi- cally partially initialized from the eeprom and partially by the driver. the cmd7 and ctrl3 registers are ini- tialized by the driver. the driver reads the mib_offset and chipid registers at initialization time. the phy_access register may be used at this time to initialize the external phy. running registers are accessed by the driver software. these include the cmd0, int0, inten0, stat0, ladrf and mib registers. the driver may access other registers during operation depending on the features being used. pci configuration registers 0=* offset 00h the pci vendor id register is a 16-bit register that iden- tifies the manufacturer of the am79c976 controller. amd ? s vendor id is 1022h. note that this vendor id is not the same as the manufacturer id in csr88 and csr89. the vendor id is assigned by the pci special interest group. the pci vendor id register is read only. this register is the same as bcr35, which can be writ- ten by the eeprom. 0* (* offset 02h the pci device id register is a 16-bit register that uniquely identifies the am79c976 controller within amd's product line. the am79c976 device id is 2000h. note that this device id is not the same as the part number in csr88 and csr89. the device id is assigned by amd. the device id is the same as the pcnet-pci ii (am79c970a) and pcnet- fast (am79c971) devices. the pci device id register is read only. 0!! offset 04h the pci command register is a 16-bit register used to control the gross functionality of the am79c976 con- troller. it controls the am79c976 controller's ability to generate and respond to pci bus cycles. to logically disconnect the am79c976 device from all pci bus cy- cles except configuration cycles, a value of 0 should be written to this register. 112 am79c976 8/01/00 preliminary the pci command register is read and written by the host. bit name description 15-10 res reserved locations. read as ze- ros; write operations have no ef- fect. 9 fbtben fast back-to-back enable. when this bit is set to 1, the am79c976 controller will generate fast back-to-back cycles. when this bit is cleared to 0, the am79c976 controller will not generate fast back-to-back cycles. fbtben is cleared by h_reset and is not effected by s_reset or by setting the stop bit. 8 serren serr enable. controls the as- sertion of the serr pin. serr is disabled when serren is cleared. serr will be asserted on detection of an address parity error and if both serren and perren (bit 6 of this register) are set. serren is cleared by h_reset and is not effected by s_reset or by setting the stop bit. 7 res reserved location. read as ze- ros; write operations have no ef- fect. 6 perren parity error response enable. enables the parity error response functions. when perren is 0 and the am79c976 controller de- tects a parity error, it only sets the detected parity error bit in the pci status register. when per- ren is 1, the am79c976 control- ler asserts perr on the detection of a data parity error. it also sets the dataperr bit (pci status register, bit 8), when the data parity error occurred during a master cycle. perren also enables reporting address parity errors through the serr pin and the serr bit in the pci status register. perren is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 5 vgasnoop vga palette snoop. read as ze- ro; write operations have no ef- fect. 4 mwien memory write and invalidate cy- cle enable. when this bit is set to 1, the am79c976 controller will generate memory write and in- validate (mwi) cycles when ap- propriate. when the bit is cleared to 0, the device will generate memory write cycles instead of mwi cycles. mwien is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 3 scycen special cycle enable. read as zero; write operations have no ef- fect. the am79c976 controller ignores all special cycle opera- tions. 2 bmen bus master enable. setting bmen enables the am79c976 controller to become a bus mas- ter on the pci bus. the host must set bmen before setting the init or strt bit in csr0 of the am79c976 controller. bmen is cleared by h_reset and is not effected by s_reset or by setting the stop bit. 1 memen memory space access enable. the am79c976 controller will ig- nore all memory accesses when memen is cleared. the host must set memen before the first memory access to the device. for memory mapped i/o, the host must program the pci mem- ory mapped i/o base address register with a valid memory ad- dress before setting memen. for accesses to the expansion rom, the host must program the pci expansion rom base ad- dress register at offset 30h with a valid memory address before set- 8/01/00 am79c976 113 preliminary ting memen. the am79c976 controller will only respond to ac- cesses to the expansion rom when both romen (pci expan- sion rom base address register, bit 0) and memen are set to 1. since memen also enables the memory mapped access to the am79c976 i/o resources, the pci memory mapped i/o base address register must be pro- grammed with an address so that the device does not claim cycles not intended for it. memen is cleared by h_reset and is not effected by s_reset or by setting the stop bit. 0 ioen i/o space access enable. the am79c976 controller will ignore all i/o accesses when ioen is cleared. the host must set ioen before the first i/o access to the device. the pci i/o base ad- dress register must be pro- grammed with a valid i/o address before setting ioen. ioen is cleared by h_reset and is not effected by s_reset or by setting the stop bit. 0 offset 06h the pci status register is a 16-bit register that contains status information for the pci bus related events. bit name description 15 perr parity error. perr is set when the am79c976 controller detects a parity error. the am79c976 controller sam- ples the ad[31:0], c/be [3:0], and the par lines for a parity error at the following times: in slave mode, during the ad- dress phase of any pci bus com- mand. in slave mode, for all i/o, mem- ory and configuration write com- mands that select the am79c976 controller when data is trans- ferred (trdy and irdy are as- serted). in master mode, during the data phase of all memory read com- mands. in master mode, during the data phase of the memory write com- mand, the am79c976 controller sets the perr bit if the target re- ports a data parity error by as- serting the perr signal. perr is not effected by the state of the parity error response en- able bit (pci command register, bit 6). perr is set by the am79c976 controller and cleared by writing a 1. writing a 0 has no effect. perr is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 14 serr signaled serr. serr is set when the am79c976 controller detects an address parity error and both serren and perren (pci command register, bits 8 and 6) are set. serr is set by the am79c976 controller and cleared by writing a 1. writing a 0 has no effect. serr is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 13 rmabort received master abort. rm- abort is set when the am79c976 controller terminates a master cycle with a master abort sequence. rmabort is set by the am79c976 controller and cleared by writing a 1. writing a 0 has no effect. rmabort is cleared by h_reset and is not affected by s_reset or by set- ting the stop bit. 12 rtabort received target abort. rt- abort is set when a target ter- minates an am79c976 master cycle with a target abort se- quence. rtabort is set by the am79c976 controller and 114 am79c976 8/01/00 preliminary cleared by writing a 1. writing a 0 has no effect. rtabort is cleared by h_reset and is not affected by s_reset or by set- ting the stop bit. 11 stabort send target abort. read as ze- ro; write operations have no ef- fect. the am79c976 controller will never terminate a slave ac- cess with a target abort se- quence. stabort is read only. 10-9 devsel device select timing. devsel is set to 01b (medium), which means that the am79c976 con- troller will assert devsel two clock periods after frame is as- serted. devsel is read only. 8 dataperr data parity error detected. dataperr is set when the am79c976 controller is the cur- rent bus master and it detects a data parity error and the parity error response enable bit (pci command register, bit 6) is set. during the data phase of all memory read commands, the am79c976 controller checks for parity error by sampling the ad[31:0] and c/be [3:0] and the par lines. during the data phase of all memory write commands, the am79c976 controller checks the perr input to detect whether the target has reported a parity error. dataperr is set by the am79c976 controller and cleared by writing a 1. writing a 0 has no effect. dataperr is cleared by h_reset and is not affected by s_reset or by set- ting the stop bit. 7 fbtbc fast back-to-back capable. read as one; write operations have no effect. the am79c976 controller is capable of accepting fast back-to-back transactions with the first transaction address- ing a different target. 6-5 res reserved locations. read as zero; write operations have no ef- fect. 4 new_cap new capabilities. this bit indi- cates whether this function imple- ments a list of extended capabilities such as pci power management. when set, this bit indicates the presence of new capabilities. a value of 0 means that this function does not imple- ment new capabilities. read as one; write operations have no effect. the am79c976 controller supports the linked additional capabilities list. 3-0 res reserved locations. read as zero; write operations have no ef- fect. 0 * offset 08h the pci revision id register is an 8-bit register that specifies the am79c976 controller revision number. the value of this register is 5xh with the lower four bits being silicon-revision dependent. the pci revision id register is read only. 00 !! ( offset 09h the pci programming interface register is an 8-bit reg- ister that identifies the programming interface of am79c976 controller. pci does not define any specific register-level programming interfaces for network devic- es. the value of this register is 00h. the pci programming interface register is read only. 05- offset 0ah the pci sub-class register is an 8-bit register that iden- tifies specifically the function of the am79c976 control- ler. the value of this register is 00h which identifies the am79c976 device as an ethernet controller. the pci sub-class register is read only. 0 - offset 0bh the pci base-class register is an 8-bit register that broadly classifies the function of the am79c976 con- troller. the value of this register is 02h which classifies the am79c976 device as a network controller. the pci base-class register is read only. 8/01/00 am79c976 115 preliminary 0(+< 6 offset 0ch this register indicates the system cache line size in units of 32-bit double words. this quantity is used to determine when to use the advanced pci bus com- mands (mwi, mrl, and mrm). it is also used for align- ing pci burst transfers to cache line boundaries. only the values 4, 8, and 16 are acceptable. if the host cpu attempts to write any other value to this location, the contents of the register will be set to 0. this register is cleared by h_reset and is not effected by s_reset or by setting the stop bit. 0<($ ! offset 0dh the pci latency timer register is an 8-bit register that specifies the minimum guaranteed time the am79c976 controller will control the bus once it starts its bus mas- tership period. the time is measured in clock cycles. every time the am79c976 controller asserts frame at the beginning of a bus mastership period, it will copy the value of the pci latency timer register into a counter and start counting down. the counter will freeze at 0. when the system arbiter removes gnt while the counter is non-zero, the am79c976 controller will con- tinue with its data transfers. it will only release the bus when the counter has reached 0. the pci latency timer is only significant in burst trans- actions, where frame stays asserted until the last data phase. in a non-burst transaction, frame is only as- serted during the address phase. the internal latency counter will be cleared and suspended while frame is deasserted. the six most significant bits of the pci latency timer register are programmable. the two least significant bits are fixed at 0. the host should read the am79c976 pci min_gnt and pci max_lat registers to determine the latency requirements for the device and then initialize the latency timer register with an appropriate value. the pci latency timer register is read and written by the host. the pci latency timer register is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 0. $' offset 0eh the pci header type register is an 8-bit register that describes the format of the pci configuration space locations 10h to 3ch and that identifies a device to be single or multi-function. the pci header type register is located at address 0eh in the pci configuration space. it is read only. bit name description 7 funct single-function/multi-function de- vice. read as zero; write opera- tions have no effect. the am79c976 controller is a single function device. 6-0 layout pci configuration space layout. read as zeros; write operations have no effect. the layout of the pci configuration space loca- tions 10h to 3ch is as shown in the table at the beginning of this section. 0 offset 10h the pci i/o base address register is a 32-bit register that determines the location of the am79c976 i/o re- sources in all of i/o space. bit name description 31-5 iobase i/o base address most significant 27 bits. these bits are written by the host to specify the location of the am79c976 i/o resources in all of i/o space. iobase must be written with a valid address be- fore the am79c976 controller slave i/o mode is turned on by setting the ioen bit (pci com- mand register, bit 0). when the am79c976 controller is enabled for i/o mode (ioen is set), it monitors the pci bus for a valid i/o command. if the value on ad[31:5] during the address phase of the cycles matches the value of iobase, the am79c976 controller will drive devsel indi- cating it will respond to the access. iobase is read and written by the host. iobase is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 4-2 iosize i/o size requirements. read as zeros; write operations have no effect. iosize indicates the size of the i/o space the am79c976 control- 116 am79c976 8/01/00 preliminary ler requires. when the host writes a value of ffff ffffh to the i/o base address register, it will read back a value of 0 in bits 4-2. that indicates an am79c976 i/o space requirement of 32 bytes. 1 res reserved location. read as zero; write operations have no effect. 0 iospace i/o space indicator. read as one; write operations have no effect. indicating that this base address register describes an i/o base address. 0#!$#'' offset 14h the pci memory mapped i/o base address register is a 32-bit register that determines the location of the am79c976 i/o resources. memory space claimed by the am79c976 device may be mapped anywhere in 32- bit memory space. bit name description 31-12 membase memory mapped i/o base ad- dress, bits 31-12. these bits are written by the host to specify the location of the am79c976 i/o re- sources in 32-bit memory space. membase must be written with a valid address before the am79c976 controller slave memory mapped i/o mode is turned on by setting the memen bit (pci command register, bit 1). when the am79c976 controller is enabled for memory mapped i/o mode (memen is set), it mon- itors the pci bus for a valid mem- ory command. if the value on ad[31:12] during the address phase of the cycles matches the value of membase, the am79c976 controller will drive devse l indicating it will respond to the access. membase is read and written by the host. membase is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 11-4 memsize memory mapped i/o size re- quirements. read as zeros; write operations have no effect. memsize indicates the size of the memory space the am79c976 controller requires. when the host writes a value of ffff ffffh to the memory mapped i/o base address regis- ter, it will read back 0s in bit 11:4 to indicate an am79c976 memo- ry space requirement of 4k bytes. 3 prefetch prefetchable. the value of this read-only bit is the inverse of the value of the disable prefetchabil- ity (prefetch_dis) bit (cmd3, bit 30). prefetch_dis is nor- mally loaded from eeprom. set- ting prefetch to 1 indicates that the memory space claimed by this device can be prefetched. because of the side effects of reading the reset register at off- set 14h or 18h (depending on the state of dwio (cmd2, bit 28)), locations at offsets less than 20h cannot be prefetched. the am79c976 device will discon- nect any attempted burst transfer at offsets less than 20h. this bit is read-only. (however, its value is the inverse of prefetch_dis, which can be loaded from eeprom.) 2-1 type memory type indicator. read as zeros; write operations have no effect. indicates that this base ad- dress register is 32 bits wide and mapping can be done anywhere in the 32-bit memory space. 0 memspacememory space indicator. read as zero; write operations have no effect. indicates that this base ad- dress register describes a memo- ry base address. 05 $ !=* offset 2ch the pci subsystem vendor id register is a 16-bit reg- ister that together with the pci subsystem id uniquely identifies the add-in card or subsystem the am79c976 controller is used in. subsystem vendor ids can be ob- tained from the pci sig. a value of 0 (the default) indi- cates that the am79c976 controller does not support subsystem identification. the pci subsystem vendor 8/01/00 am79c976 117 preliminary id is an alias of bcr23, bits 15-0. it is programmable through the eeprom. the pci subsystem vendor id register is read only. 05 $ !* offset 2eh the pci subsystem id register is a 16-bit register that together with the pci subsystem vendor id uniquely identifies the add-in card or subsystem the am79c976 controller is used in. the value of the subsystem id is up to the system vendor. a value of 0 (the default) indi- cates that the am79c976 controller does not support subsystem identification. the pci subsystem id is an alias of bcr24, bits 15-0. it is programmable through the eeprom. the pci subsystem id register is read only. 0%&' # offset 30h the pci expansion rom base address register is a 32-bit register that defines the base address, size and address alignment of an expansion rom. the host cpu can determine the size and alignment require- ments of the rom by writing all 1s to this register, read- ing back the result, and masking out the least significant bit. the device will return 0s in all don ? t care bits. the am79c976 device supports roms ranging in size from 2 kbytes to 16 mbytes. the amount of address space claimed by the rom can be programmed through the rom configuration register, which can be loaded from the external serial eeprom. the bits of the rom configuration register (rom_cfg) act as write enable bits for bits [23:11] and bit 0 of this register. see figure 4646. as an example, assume that rom_cfg is pro- grammed to 0f001h. this means that bits [23:20] and bit 0 of rombase are write enabled, and bits [19:11] are fixed at 0. in addition, bits [31:24] of rombase are always write enabled, and bits [10:1] are always 0, re- gardless of the contents of rom_cfg. therefore, when the host cpu writes all 1s to rombase, it will read back 0fff00001h. masking out bit 0 leaves 0fff00000h. this means that bits [19:0] of the base address are don ? t cares, and the rom occupies 2 20 or 1 mbytes of address space, and must be mapped to a 1 mbyte boundary. if the cpu then writes 00300001h to this register and sets the memen bit (pci command register, bit 1) to enable memory accesses, the rom will claim the memory space between 00300000h and 003fffffh. ",0%&' # note: the procedure described in the pci expansion rom base address register section specifies the amount of address space that the rom claims. the rom may be smaller than the amount of address space claimed. the actual size of the code in the ex- pansion rom is always determined by reading the ex- pansion rom header. . : , : c : . . a , , a "1 e "%&3 118 am79c976 8/01/00 preliminary bit name description 31-24 rombase expansion rom base address most significant 8 bits. these bits are written by the host to specify the location of the expansion rom in pci memory space. rombase must be written with a valid address before the am79c976 expansion rom ac- cess is enabled by setting romen (pci expansion rom base address register, bit 0) and memen (pci command register, bit 1). when the am79c976 controller is enabled for expansion rom access (romen and memen are set to 1), it monitors the pci bus for a valid memory com- mand. if the value on ad[31:2] during the address phase of the cycle falls in the address space specified by the contents of this register, the am79c976 control- ler will drive devsel indicating it will respond to the access. rombase is read and written by the host. rombase is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 23-11 romsize expansion rom base address bits [23:11]. those bits in this field that are enabled by the cor- responding bits in the rom con- figuration register (rom_cfg) are written by the host cpu to specify the location of the expan- sion rom in pci memory space. those bits in this field that are not enabled by the corresponding bits in rom_cfg are fixed at 0. 10-1 zeros read as zeros; write operation has no effect. 0 romen expansion rom enable. written by the host to enable access to the expansion rom. the am79c976 controller will only re- spond to accesses to the expan- sion rom when both romen and memen (pci command reg- ister, bit 1) are set to 1. this bit can be set to 1 only when bit 0 of rom_cfg is set to 1. when bit 0 of rom_cfg is cleared to 0, romen is fixed a 0, and the ex- pansion rom cannot be mapped into pci memory space. romen is read and written by the host. romen is cleared by h_reset and is not effected by s_reset or by setting the stop bit. 0'5 0 offset 34h bit name description 7-0 cap_ptr the pci capabilities pointer register is a read-only 8-bit reg- ister that points to a linked list of capabilities implemented on this device. this register has the val- ue 44h. the pci capabilities register is read only. 0'< offset 3ch the pci interrupt line register is an 8-bit register that is used to communicate the routing of the interrupt. this register is written by the post software as it ini- tializes the am79c976 controller in the system. the register is read by the network driver to determine the interrupt channel which the post software has as- signed to the am79c976 controller. the pci interrupt line register is not modified by the am79c976 control- ler. it has no effect on the operation of the device. the pci interrupt line register is read and written by the host. it is cleared by h_reset and is not affected by s_reset or by setting the stop bit. 0'0 offset 3dh this pci interrupt pin register is an 8-bit register that indicates the interrupt pin that the am79c976 controller is using. the value for the am79c976 interrupt pin reg- ister is 01h, which corresponds to inta . the pci interrupt pin register is read only. 0# @9 offset 3eh the pci min_gnt register is an 8-bit register that specifies the minimum length of a burst period that the am79c976 device needs to keep up with the network activity. the length of the burst period is calculated as- suming a clock rate of 33 mhz. the register value spec- ifies the time in units of 1/4 s. the pci min_gnt register is an alias of the minimum grant shadow reg- 8/01/00 am79c976 119 preliminary ister, which can be loaded from the serial eeprom. it is recommended that the shadow register be pro- grammed to a value of 18h, which corresponds to 6 s. the host should use the value in this register to deter- mine the setting of the pci latency timer register. the pci min_gnt register is read only. 0#a@< offset 3fh the pci max_lat register is an 8-bit register that spec- ifies the maximum arbitration latency the am79c976 controller can sustain without causing problems to the network activity. the register value specifies the time in units of 1/4 s. the max_lat register is an alias of the maximum latency shadow register, which can be load- ed from the serial eeprom. it is recommended that the shadow register be programmed to a value of 18h, which corresponds to 6 s. the host should use the value in this register to deter- mine the setting of the pci latency timer register. the pci max_lat register is read only 0'5 $ offset 44h bit name description 7-0 cap_id this register identifies the linked list item as being the pci power management registers. this is a read-only register whose value is fixed at 1h. 0 &!0 offset 45h bit name description 7-0 nxt_itm_ptr the next item pointer register points to the starting address of the next capability. the pointer at this offset is a null pointer, indi- cating that this is the last capabil- ity in the linked list of the capabilities. this is a read-only register whose content is fixed at 0. 008# !'5 :0#; offset 46h note: all bits of this register are loaded from eeprom. the register is aliased to bcr36 for testing purposes. bit name description 15-11 pme_spt pme support. this 5-bit field indi- cates the power states in which the function may assert pme . a value of 0b for any bit indicates that the function is not capable of asserting the pme signal while in that power state. bit(11) xxxx1b - pme can be asserted from d0. bit(12) xxx1xb - pme can be asserted from d1. bit(13) xx1xxb - pme can be asserted from d2. bit(14) x1xxxb - pme can be asserted from d3hot. bit(15) 1xxxxb - pme can be asserted from d3cold. the value read from bit(15) is the and of the value of bcr36, bit 15 and the current state of the vaux_sense pin. read only. 10 d2_spt d2 support. if this bit is a 1, this function supports the d2 power management state. read only. 9 d1_spt d1 support. if this bit is a 1, this function supports the d1 power management state. read only. 8-6 res reserved locations. written and read as zeros. 5 dsi device specific initialization. when this bit is 1, it indicates that special initialization of the func- tion is required (beyond the stan- dard pci configuration header) before the generic class device driver is able to use it. read only. 4 res reserved location. written and read as zero. 120 am79c976 8/01/00 preliminary 3 pme_clk pme clock. when this bit is a 1, it indicates that the function relies on the presence of the pci clock for pme operation. when this bit is a 0 it indicates that no pci clock is required for the function to generate pme . functions that do not support pme generation in any state must return 0 for this field. read only. 2-0 pmis_ver power management interface specification version. a value of 010b indicates that this function complies with the revision 1.1 of the pci power management in- terface specification. 008# ! :0#; offset 48h bit name description 15 pme_status pme status. this bit is set when the function would normally as- sert the pme signal independent of the state of the pme_en bit. writing a 1 to this bit will clear it and cause the function to stop as- serting a pme (if enabled). writ- ing a 0 has no effect. if the function supports pme from d3cold then this bit is sticky and must be explicitly cleared by the operating system each time the operating system is initially load- ed. read/write accessible. sticky bit. this bit is reset by por. s_reset or setting the stop bit has no effect. if the function does not support pme# assertion from d3cold, either because bit 15 of the pmc alias register is zero or the vaux_sense pin is low, pme_status will be reset fol- lowing h_reset. this reset is actually done at the end of the eeprom read operation, since bit 15 of the pmc alias register may be loaded from the ee- prom. 14-13 data_scale data scale. this two bit read- only field indicates the scaling factor to be used when interpret- ing the value of the data register. the value and meaning of this field will vary depending on the data_scale field. read only. 12-9 data_sel data select. this optional four-bit field is used to select which data is reported through the data reg- ister and data_scale field. read/write accessible. sticky bit. this bit is reset by por. h_reset, s_reset, or setting the stop bit has no effect. 8 pme_en pme enable. when a 1, pme_en enables the function to assert pme . when a 0, pme as- sertion is disabled. this bit defaults to ? 0 ? if the func- tion does not support pme gener- ation from d3cold. if the function supports pme from d3cold, then this bit is sticky and must be explicitly cleared by the operating system each time the operating system is initially load- ed. read/write accessible. sticky bit. this bit is reset by por. s_reset or setting the stop bit has no effect. if the function does not support pme assertion from d3cold, either because bit 15 of the pmc alias register is zero or the vaux_sense pin is low, pme_status will be reset fol- lowing h_reset. this reset is actually done at the end of the eeprom read operation, since bit 15 of the pmc alias register may be loaded from the eeprom. 7-2 res reserved locations. read only. 1-0 pwr_state 8/01/00 am79c976 121 preliminary power state. this 2-bit field is used both to determine the cur- rent power state of a function and to set the function into a new power state. the definition of the field values is as follows: 00b - d0 01b - d1 10b - d2 11b - d3 these bits can be written and read, but their contents have no effect on the operation of the device. read/write accessible. 00# ''%& offset 4ah bit name description 7-0 pmcsr_bse the pci pmcsr bridge support extensions register is an 8-bit register. pmcsr bridge support extensions are not supported. this is a read-only register whose content is 0. 0* offset 4bh note: all bits of this register are loaded from eeprom. the register is aliased to lower bytes of the bcr37-44 for testing purposes. bit name description 7-0 data_reg the pci data register is an 8-bit read-only register that is used as a window into an array of 8 ten-bit pcidata registers. the value read from this register is the 8 least significant bits of the pci- data register selected by data_sel field of the pmcsr (offset 48h in pci configuration space). the two most significant bits of the selected pcidata register are read from the data_scale field of the pmcsr. the interpretation of the contents of this register is described in the pci bus power management in- terface specification , version 1.1. 122 am79c976 8/01/00 preliminary memory-mapped registers the memory-mapped registers give the host cpu ac- cess to all programmable features of the am79c976 device. these registers are mapped directly into pci memory space so that any programmable feature can be accessed with a single pci memory read or write transaction. data in these registers can be accessed as a single byte, a 16-bit word, or a 32-bit double word. in addition, the am79c976 controller ? s memory is prefetchable, which allows burst read and write opera- tions. accesses to consecutive registers or to registers logically wider than double word (badx, badr, padr, etc.) may be treated as a single block move to take ad- vantage of the pci burst. registers that are logically wider than a double word are shown in the register descriptions as a single reg- ister. these may be accessed using multiple smaller accesses or with a single burst access. some registers that are smaller than a double word in width (stval, padr[47:32], xmt_ring_len, rcv_ring_len) are placed in the memory map in the lower half of a double word. the upper half ignores writes and reads back zeros (stval, padr[47:32]) or ones (xmt_ring_len, rcv_ring_len) as appro- priate for sign extension. this allows these registers to be accessed with double word reads and writes. memory-mapped registers can be initialized with data loaded from the serial eeprom. the command and interrupt enable registers (cmd0, cmd2, cmd3, cmd7, and inten0) use a write access technique that in this document is called command style access. command style access allows the host cpu to write to selected bits of a register without alter- ing bits that are not selected. command style registers are divided into 4 bytes that can be written indepen- dently. the high order bit of each byte is the ? value ? bit that specifies the value that will be written to selected bits of the register. the 7 low order bits of each byte make up a bit map that selects which register bits will be altered. if a bit in the bit map is set to 1, the corre- sponding bit in the register will be loaded with the con- tents of the value bit. if a bit in the bit map is cleared to 0, the corresponding bit in the register will not be al- tered. for example, if the value 10011010b is written to the least significant byte of a command style register, bits 1, 3, and 4 of the register will be set to 1, and the other bits will not be altered. if the value 00011010b is written to the same byte, bits 1, 3, and 4 will be cleared to 0, and the other bits will not be altered. in the worst case it takes two write accesses to write to all of the bits in a command style register. one access writes to all bits that should be set to 1, and the other access writes to all bits that should be cleared to 0. the eeprom loading logic bypasses the command style access logic and treats command style registers just like the other writable memory-mapped registers. the value bits are ignored and the contents of the bit map fields are written directly into the corresponding registers. for example, if the eeprom logic loads the value 00011010b into the least significant byte of a com- mand style register, bits 1, 3, and 4 of the register will be set to 1, and bits 0, 2, 5, and 6 will be cleared to 0. in the following register descriptions, the offset listed for each register is the offset relative to the contents of the pci memory-mapped i/o base address register. # offset 28h this read-only register contains the offset of the block of statistics counters. for the am79c976 device the content of this register is fixed at 200h. the contents of the mib offset registers and therefore the locations of statistics counter blocks in other pcnet family devices may be different. therefore, software should calculate the address of a particular mib counter by adding the contents of the memory-mapped i/o base address register plus the contents of this register plus the off- set shown in table 2 on page 33 or table 3 on page 41. 0@=<%4?-0=4 offset 0a8h the contents of this register are cleared to 0 when the rst pin is asserted. the register is not cleared at the start of a serial eeprom read operation or after a se- rial eeprom read error. table 26. ap_value0: auto-poll value0 register 0@=<%?-0= offset 0aah the contents of this register are cleared to 0 when the rst pin is asserted. the register is not cleared at the start of a serial eeprom read operation or after a se- rial eeprom read error. bit name description 15-0 ap_value0 this register contains the results of the automatic polling of the user- selectable external phy register, ap_reg0. 8/01/00 am79c976 123 preliminary table 27. ap_value1: auto-poll value1 register 0@=<% ?-0= offset 0ach the contents of this register are cleared to 0 when the rst pin is asserted. the register is not cleared at the start of a serial eeprom read operation or after a se- rial eeprom read error. table 28. ap_value2: auto-poll value2 register 0@=<% ?-0= offset 0aeh the contents of this register are cleared to 0 when the rst pin is asserted. the register is not cleared at the start of a serial eeprom read operation or after a se- rial eeprom read error. table 29. ap_value3: auto-poll value3 register 0@=<%"?-0=" offset 0b0h the contents of this register are cleared to 0 when the rst pin is asserted. the register is not cleared at the start of a serial eeprom read operation or after a se- rial eeprom read error. table 30. ap_value4: auto-poll value4 register 0@=<%)?-0=) offset 0b2h the contents of this register are cleared to 0 when the rst pin is asserted. the register is not cleared at the start of a serial eeprom read operation or after a se- rial eeprom read error. table 31. ap_value5: auto-poll value5 register 0 <<4?-04 offset 088h this register controls the automatic polling of the status register of the default external phy. all bits in this register are set to their default values by h_reset. all bits are also set to their default values before eeprom data are loaded or after an eeprom read failure. the default value for all bits except for bits 15 (ap_reg0_en) and 12:8 (ap_reg0_addr) is 0. the default value for ap_reg0_en is 1 and the default value for the ap_reg0_addr field is 00001b. when loading the autopoll0 register from the ee- prom, bits [9:5] are also loaded into bcr33 bits [9:5]. this allows operation with legacy drivers that expect the phy address in that location. table 32. autopoll0: auto-poll0 register bit name description 15-0 ap_value 1 this register contains the results of the automatic polling of the user- selectable external phy register, ap_reg1. bit name description 15-0 ap_value2 this register contains the results of the automatic polling of the user- selectable external phy register, ap_reg2. bit name description 15-0 ap_value3 this register contains the results of the automatic polling of the user- selectable external phy register, ap_reg3. bit name description 15-0 ap_value4 this register contains the results of the automatic polling of the user- selectable external phy register, ap_reg4. bit name description 15-0 ap_value5 this register contains the results of the automatic polling of the user- selectable external phy register, ap_reg5. bit name description 15 ap_reg0_en enable bit for autopoll register 0. this bit is read-only and always has the value 1. 14-13 res reserved locations. written as zeros and read as undefined 12-8 ap_reg0_ addr ap_reg0 address. this field is read-only and always has the value 00001. 124 am79c976 8/01/00 preliminary 0 <<?-0 offset 08ah this register controls the automatic polling of a user- selectable external phy register. all bits in this register are set to their default values by h_reset. all bits are also set to their default values before eeprom data are loaded or after an eeprom read failure. the default value for all bits in this register is 0. table 33. autopoll1: auto-poll1 register 7-5 res reserved locations. written as zero and read as undefined. 4-0 ap_phy0_ addr auto-poll phy0 address. this field contains the address of the external phy that contains ap-reg0. the network port manager uses this phy address for auto-negotiation. the autopoll state machine also uses this field as the default phy address when one or more of the ap_phyn_dflt bits are set. bit name description bit name description 15 ap_reg1_en enable bit for autopoll register 1. when this bit and the auto-poll external phy bit (apep) in cmd1 are both set to 1, the auto-poll state machine periodically reads the external phy register selected by the ap_phy1_addr and ap_reg1_addr fields and sets the apint1 interrupt bit if it detects a change in the register ? s contents. 14-13 res reserved locations. written as zeros and read as undefined. 12-8 ap_reg1_addr ap_reg1 address. this field contains the register number of an external phy register that the auto-poll state machine will periodically read if the ap_reg1_en bit in this register and the apep bit (cmd3, bit 24) is set. 7 res reserved location. written as zero and read as undefined. 6 ap_pre_sup1 auto-poll preamble suppression. if this bit is set to 1, the auto-poll state machine will suppress the preambles of the mii management frames that it uses to periodically read the external phy register selected by the ap_phy1_addr and ap_reg1_addr fields. this bit is ignored when the ap_phy1_dflt bit is set. 5 ap_phy1_dflt auto-poll phy1 default. when this bit is set, the auto-poll state machine ignores the contents of the ap_phy1_addr and ap_pre_sup1 fields and uses the ap_phy0_addr field for the address of the phy device to be polled. if this bit is set, the auto-poll state machine will suppress preambles only if the port manager has determined that the default external phy can accept mii management frames without preambles. (the port manager examines bit 6 in register 1 of the default phy to make this determination.) 4-0 ap_phy1_addr auto-poll phy1 address. this field contains the address of the external phy that contains ap_reg1. this bit is ignored when the ap_phy1_dflt bit is set. 8/01/00 am79c976 125 preliminary 0 << ? -0 offset 08ch this register controls the automatic polling of a user- selectable external phy register, ap_reg2. all bits in this register are set to their default values by h_reset. all bits are also set to their default values before eeprom data are loaded or after an eeprom read failure. the default value for all bits in this register is 0. table 34. autopoll2: auto-poll2 register bit name description 15 ap_reg2_en enable bit for autopoll register 2. when this bit and the auto-poll external phy bit (apep) in cmd1 are both set to 1, the auto-poll state machine periodically reads the external phy register selected by the ap_phy2_addr and ap_reg2_addr fields and sets the apint2 interrupt bit if it detects a change in the register ? s contents. 14-13 res reserved locations. written as zeros and read as undefined. 12-8 ap_reg2_addr ap_reg2 address. this field contains the register number of an external phy register that the auto-poll state machine will periodically read if the ap_reg2_en bit in this register and the apep bit (cmd3, bit 24) is set. 7 res reserved location. written as zero and read as undefined. 6 ap_pre_sup2 auto-poll preamble suppression. if this bit is set to 1, the auto-poll state machine will suppress the preambles of the mii management frames that it uses to periodically read the external phy register selected by the ap_phy2_addr and ap_reg2_addr fields. this bit is ignored when the ap_phy2_dflt bit is set. 5 ap_phy2_dflt auto-poll phy2 default. when this bit is set, the auto-poll state machine ignores the contents of the ap_phy2_addr and ap_pre_sup2 fields and uses the ap_phy0_addr field for the address of the phy device to be polled. if this bit is set, the auto-poll state machine will suppress preambles only if the port manager has determined that the default external phy can accept mii management frames without preambles. (the port manager examines bit 6 in register 1 of the default phy to make this determination.) 4-0 ap_phy2_addr auto-poll phy2 address. this field contains the address of the external phy that contains ap_reg2. this bit is ignored when the ap_phy2_dflt bit is set. 126 am79c976 8/01/00 preliminary autopoll3: auto-poll3 register offset 08eh this register controls the automatic polling of a user- selectable external phy register, ap_reg3. all bits in this register are set to their default values by h_reset. all bits are also set to their default values before eeprom data are loaded or after an eeprom read failure. the default value for all bits in this register is 0. table 35. autopoll3: auto-poll3 register bit name description 15 ap_reg3_en enable bit for autopoll register 3. when this bit and the auto-poll external phy bit (apep) in cmd1 are both set to 1, the auto-poll state machine periodically reads the external phy register selected by the ap_phy3_addr and ap_reg3_addr fields and sets the apint3 interrupt bit if it detects a change in the register ? s contents. 14-13 res reserved locations. written as zeros and read as undefined. 12-8 ap_reg3_addr ap_reg3 address. this field contains the register number of an external phy register that the auto-poll state machine will periodically read if the ap_reg3_en bit in this register and the apep bit (cmd3, bit 24) is set. 7 res reserved location. written as zero and read as undefined. 6 ap_pre_sup3 auto-poll preamble suppression. if this bit is set to 1, the auto-poll state machine will suppress the preambles of the mii management frames that it uses to periodically read the external phy register selected by the ap_phy3_addr and ap_reg3_addr fields. this bit is ignored when the ap_phy3_dflt bit is set. 5 ap_phy3_dflt auto-poll phy3 default. when this bit is set, the auto-poll state machine ignores the contents of the ap_phy3_addr and ap_pre_sup3 fields and uses the ap_phy0_addr field for the address of the phy device to be polled. if this bit is set, the auto-poll state machine will suppress preambles only if the port manager has determined that the default external phy can accept mii management frames without preambles. (the port manager examines bit 6 in register 1 of the default phy to make this determination.) 4-0 ap_phy3_addr auto-poll phy3 address. this field contains the address of the external phy that contains ap_reg3. this bit is ignored when the ap_phy3_dflt bit is set. 8/01/00 am79c976 127 preliminary autopoll4: auto-poll4 register offset 090h this register controls the automatic polling of a user- selectable external phy register, ap_reg4. all bits in this register are set to their default values by h_reset. all bits are also set to their default values before eeprom data are loaded or after an eeprom read failure. the default value for all bits in this register is 0. table 36. autopoll4: auto-poll4 register bit name description 15 ap_reg4_en enable bit for autopoll register 4. when this bit and the auto-poll external phy bit (apep) in cmd1 are both set to 1, the auto-poll state machine periodically reads the external phy register selected by the ap_phy4_addr and ap_reg4_addr fields and sets the apint4 interrupt bit if it detects a change in the register ? s contents. 14-13 res reserved locations. written as zeros and read as undefined. 12-8 ap_reg4_addr ap_reg4 address. this field contains the register number of an external phy register that the auto-poll state machine will periodically read if the ap_reg4_en bit in this register and the apep bit (cmd3, bit 24) is set. 7 res reserved location. written as zero and read as undefined. 6 ap_pre_sup4 auto-poll preamble suppression. if this bit is set to 1, the auto-poll state machine will suppress the preambles of the mii management frames that it uses to periodically read the external phy register selected by the ap_phy4_addr and ap_reg4_addr fields. this bit is ignored when the ap_phy4_dflt bit is set. 5 ap_phy4_dflt auto-poll phy4 default. when this bit is set, the auto-poll state machine ignores the contents of the ap_phy4_addr and ap_pre_sup4 fields and uses the ap_phy0_addr field for the address of the phy device to be polled. if this bit is set, the auto-poll state machine will suppress preambles only if the port manager has determined that the default external phy can accept mii management frames without preambles. (the port manager examines bit 6 in register 1 of the default phy to make this determination.) 4-0 ap_phy4_addr auto-poll phy4 address. this field contains the address of the external phy that contains ap_reg4. this bit is ignored when the ap_phy4_dflt bit is set. 128 am79c976 8/01/00 preliminary autopoll5: auto-poll5 register offset 092h this register controls the automatic polling of a user- selectable external phy register, ap_reg5. all bits in this register are set to their default values by h_reset. all bits are also set to their default values before eeprom data are loaded or after an eeprom read failure. the default value for all bits in this register is 0. table 37. autopoll5: auto-poll5 register *?( offset 120h this 64-bit register allows the receive descriptor ring to be located anywhere in a 64-bit address space. for systems with a 32-bit or smaller address space, it is only necessary to program the lower 32 bits of this reg- ister (by writing to offset 120h). the upper 32 bits will remain at the default value of 0. the contents of this register are set to the default value 0 when the rst pin is asserted. this register is not af- fected by the serial eeprom read operation or by a se- rial eeprom read error. table 38. receive ring base address register bit name description 15 ap_reg5_en enable bit for autopoll register 5. when this bit and the auto-poll external phy bit (apep) in cmd1 are both set to 1, the auto-poll state machine periodically reads the external phy register selected by the ap_phy5_addr and ap_reg5_addr fields and sets the apint5 interrupt bit if it detects a change in the register ? s contents. 14-13 res reserved locations. written as zeros and read as undefined. 12-8 ap_reg5_addr ap_reg5 address. this field contains the register number of an external phy register that the auto-poll state machine will periodically read if the ap_reg5_en bit in this register and the apep bit (cmd3, bit 24) is set. 7 res reserved location. written as zero and read as undefined. 6 ap_pre_sup5 auto-poll preamble suppression. if this bit is set to 1, the auto-poll state machine will suppress the preambles of the mii management frames that it uses to periodically read the external phy register selected by the ap_phy5_addr and ap_reg5_addr fields. this bit is ignored when the ap_phy5_dflt bit is set. 5 ap_phy5_dflt auto-poll phy5 default. when this bit is set, the auto-poll state machine ignores the contents of the ap_phy5_addr and ap_pre_sup5 fields and uses the ap_phy0_addr field for the address of the phy device to be polled. if this bit is set, the auto-poll state machine will suppress preambles only if the port manager has determined that the default external phy can accept mii management frames without preambles. (the port manager examines bit 6 in register 1 of the default phy to make this determination.) 4-0 ap_phy5_addr auto-poll phy5 address. this field contains the address of the external phy that contains ap_reg5. this bit is ignored when the ap_phy5_dflt bit is set. bit name description 63-0 badr base address of receive descriptor ring. in systems with a 32-bit or smaller address space, it is only necessary to program the 32 low-order bits of this register. the low order 32 bits of this register are an alias of csr24 and csr25. 8/01/00 am79c976 129 preliminary badx: transmit ring base address register offset 100h this 64-bit register allows the transmit descriptor ring to be located anywhere in a 64-bit address space. for systems with a 32-bit or smaller address space, it is only necessary to program the lower 32 bits of this reg- ister (by writing to offset 100h). the upper 32 bits will remain at the default value of 0. the contents of this register are set to the default value 0 when the rst pin is asserted. this register is not af- fected by the serial eeprom read operation or by a se- rial eeprom read error. table 39. transmit ring base address register .0*?+ '* offset 0f0h this read-only register is an alias of csr88. table 40. chipid: chip id register .0 << #%?+ 0 ! offset 18ah the contents of this register are cleared to 0 when the rst pin is asserted, before the serial eeprom is read, and after a serial eeprom read error. table 41. chpolltime: chain polling interval register bit name description 63-0 badx base address of transmit descriptor ring. in systems with a 32-bit or smaller address space, it is only necessary to program the 32 low-order bits of this register. the low-order 32 bits of this register are an alias of csr30 and csr31. bit name description 31-28 ver version. this 4-bit pattern is silicon-revision dependent. 27-12 partid part number. the 16-bit code for the am79c976 controller is 0010 0110 0010 1000b (2628h). this register is exactly the same as the device id register in the jtag description. however, this part number is different from that stored in the device id register in the pci configuration space. 11-1 manfid manufacturer id. the 11-bit manufacturer code for amd is 00000000001b. this code is per the jedec publication 106-a. note that this code is not the same as the vendor id in the pci configuration space. 0onealways logic 1. bit name description 15-0 chpoll time chain polling interval. this register contains the time that the am79c976 controller will wait between successive polling operations when the buffer management unit is in the middle of a buffer chaining operation. the chpolltime value is expressed as the two ? s complement of the desired interval, where each bit of chpolltime approximately represents 3 erclk periods. chpolltime[3:0] are ignored. (chpolltime[16] is implied to be a 1, so chpolltime[15] is significant and does not represent the sign of the two ? s complement chpolltime value.) the default value of this register is 0000h. this corresponds to a polling interval of 65,536 clock periods (2.185 ms when erclk = 90 mhz). setting the init bit starts an initialization process that sets chpolltime to its default value. if the user wants to program a value for chpolltime other than the default, then he must change the value after the initialization sequence has completed. this register is an alias for csr49. 130 am79c976 8/01/00 preliminary #*4?!!4 offset 048h cmd0 is a command-style register. all bits in this reg- ister are cleared to 0 when the rst pin is asserted, be- fore the serial eeprom is read, and after a serial eeprom read error. table 42. cmd0: command0 register bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15 val1 value bit for byte 1. the value of this bit is written to any bits in the cmd0 register that correspond to bits in the cmd0[14:8] bit map field that are set to 1. 14-13 res reserved locations. written as zeros and read as undefined. 12 rdmd receive demand, when set, causes the descriptor management unit to access the receive descriptor ring without waiting for the chain poll-time counter to expire. 11-9 res reserved locations. written as zeros and read as undefined. 8tdmd transmit demand, when set, causes the buffer management unit to access the transmit descriptor ring without waiting for the poll-time counter to elapse. if txon is not enabled, tdmd bit will be reset and no transmit descriptor ring access will occur. if the txdpoll bit in cmd2 is set, the host processor must set tdmd each time it is ready for the am79c976 device to poll the transmit descriptor ring. when txdpoll = 0, setting tdmd merely hastens the am79c976 controller ? s next access to a transmit descriptor ring entry. 7val0 value bit for byte 0. the value of this bit is written to any bits in the cmd0 register that correspond to bits in the cmd0[6:0] bit map field that are set to 1. 6uintcmd user interrupt command. uintcmd can be used by the host to generate an interrupt unrelated to any network activity. writing a 1 to this bit causes the uint bit in the interrupt register to be set to 1, which in turn causes inta to be asserted if interrupts are enabled. uintcmd is always read as 0. 5 rx_fast_ spnd receive fast suspend. setting this bit causes the receiver to suspend its activities as quickly as possible without stopping in the middle of a frame reception. setting rx_fast_spnd does not stop the dma controller from transferring frame data from the receive fifo to host memory. if a frame is being received at the time that rx_fast_spnd is set to 1, the reception of that frame will be completed, but no more frames will be received until rx_fast_spnd is cleared to 0. after the receiver has suspended its activity, the rx_suspended bit in the status register and the suspend interrupt (spndint) bit in the interrupt register will be set, which will cause an interrupt to occur if interrupts are enabled and the spndinten bit in the interrupt enable register is set. 4 tx_fast_spnd transmit fast suspend. setting this bit causes the transmitter to suspend its activities as quickly as possible without stopping in the middle of a frame transmission. setting tx_fast_spnd does not stop the dma controller from transferring frame data from host memory to the transmit fifo. if a frame is being transmitted at the time that tx_fast_spnd is set to 1, the transmission of that frame will be completed, but no more frames will be transmitted until tx_fast_spnd is cleared to 0. after the transmitter has suspended its activity, the tx_suspended bit in the status register and the suspend interrupt (spndint) bit in the int0 register will be set, which will cause an interrupt to occur if interrupts are enabled and the spndinten bit in the interrupt enable register is set. 8/01/00 am79c976 131 preliminary #* ?!! offset 050h cmd2 is a command-style register. all bits in this reg- ister are cleared to 0 when the rst pin is asserted, be- fore the serial eeprom is read, and after a serial eeprom read error. table 43. cmd2: command2 register 3 rx_spnd receive suspend. setting this bit causes the receiver to suspend its activities without stopping in the middle of a frame reception. after the receiver suspends its activities, the dma controller continues copying data from the receive fifo into host system memory until the fifo is empty or until no more receive descriptors are available. after the receive fifo has been emptied or after all receive descriptors have been used, the receive dma controller suspends its polling activity, and the rx_suspended bit in the status register and the suspend interrupt (spndint) bit in the interrupt register will be set. setting the spndint bit will cause an interrupt to occur if interrupts are enabled and the spndinten bit in the interrupt enable register is set. 2tx_spnd transmit suspend. setting this bit causes the transmitter to suspend its activities without stopping in the middle of a frame transmission. after the transmitter suspends its activities, the dma controller continues copying data from host system memory into the transmit fifo until the fifo is full or until no more transmit descriptors are available. after the transmit fifo has been filled or after all transmit descriptors have been used, the transmit dma controller suspends its polling activity, and the tx_suspended bit in the status register and the suspend interrupt (spndint) bit in the interrupt register will be set. setting the spndint bit will cause an interrupt to occur if interrupts are enabled and the spndinten bit in the interrupt enable register is set. 1 intren interrupt enable. this bit allows inta to be asserted if any bit in the interrupt register is set. if intren is cleared to 0, inta will not be asserted, regardless of the state of the interrupt register. intren is not an alias of the iena bit in csr0. 0run setting the run bit enables the am79c976 controller to start processing descriptors and transmitting and receiving packets. clearing the run bit to 0 abruptly disables the transmitter, receiver, and descriptor processing logic, possibly while a frame is being transmitted or received. the act of changing the run bit from 1 to 0 causes the following bits to be reset to 0: iena, tx_spnd, rx_spnd, tdmd, rdmd, uintcmd, tx_fast_spnd, rint, tint, txstrtint, txdnint, mpint, and uint. bit name description bit name description 31 val3 value bit for byte 3. the value of this bit is written to any bits in the cmd2 register that correspond to bits in the cmd2[30:24] bit map field that are set to 1. 30 nouflo no underflow on transmit. when the nouflo bit is set to 1, the am79c976 controller will not start transmitting the preamble for a packet until the transmit start point (ctrl1, bits 16-17) requirement has been met and the complete packet has been copied into the transmit fifo. when the nouflo bit is cleared to 0, the transmit start point is the only restriction on when preamble transmission begins for transmit packets. setting the nouflo bit guarantees that the am79c976 controller will never suffer transmit underflows, because the arbiter that controls transfers to and from the ssram guarantees a worst case latency on transfers to and from the mac and bus transmit fifos such that it will never underflow if the complete packet has been copied into the am79c976 controller before packet transmission begins. this bit is an alias of bcr18, bit 11. it is included only to allow programming from the eeprom for compatibility with legacy software. 132 am79c976 8/01/00 preliminary 29 ledpe led program enable. when ledpe is set to 1, programming of the led functions through bcr4, bcr5, bcr6, and bcr7 is enabled. when ledpe is cleared to 0, programming of led functions through these registers is disabled. writes to these registers will be ignored. however, ledpe does not affect the programming of led functions through the memory mapped led registers, led0, led1, led2 and led3. the memory-mapped led registers are always enabled, regardless of the state of ledpe. this bit is an alias of bcr2, bit 12. it is included only to allow programming from the eeprom for compatibility with legacy software. 28 dwio double word i/o. when set, this bit indicates that the am79c976 controller is programmed for dword i/o (dwio) mode. when cleared, this bit indicates that the am79c976 controller is programmed for word i/o (wio) mode. this bit affects the i/o resource offset map and it affects the defined width of the am79c976 controllers i/o resources. see the dwio and wio sections for more details. the initial value of the dwio bit is determined by the programming of the eeprom. the value of dwio can be altered automatically by the am79c976 controller. specifically, the am79c976 controller will set dwio if it detects a dword write access to offset 10h from the am79c976 controller i/o base address (corresponding to the rdp resource). this bit is an alias of bcr18, bit 7. it is included only to allow programming from the eeprom for compatibility with legacy software. 27 apromwe address prom write enable. the am79c976 controller contains a 16-byte shadow ram on board that emulates a small prom that was used in conjunction with early amd ethernet controllers. accesses to address prom i/o space will be directed to this ram. when apromwe is set to 1, then write access to the shadow ram will be enabled. this bit is an alias of bcr12, bit 8. it is included only to allow programming from the eeprom for compatibility with legacy software. 26-24 res reserved locations. written as zeros and read as undefined. 23 val2 value bit for byte 2. the value of this bit is written to any bits in the cmd2 register that correspond to bits in the cmd2[22:16] bit map field that are set to 1. 22-21 res reserved locations. written as zeros and read as undefined. 20 fdrpa full-duplex runt packet accept. when fdrpa is cleared to 0 and full-duplex mode is enabled, the am79c976 controller will only receive frames that meet the minimum ethernet frame length of 64 bytes. receive dma will not start until at least 64 bytes or a complete frame have been received. by default, fdrpa is cleared to 0. when fdrpa is set to 1, the am79c976 controller will accept any frame of 12 bytes or greater, and receive dma will start according to the programming of the receive fifo watermark. this bit is the inverse of bcr9, bit 2. 19 rpa runt packet accept. this bit forces the am79c976 controller to accept runt packets (packets shorter than 64 bytes). the minimum packet size that can be received is 12 bytes. this bit is an alias of csr124, bit 3. 18 drcvpa disable receive physical address. when set, the physical address detection (station or node id) of the am79c976 controller will be disabled. frames addressed to the node ? s individual physical address will not be recognized. this bit is an alias of csr15, bit 13. 17 drcvbc disable receive broadcast. when set, disables the am79c976 controller from receiving broadcast messages. used for protocols that do not support broadcast addressing, except as a function of multicast. drcvbc is cleared by activation of h_reset or s_reset (broadcast messages will be received) and is unaffected by stop. this bit is an alias of csr15, bit 14. 16 prom promiscuous mode. when prom = 1, all incoming receive frames are accepted, regardless of their destination addresses. this bit is an alias of csr15, bit 15. bit name description 8/01/00 am79c976 133 preliminary 15 val1 value bit for byte 1. the value of this bit is written to any bits in the cmd2 register that correspond to bits in the cmd2[14:8] bit map field that are set to 1. 14 rcvalgn receive packet align. when set, this bit forces the data field of iso 8802-3 (ieee/ansi 802.3) packets to align to 0 mod 4 address boundaries (i.e., dword aligned addresses). it is important to note that this feature will only function correctly if all receive buffer boundaries are dword aligned and all receive buffers have 0 mod 4 lengths. in order to accomplish the data alignment, the am79c976 controller simply inserts two bytes of random data at the beginning of the receive packet (i.e., before the iso 8802-3 (ieee/ansi 802.3) destination address field). the mcnt field reported to the receive descriptor will not include the extra two bytes. this bit is an alias of csr122, bit 0. 13 astrp_rcv auto strip receive. when set, astrp_rcv enables the automatic pad stripping feature. for any receive frame whose length field has a value less than 46, the pad and fcs fields will be stripped and not placed in the fifo. this bit is an alias of csr4, bit 10. 12 fcoll force collision. this bit allows the collision logic to be tested. the am79c976 controller must be in internal loopback for fcoll to be valid. if fcoll = 1, a collision will be forced during loopback transmission attempts, which will result in a retry error. if fcoll = 0, the force collision logic will be disabled. this bit is an alias of csr15, bit 4. 11 emba enable modified back-off algorithm (see contention resolution section in media access management section for more details). if emba is set, a modified back-off algorithm is implemented. this bit is an alias of csr3, bit 3. 10 dxmt2pd disable transmit two part deferral (see medium allocation section in the media access management section for more details). if dxmt2pd is set, transmit two part deferral will be disabled. this bit is an alias of csr3, bit 4. 9ltinten last transmit interrupt enable. when this bit is set to 1, the ltint bit in transmit descriptors can be used to determine when transmit interrupts occur. the transmit interrupt (tint) bit will be set after a frame has been copied to the transmit fifo if the ltint bit in the frame ? s last transmit descriptor is set. if the ltint bit in the frame ? s last descriptor is 0 tint will not be set after the frame has been copied to the transmit fifo. this bit is an alias of csr5, bit 14. 8dxmtfcs disable transmit crc (fcs). when dxmtfcs is set to 0, the transmitter will generate and append an fcs to the transmitted frame. when dxmtfcs is set to 1, no fcs is generated or sent with the transmitted frame. dxmtfcs is overridden when add_fcs and enp bits are set in the transmit descriptor. when the auto padding logic, which is enabled by the apad_xmt bit (cmd2, bit6), adds padding to a frame, a valid fcs field is appended to the frame, regardless of the state of dxmtfcs. if dxmtfcs is set and add_fcs is clear for a particular frame, no fcs will be generated. if add_fcs is set for a particular frame, the state of dxmtfcs is ignored and a fcs will be appended on that frame by the transmit circuitry. see also the add_fcs bit in the transmit descriptor. this bit was called dtcr in the lance (am7990) device. this bit is an alias of csr15, bit 3. 7val0 value bit for byte 0. the value of this bit is written to any bits in the cmd2 register that correspond to bits in the cmd2[6:0] bit map field that are set to 1. bit name description 134 am79c976 8/01/00 preliminary 6apad_xmt auto pad transmit. when set, apad_xmt enables the automatic padding feature. transmit frames will be padded to extend them to 64 bytes including fcs. the fcs is calculated for the entire frame, including pad, and appended after the pad field. when the auto padding logic modifies a frame, a valid fcs field will be appended to the frame, regardless of the state of the dxmtfcs bit (cmd2, bit 8) and of the add_fcs bit in the transmit descriptor. this bit is an alias of csr4, bit 11. 5drty disable retry. when drty is set to 1, the am79c976 controller will attempt only one transmission. in this mode, the device will not protect the first 64 bytes of frame data in the transmit fifo from being overwritten, because automatic retransmission will not be necessary. when drty is set to 0, the am79c976 controller will attempt 16 transmissions before signaling a retry error. this bit is an alias of csr15, bit 5. 4inloop internal loopback. when this bit is set, the transmitter is internally connected to the receiver so that the txd[3:0] outputs are connected internally to the rxd[3:0] inputs, the tx_en output is connected to the rx_dv input, and rx_clk is connected to tx_clk. the device is forced into full duplex mode so that collisions can not occur. the inloop and exloop bits should not be set at the same time. setting inloop to 1 is equivalent to setting loop (in csr15) to 1 and miiilp (in bcr32) to 1. 3 exloop external loopback. when this bit is set, the device is forced into full duplex mode so that collisions can not occur during loop back testing. if the txd[3:0] outputs are connected externally to the rxd[3:0] inputs, the tx_en output is externally connected to the rx_dv input, and rx_clk is connected to tx_clk, then transmitted frames will also be received. this connection can be made by attaching an external jumper or by programming an attached phy to loopback mode. the inloop and exloop bits should not be set at the same time. setting exloop to 1 is equivalent to setting loop (in csr15) to 1 and miiilp (in bcr32) to 0. 2 lappen look ahead packet processing enable. when set to a 1, the lappen bit will cause the am79c976 controller to generate an interrupt following the descriptor write operation to the first buffer of a receive frame. this interrupt will be generated in addition to the interrupt that is generated following the descriptor write operation to the last buffer of a receive packet. the interrupt will be signaled through the rint bit of csr0 or the int register. setting lappen to a 1 also modifies the way the controller accesses the receive descriptors. see the look ahead packet processing section. this bit is an alias of csr3, bit 5. see appendix a for more information on the look ahead packet processing concept. 1 chdpoll disable chain polling. if chdpoll is set, the buffer management unit will disable chain polling. likewise, if chdpoll is cleared, automatic chain polling is enabled. if chdpoll is set and the buffer management unit is in the middle of a buffer-changing operation, setting the rdmd bit in cmd0 or csr7 will cause a poll of the current receive descriptor, and setting the tdmd bit in cmd0 or crr0 will cause a poll of the current transmit descriptor. if chdpoll is set, the rdmd bit in csr7 or cmd0 can be set to initiate a manual poll of a receive or transmit descriptor if the buffer management unit is in the middle of a buffer-chaining operation. this bit is an alias of csr7, bit 12. 0txdpoll disable transmit polling. if txdpoll is set, the buffer management unit will disable transmit polling. likewise, if txdpoll is cleared, automatic transmit polling is enabled. if txdpoll is set, tdmd bit in csr0 or cmd0 must be set in order to initiate a manual poll of a transmit descriptor. transmit descriptor polling will not take place if txon is reset. transmit polling will take place following receive activities. this bit is an alias of csr4, bit 12. bit name description 8/01/00 am79c976 135 preliminary cmd3: command3 offset 054h cmd3 is a command-style register. all bits in this reg- ister are cleared to 0 when the rst pin is asserted, be- fore the serial eeprom is read, and after a serial eeprom read error. table 44. cmd3: command3 register bit name description 31 val3 value bit for byte 3. the value of this bit is written to any bits in the cmd3 register that correspond to bits in the cmd3[30:24] bit map field that are set to 1. 30 prefetch_dis disable prefetchability. this bit, which can be loaded from eeprom, is the inverse of the value reported in the prefetch bit in the pci memory-mapped i/o base address register, which is read-only. setting prefetch_dis to 1 indicates that the memory space claimed by this device can not be prefetched. because of the side effects of reading the reset register at offset 14h or 18h (depending on the state of dwio (cmd2, bit 28)), locations at offsets less than 20h cannot be prefetched. the am79c976 device will disconnect any attempted burst transfer at offsets less than 20h. if a logical 1 is written to this bit position, the corresponding bit in the register will be loaded with the contents of the val3 bit. if a logical 0 is written to this bit position, the corresponding bit in the register will not be altered. 29 dis_read_wait disable read wait. when this bit is set to 1, the controller will not insert irdy wait states in burst read transfers. 28 dis_write_wait disable write wait. when this bit is set to 1, the controller will not insert irdy wait states in burst write transfers. 27 disable_mwi disable mwi. when this bit is set to 1, the controller will not generate mwi pci bus commands. 26 rst_phy reset phy. when this bit is set to 1, the controller will assert the phy_rst signal. the signal will remain asserted for as long as this bit remains set. 25 init_mib initialize management information base counters. setting this bit will cause all of the mib counters to be reset to 0. resetting these counters takes about 55 erclk cycles. this bit is cleared automatically after the counters have all been reset to 0. this bit must not be set to 1 by the eeprom logic. if a logical 1 is written to this bit position, the corresponding bit in the register will be loaded with the contents of the val3 bit. if a logical 0 is written to this bit position, the corresponding bit in the register will not be altered. 24 apep mii auto-poll external phy (apep) when set to 1, the am79c976 controller will poll the mii status register in the external phy. this feature allows the software driver or upper layers to see any changes in the status of the external phy. an interrupt, when enabled, is generated when the contents of the new status is different from the previous status. this bit is an alias of bcr32, bit 11. 23 val2 value bit for byte 2. the value of this bit is written to any bits in the cmd3 register that correspond to bits in the cmd3[22:16] bit map field that are set to 1. 22 res reserved. written as 1 and read as undefined. 21 jumbo accept jumbo frames. this bit affects the way the mib counters count long frames. if jumbo is 0, only frames that are between 64 and 1518 bytes (or 1522 bytes if vlan is set to 1) are counted as valid frames. when jumbo is 1, any frame longer than 63 bytes with a valid fcs field is counted as a valid frame. 20 vsize vlan frame size. this bit determines the maximum frame size used for determining when to increment the xmtpkts1024to1518octets, xmtexcessivedefer, rcvpkts1024to1518octets, and rcvoversizepkts mib counters and when to assert the excessive deferral interrupt. when this bit is set to 1 the maximum frame size is 1522 bytes. when it is cleared to 0, the maximum frame size is 1518 bytes. 136 am79c976 8/01/00 preliminary 19 vlonly admit only vlan frames. when this bit is set to 1, only frames with a vlan tag header containing a non-zero vlan id field will be received. all other frames will be rejected. 18 rex_rtry retransmit on retry error. when this bit is set to 1, if collisions occur for 16 attempts to transmit a frame, the back-off logic is reset, but the frame is not discarded. instead, it is treated as if it were the next frame in the transmit queue. when this bit is cleared to 0, if collisions occur for 16 attempts to transmit a frame, the frame is dropped. in either case, if collisions occur for 16 attempts to transmit a frame, the xmtexcessivecollision counter is incremented. 17 rex_uflo retransmit on underflow. when this bit is set to 1, if the transmitter is forced to abort a transmission because the transmit fifo underflows, the transmitter will not discard the frame. instead, it will automatically wait until the entire frame has been loaded into the transmit fifo and then will restart the transmission process. when this bit is cleared to 0, if the transmitter is forced to abort a transmission because the fifo underflows, the transmitter will discard the frame. in either case, the xmtunderrunpkts counter will be incremented. 16 rtry_lcol retry on late collision. when this bit is set to 1, late collisions are treated like normal collisions, except that the xmtlatecollision counter and the xmtcollisions counter will both be incremented. when this bit is cleared to 0, if a late collision occurs, the transmitter will discard the frame that was being transmitted when the collision occurred. 15 val1 value bit for byte 1. the value of this bit is written to any bits in the cmd3 register that correspond to bits in the cmd3[14:8] bit map field that are set to 1. 14 dispm disable port manager. (the corresponding bit in older pcnet family devices is called disable auto-negotiation auto setup or danas. the name has been changed, but not the function.) when dispm is set, the network port manager function is disabled, and the host cpu is responsible for ensuring that the mac and external phy are operating in the same mode. this bit is an alias of bcr32, bit 7. 13 intlevel interrupt level. this bit allows the interrupt output signals to be programmed for level- or edge- sensitive applications. when intlevel is cleared to 0, the inta pin is configured for level-sensitive applications. in this mode, an interrupt request is signaled by a low level driven on the inta pin by the am79c976 controller. when the interrupt is cleared, the inta pin is tri-stated by the am79c976 controller and allowed to be pulled to a high level by an external pull-up device. this mode is intended for systems which allow the interrupt signal to be shared by multiple devices. when intlevel is set to 1, the inta pin is configured for edge-sensitive applications. in this mode, an interrupt request is signaled by a high level driven on the inta pin by the am79c976 controller. when the interrupt is cleared, the inta pin is driven to a low level by the am79c976 controller. this mode is intended for systems that do not allow interrupt channels to be shared by multiple devices. intlevel should not be set to 1 when the am79c976 controller is used in a pci bus application. this bit is an alias of bcr2, bit 7. 12 force_fd force full duplex. (this bit is called full-duplex enable (fden) in other pcnet family devices.) this bit controls whether full-duplex operation is enabled. when force_fd is cleared and the port manager is disabled, the am79c976 controller will always operate in the half-duplex mode. when force_fd is set, the am79c976 controller will operate in full-duplex mode. do not set this bit when the port manager is enabled . this bit is an alias of bcr9, bit 0. 11 force_ls force link status. when this bit is set, the internal link status is forced to the pass state regardless of the actual state of the phy device. when this bit is cleared to 0, the internal link status is determined by the port manager. bit name description 8/01/00 am79c976 137 preliminary 10 rxfrtgen receive frame tag enable. when this bit is set, frame tag data that is shifted in through the external address detection interface (eadi) while a frame is being received will be copied to the receive descriptor. 9 mpplba magic packet physical logical broadcast accept. if mpplba is at its default value of 0, the am79c976 controller will only detect a magic packet frame if the destination address of the packet matches the content of the physical address register (padr). if mpplba is set to 1, the destination address of the magic packet frame can be unicast, multicast, or broadcast. note that the setting of mpplba only affects the address detection of the magic packet frame. the magic packet frame ? s data sequence must be made up of 16 consecutive physical addresses (padr[47:0]) regardless of what kind of destination address it has. this bit is or ? ed with empplba bit (csr116, bit 6). this bit is an alias of csr5, bit 5. 8 mppen_ee magic packet pin enable. when either this bit or the mppen_sw bit in cmd7 is set, the device enters the magic packet mode when the pg input goes low. this bit has the same function as mppen_sw except that h_reset clears mppen_ee to 0, while h_reset has no effect on mppen_sw. this bit is an alias of csr116, bit 4. 7val0 value bit for byte 0. the value of this bit is written to any bits in the cmd3 register that correspond to bits in the cmd3[6:0] bit map field that are set to 1. 6 mpen_ee magic packet enable. when either this bit or the mpen_sw bit in cmd7 is set, the device enters the magic packet mode. this bit has the same function as mpen_sw except that h_reset clears mpen_ee to 0, while h_reset has no effect on mpen_sw. 5 lcmode_ee link change wake-up mode. when either this bit or the lcmode_sw bit in cmd7 is set to 1, the lcdet bit gets set when the mii auto polling logic detects a link change. this bit has the same function as lcmode_sw except that h_reset clears lcmode_ee to 0, while h_reset has no effect on lcmode_sw. this bit is an alias of csr116, bit 8. 4pme_en_ovr pme_en overwrite. when this bit is set and the mpmat or lcdet bit is set, the pme pin will always be asserted regardless of the state of pme_en bit. this bit is an alias of csr116, bit 10. 3 rwu_driver rwu driver type. if this bit is set to 1, rwu is a totem pole driver; otherwise, rwu is an open drain output. this bit is an alias of csr116, bit 3. 2rwu_gate rwu gate control. if this bit is set, rwu is forced to the high impedance state when pg is low, regardless of the state of the mpmat and lcdet bits. this bit is an alias of csr116, bit 2. 1rwu_pol rwu pin polarity. if rwu_pol is set to 1, the rwu pin is normally high and asserts low; otherwise, rwu is normally low and asserts high. this bit is an alias of csr116, bit 1. 0rst_pol phy_rst pin polarity. if the phy_pol is set to 1, the phy_rst pin is active low; otherwise, phy_rst is active high. this bit is an alias of csr116, bit 0. bit name description 138 am79c976 8/01/00 preliminary cmd7: command7 offset 064h cmd7 is a command-style register. all bits in this reg- ister are cleared to 0 when power is first applied to the device (power-on reset). the contents of this register are not affected by the state of the rst pin. the con- tents of this register can not be loaded from the eeprom. therefore, the contents of this register are not disturbed when pci bus power is removed and re- applied. table 45. cmd7: command7 register bit name description 31-8 res reserved locations. written as zeros and read as undefined. 7val0 value bit for byte 0. the value of this bit is written to any bits in the cmd7 register that correspond to bits in the cmd7[6:0] bit map field that are set to 1. 6-4 res reserved locations. written as zeros and read as undefined. 3pmat_mode pattern match mode. writing a 1 to this bit will enable pattern match mode and should only be done after the pattern match ram has been programmed. pattern match mode is enabled when either this bit or bcr45, bit 7 is set. 2 mppen_sw magic packet pin enable. when either this bit or the mppen_ee bit in cmd3 is set, the device enters the magic packet mode when the pg input goes low. this bit has the same function as mppen_ee except that h_reset clears mppen_ee to 0, while h_reset has no effect on mppen_sw. 1 mpen_sw magic packet software mode enable. the am79c976 controller enters the magic packet mode when this bit is set to 1. this bit has the same function as mpen_ee except that h_reset clears mpen_ee to 0, while h_reset has no effect on mpen_sw. 0 lcmode_sw link change wake-up mode. when either this bit or the lcmode_ee bit in cmd3 is set to 1, the lcdet bit gets set when the mii auto polling logic detects a link change. this bit has the same function as lcmode_ee except that h_reset clears lcmode_ee to 0, while h_reset has no effect on lcmode_sw. 8/01/00 am79c976 139 preliminary ctrl0: control0 register offset 068h this register contains several miscellaneous control bits. each byte of this register controls a single func- tion. it is not necessary to do a read-modify-write oper- ation to change a function ? s settings if only a single byte of the register is written. all bits in this register are set to their default values by h_reset. all bits are also set to their default values before eeprom data are loaded or after an eeprom read failure. the default value for all bits except for bits 11:8 (romtmg) is 0. the default value for the romtmg field is 1001b. table 46. ctrl0: control0 register bit name description 31-25 res reserved locations. written as zeros and read as undefined. 24 bswp byte swap. this bit is used to choose between big and little endian modes of operation. when bswp is set to a 1, big endian mode is selected. when bswp is set to 0, little endian mode is selected. when big endian mode is selected, the am79c976 controller will swap the order of bytes on the ad bus during a data phase on accesses to the fifos only. specifically, ad[31:24] becomes byte 0, ad[23:16] becomes byte 1, ad[15:8] becomes byte 2, and ad[7:0] becomes byte 3 when big endian mode is selected. when little endian mode is selected, the order of bytes on the ad bus during a data phase is: ad[31:24] is byte 3, ad[23:16] is byte 2, ad[15:8] is byte 1, and ad[7:0] is byte 0. byte swap only affects data transfers that involve the fifos. initialization block transfers are not affected by the setting of the bswp bit. descriptor transfers are not affected by the setting of the bswp bit. rdp, rap, bdp and pci configuration space accesses are not affected by the setting of the bswp bit. address prom transfers are not affected by the setting of the bswp bit. expansion rom accesses are not affected by the setting of the bswp bit. note that the byte ordering of the pci bus is defined to be little endian. bswp should not be set to 1 when the am79c976 controller is used in a pci bus application. this bit is an alias of csr3, bit 2. 23:18 res reserved locations. written as zeros and read as undefined. 17-16 sram_type ssram type. this field must be set up to indicate the type of external ssram that is connected to the external memory interface. 15-12 res reserved locations. written as zeros and read as undefined. sram_type[1:0] external memory type 00 reserved 01 zbt 10 reserved 11 pipelined burst 140 am79c976 8/01/00 preliminary <? offset 06ch this register contains several miscellaneous control bits. each byte of this register controls a single func- tion. it is not necessary to do a read-modify-write oper- ation to change a function ? s settings if only a single byte of the register is written. all bits in this register are set to their default values by h_reset. all bits are also set to their default values before eeprom data are loaded or after an eeprom read failure. the default value for all bits except for bits 17:16 (xmtsp) and bits 1:0 (rcvfw) is 0. the default value for the xmtsp field is 01b (64 bytes). the default value for the rcvfw field is also 01b. table 47. ctrl1: control1 register 11-8 romtmg expansion rom timing. the value of romtmg is used to tune the timing for all accesses to the external flash/eprom. romtmg defines the amount of time that a valid address is driven on the era[19:0] pins. the register value specifies delay in number of romclk cycles, where romclk is an internal clock signal that runs at one fourth the speed of erclk. note : programming romtmg with a value of 0 is not permitted. to ensure adequate expansion rom setup time, romtmg should be set to 1 plus tacc / (romclk period), where tacc is the access time of the expansion rom device (flash or eprom). (the extra romclk cycle is added to account for the era[19:0] output delay from romclk plus the erd[7:0] setup time to romclk.) romtmg is set to the default value of 1001b by h_reset. it is also set to its default value before the eeprom read process starts or when the eeprom read process fails. the default value allows using an expansion rom with an access time of 350 ns if erclk is running at 90 mhz. this field is an alias of bcr18, bits 15:12. 7-5 res reserved locations. written as zeros and read as undefined. 4 burst_align pci bus burst align. when this bit is set, if a burst transfer starts in the middle of a cache line, the transfer will stop at the first cache line boundary. 3-0 burst_limit pci bus burst limit. this 4-bit field limits the maximum length of a burst transfer. if the contents of this register are 0, the burst length is limited by the amount of data available or by the amount of fifo space available. if the contents of this field are not zero, a burst transfer will end when the transfer has crossed the number of cache line boundaries equal to the contents of this field. bit name description bit name description 31-26 res reserved locations. written as zeros and read as undefined. 25-24 slotmod slot time modulation. this field determines the value of the slot time parameter used for the mac half-duplex backoff algorithm. if slotmod is set to anything other than the default value of 0, the controller will not conform to ieee std 802.3. 23:18 res reserved locations. written as zeros and read as undefined. value slot time (bits) 00 512 (standard) 01 256 10 1024 11 reserved 8/01/00 am79c976 141 preliminary 17-16 xmtsp transmit start point. xmtsp controls the point at which preamble transmission attempts to commence in relation to the number of bytes written to the mac transmit fifo for the current transmit frame. when the entire frame is in the mac transmit fifo, transmission will start regardless of the value in xmtsp. if any of rex_uflo, rex_rtry, or rtry_lcol are set, no frame data will be overwritten until the frame has been transmitted or discarded. otherwise, no data will be overwritten until at least 64 bytes have been transmitted. note that when the no underflow (nouflo) bit (bcr18, bit 11) is set to 1 or xmtsp = 11b, transmission will not start until the complete frame has been copied into the transmit fifo. this mode is useful in a system where high latencies cannot be avoided. the default value for xmtsp[1:0] is 01b (64 bytes). this field is an alias of csr80, bits 11:10. 15-10 res reserved locations. written as zeros and read as undefined. 9-8 xmtfw transmit fifo watermark. xmtfw specifies the point at which transmit dma is requested, based upon the number of bytes that could be written to the transmit fifo without fifo overflow. transmit dma is requested when the number of bytes specified by xmtfw could be written to the fifo without causing transmit fifo overflow, and the internal state machine has reached a point where the transmit fifo is checked to determine if dma servicing is required. the default value for xmtfw[1:0] is 00b (16 bytes). this field is an alias of csr80, bits 9:8. bit name description xmtsp[1:0] nouflo bytes written 00 0 16 01 0 64 10 0 128 11 0 full frame xx 1 full frame xmtfw[1:0] bytes available 00 16 01 64 10 128 11 256 142 am79c976 8/01/00 preliminary 7-2 res reserved locations. written as zeros and read as undefined. 1-0 rcvfw receive fifo watermark. rcvfw controls the point at which receive dma is requested in relation to the number of received bytes in the receive fifo. rcvfw specifies the number of bytes which must be present (once the frame has been verified as a non-runt) before receive dma is requested. note, however, that if the network interface is operating in half-duplex mode, in order for receive dma to be performed for a new frame, at least 64 bytes must have been received. this effectively avoids having to react to receive frames which are runts or suffer a collision during the slot time (512 bit times). if the runt packet accept feature is enabled or if the network interface is operating in full-duplex mode, receive dma will be requested as soon as either the rcvfw threshold is reached, or a complete valid receive frame is detected (regardless of length). when the full duplex runt packet accept disable (fdrpad) bit in cmd2 is set and the am79c976 controller is in full- duplex mode, in order for receive dma to be performed for a new frame, at least 64 bytes must have been received. this effectively disables the runt packet accept feature in full-duplex mode. the default value for rcvfw[1:0] is 01b (64 bytes). this field is an alias of csr80, bits 13:12. bit name description rcvfw[1:0] bytes received 00 48 01 64 10 128 11 256 8/01/00 am79c976 143 preliminary ctrl2: control2 register offset 070h this register contains several miscellaneous control bits. each byte of this register controls a single func- tion. it is not necessary to do a read-modify-write oper- ation to change a function ? s settings if only a single byte of the register is written. all bits in this register are set to their default values by h_reset. all bits are also set to their default values before eeprom data are loaded or after an eeprom read failure. the default value for all bits except for bits 2:0 (apdw) is 0. the default value for the apdw field is 100b. table 48. ctrl2: control2 register bit name description 31-19 res reserved locations. written as zeros and read as undefined. 18-16 fs force speed. this three-bit field sets the mac ? s internal speed indicator according to the table below. the speed indication is used only for leds. 15-10 res reserved locations. written as zeros and read as undefined. 9-8 fmdc fast management data clock. when fmdc is set to 2h the mii management data clock will run at 10 mhz max. the management data clock will no longer be ieee 802.3u-compliant and setting this bit should be used with care. the accompanying external phy must also be able to accept management frames at the new clock rate. when fmdc is set to 1h, the mii management data clock will run at 5 mhz max. the management data clock will no longer be ieee 802.3u-compliant and setting this bit should be used with care. the accompanying external phy must also be able to accept management frames at the new clock rate. when fmdc is set to 0h, the mii management data clock will run at 2.5 mhz max and will be fully compliant to ieee 802.3u standards. this field is an alias of bcr32, bits13:12 7 res reserved location. written as zero and read as undefined. 6 xphyrst external phy reset. when xphyrst is set, the am79c976 controller after an h_reset or s_reset will issue an mii management frame that will reset the external phy. this bit is needed when there is no way to guarantee the state of the external phy. this bit must be reprogrammed after every h_reset. xphyrst is only valid when the internal network port manager is scanning for a network port. this bit is an alias of bcr32, bit 6. 5xphyane external phy auto-negotiation enable. this bit will force the external phy into enabling auto- negotiation. when set to 0 the am79c976 controller will send an mii management frame disabling auto-negotiation. xphyane is only valid when the internal network port manager is scanning for a network port. this bit is an alias of bcr32, bit 5. 4 xphyfd external phy full duplex. when set, this bit will force the external phy into full duplex when auto- negotiation is not enabled. xphyfd is only valid when the internal network port manager is scanning for a network port. this bit is an alias of bcr32, bit 4. fs[2:0] speed 000 speed determined by phy 001 reserved 010 10 mb/s 011 100 mb/s 1xx reserved 144 am79c976 8/01/00 preliminary < ? offset 074h all bits in this register are set to their default values by h_reset. all bits are also set to their default values before eeprom data are loaded or after an eeprom read failure. the default value for all bits is 0. table 49. ctrl3: control3 register table 50. software styles 3 xphysp external phy speed. when set, this bit will force the external phy into 100 mbps mode when auto- negotiation is not enabled. xphysp is only valid when the internal network port manager is scanning for a network port. this bit is an alias of bcr32, bit 3. 2-0 apdw mii auto-poll dwell time. apdw determines the dwell time between mii management frames accesses when auto-poll is turned on. the default value of this field is 100b. this field is an alias of bcr32, bits 10:8. bit name description apdw auto-poll dwell time 000 continuous (26 s @ 2.5 mhz) 001 every 64 mdc cycles (51 s @ 2.5 mhz) 010 every 128 mdc cycles (103 s @ 2.5 mhz) 011 every 256 mdc cycles (206 s @ 2.5 mhz) 100 every 512 mdc cycles (410 s @ 2.5 mhz) 101 every 1024 mdc cycles (819 s @ 2.5 mhz) 110-111 reserved bit name description 31-8 res reserved locations. written as zeros and read as undefined. 7-0 swstyle software style register. the value in this register determines the style of register and memory resources that shall be used by the am79c976 controller. the software style selection will affect the interpretation of a few bits within the csr space, the order of the descriptor entries, and the width of the descriptors and initialization block entries. all am79c976 controller csr bits and bcr bits and all descriptor, buffer, and initialization block entries not cited in table 50 are unaffected by the software style selection and are, therefore, always fully functional as specified in the csr and bcr sections. swstyle [7:0] style name ssize32 initialization block entries descriptor ring entries 00h lance/ pcnet-isa controller 0 16-bit software structures, non-burst or burst access 16-bit software structures, non- burst access only 01h res 1 res res 8/01/00 am79c976 145 preliminary * # ?#!$ - - (( offset 1a0h this register is used to control and indirectly access the memory built-in self-test (mbist) logic that automati- cally tests the external ssram. the contents of this register are cleared to 0 when the rst pin is asserted. the register is not cleared at the start of a serial eeprom read operation or after a se- rial eeprom read error. table 51. datambist: memory built-in self-test access register 02h pcnet-pci controller 1 32-bit software structures, non-burst or burst access 32-bit software structures, non- burst access only 03h pcnet-pci controller 1 32-bit software structures, non-burst or burst access 32-bit software structures, non- burst or burst access 04h vlan 1 not used 32-bit software structures, non- burst or burst access 05h 64-bit address 1 not used 32-bit software structures, 32- byte descriptors, non-burst or burst access all other reserved undefined undefined undefined swstyle [7:0] style name ssize32 initialization block entries descriptor ring entries bit name description 63 dm_done mbist done indicator. this bit is set to 1 when the automatic memory test has stopped, either because the test has completed or because an error was detected. it is cleared to 0 when either dm_start or dm_resume is set. this bit is read-only. 62 dm_error mbist error indicator. this bit is set to 1 when the memory test logic has detected a memory error. it is cleared to 0 when either dm_start or dm_resume is set. this bit is read-only. 61 dm_start mbist start. setting this bit to 1 resets the mbist logic, including the dm_error and dm_test_fail bits, and starts the memory test process. dm_start should not be set at the same time that the dm_resume bit is set. dm_start is automatically cleared when the memory test stops. this bit is read/write. 60 dm_resume mbist resume. setting this bit to 1 restarts the memory test sequence at the point where it last stopped. setting this bit clears the dm_error bit, but it does not clear the dm_test_fail bit. this bit should not be set at the same time that the dm_start bit is set. dm_resume is automatically cleared when the memory test stops. this bit is read/write. 59 dm_fail_stop mbist stop on failure control. when this bit is set to 1, the memory test will stop each time an error is detected. when this bit is cleared to 0, the memory test will run to completion, regardless of the number of errors that are detected. this bit is read/write. 58 dm_test_fail mbist test failure indicator. this bit is set when a memory test error is detected. it is reset when dm_start is set to 1. it is not cleared when dm_resume is set to 1. this bit is read-only. 57 res reserved. written as 0, read as undefined. 146 am79c976 8/01/00 preliminary 56 dm_dir mbist test direction. this bit is set to 1 when the mbist memory pointer was counting down when the test stopped. it is cleared to 0 when the mbist memory pointer was counting up when the test stopped. this bit is read-only. 55-54 dm_fail_state mbist error offset indicator. this field indicates offset of the location of the last memory test error with respect to the value of the dm_addr field. the interpretation of this field depends on the value of the dm_dir field, which indicates whether the address pointer was counting up or down when the error was detected. this field is read-only. 53-52 dm_backg mbist background. this field contains the background pattern that the memory test logic was using when the test stopped. this field is read-only. 51-32 dm_addr mbist address. this field contains the contents of the mbist address pointer at the time that the test stopped. because of the pipelined nature of the external ssram, this value may not be the location of the memory error. the actual error location is obtained by adding or subtracting the contents of the dm_fail_state field as described above. this field is read-only. 31-0 dm_data mbist data. this field contains the last data that the memory test logic read from the external ssram. if the dm_err and dm_fail_stop bits are both set to 1, the contents of this field contains an error. this field is read-only. bit name description dm_dir fail_state error location 0 00 error at dm_address 0 01 error at dm_address-1 0 10 error at dm_address-2 0 11 error at dm_address-3 1 00 error at dm_address 1 01 error at dm_address+1 1 10 error at dm_address+2 1 11 error at dm_address+3 8/01/00 am79c976 147 preliminary delayed_int: delayed interrupts register offset 0c0h the contents of this register are cleared to 0 when the rst pin is asserted, before the serial eeprom is read, and after a serial eeprom read error. table 52. delayed_int: delayed interrupts register eeprom_acc: eeprom access register offset 17ch the contents of this register are set to default values when the rst pin is asserted. the register is not cleared at the start of a serial eeprom read operation or after a serial eeprom read error. the default value for all bits in this register is 0. this register is an alias of bcr19. bit name description 31-21 res reserved. written as 0, read as undefined. 20-16 event_count this field indicates the maximum number of receive and/or transmit interrupt events (rint and/ or tint) that can occur before a delayed interrupt signal occurs. 15-11 res reserved. written as 0, read as undefined. 10-0 max_delay this field indicates the maximum time (measured in units of 10 microseconds) that can elapse after an interrupt event before a delayed interrupt signal occurs. 148 am79c976 8/01/00 preliminary table 53. eeprom_acc: eeprom access register bit name description 15 pvalid eeprom valid status bit. pvalid is read only; write operations have no effect. a value of 1 in this bit indicates that a pread operation has occurred, and that (1) there is an eeprom connected to the am79c976 controller interface pins and (2) the contents read from the eeprom have passed the crc verification operation. a value of 0 in this bit indicates a failure in reading the eeprom. the crc for the eeprom is incorrect or no eeprom is connected to the interface pins. pvalid is set to 0 during h_reset. however, following the h_reset operation, an automatic read of the eeprom will be performed. just as is true for the normal pread command, at the end of this automatic read operation, the pvalid bit may be set to 1. therefore, h_reset will set the pvalid bit to 0 at first, but the automatic eeprom read operation may later set pvalid to a 1. if pvalid becomes 0 following an eeprom read operation (either automatically generated after h_reset, or requested through pread), then all eeprom-programmable registers will be reset to their default values. the content of the address prom locations, however, will not be cleared. if no eeprom is present at the eesk, eedi, and eedo pins, then all attempted pread commands will terminate early and pvalid will not be set. this applies to the automatic read of the eeprom after h_reset, as well as to host-initiated pread commands. 14 pread eeprom read command bit. when this bit is set to a 1 by the host, the pvalid bit (bit 15) will immediately be reset to a 0, and then the am79c976 controller will perform a read operation from the external serial eeprom. the eeprom data that is fetched during the read will be stored in the appropriate internal registers on board the am79c976 controller. upon completion of the eeprom read operation, the am79c976 controller will assert the pvalid bit. at the end of the read operation, the pread bit will automatically be reset to a 0 by the am79c976 controller and pvalid will be set, provided that an eeprom existed on the interface pins and that the crc for the eeprom was correct. note that when pread is set to a 1, then the am79c976 controller will no longer respond to any accesses directed toward it until the pread operation has completed successfully. the am79c976 controller will terminate these accesses with the assertion of devsel and stop while trdy is not asserted, signaling to the initiator to disconnect and retry the access at a later time. if a pread command is given to the am79c976 controller but no eeprom is attached to the interface pins, the pread bit will be cleared to a 0, and the pvalid bit will remain reset with a value of 0. this applies to the automatic read of the eeprom after h_reset as well as to host initiated pread commands. all eeprom programmable registers will be set to their default values by such an aborted pread operation. at the end of the read operation, if bit 15 of the pmc alias register is zero or the vaux_sense pin is low, the pme_status and pme_en bits of the pmcsr register will be reset. 13 eedet eeprom detect. this bit indicates whether or not an eeprom was detected by the erprom read operation. if this bit is a 1, it indicates that an eeprom was detected. if this bit is a 0, it indicates that an eeprom was not detected. eedet is read only; write operations have no effect. the value of this bit is determined at the end of the h_reset operation. 12-5 res reserved locations. written as zeros and read as undefined. 4 een eeprom port enable. when this bit is set to a 1, it causes the values of ecs, esk, and edi to be driven onto the eecs, eesk, and eedi pins, respectively. if een = 0 and no eeprom read function is currently active, then eecs will be driven low. when een = 0 and no eeprom read function is currently active, eesk and eedi pins will be driven by the led1 and led0 functions, respectively. see table 54. 3 res reserved location. written as 0; read as undefined. 8/01/00 am79c976 149 preliminary table 54. interface pin assignment 2ecs eeprom chip select. this bit is used to control the value of the eecs pin of the interface when the een bit is set to 1 and the pread bit is set to 0. if een = 1 and pread = 0 and ecs is set to a 1, then the eecs pin will be forced to a high level at the rising edge of the next clock following bit programming. if een = 1 and pread = 0 and ecs is set to a 0, then the eecs pin will be forced to a low level at the rising edge of the next clock following bit programming. ecs has no effect on the output value of the eecs pin unless the pread bit is set to 0 and the een bit is set to 1. 1 esk eeprom serial clock. this bit and the edi/edo bit are used to control host access to the eeprom. values programmed to this bit are placed onto the eesk pin at the rising edge of the next clock following bit programming, except when the pread bit is set to 1 or the een bit is set to 0. if both the esk bit and the edi/edo bit values are changed during the same register write operation, while een = 1, then setup and hold times of the eedi pin value with respect to the eesk signal edge are not guaranteed. esk has no effect on the eesk pin unless the pread bit is set to 0 and the een bit is set to 1. 0 edi/edo eeprom data in/eeprom data out. data that is written to this bit will appear on the eedi output of the interface, except when the pread bit is set to 1 or the een bit is set to 0. data that is read from this bit reflects the value of the eedo input of the interface. edi/edo has no effect on the eedi pin unless the pread bit is set to 0 and the een bit is set to 1. bit name description pin pread or auto read in progress een eecs eesk eedi low x x 0 tri-state tri-state high 1 x active active active high 0 1 from ecs bit from esk bit from edi bit high 0 0 0 led1 led0 150 am79c976 8/01/00 preliminary flash_addr: flash address register offset 198h the contents of this register are cleared to 0 when the rst pin is asserted. the register is not cleared at the start of a serial eeprom read operation or after a se- rial eeprom read error. table 55. flash_addr: flash address register <.@* ? +* offset 19ch the contents of this register are cleared to 0 when the rst pin is asserted. the register is not cleared at the start of a serial eeprom read operation or after a se- rial eeprom read error. this register is an alias of bcr30. table 56. flash_data: flash data register bit name description 31 laainc lower address auto increment. when the laainc bit is set to 1, the low-order 16-bit portion of the flash address register will automatically increment by one after a read or write access to the flash data register. when the low-order 16-bit portion of the flash address reaches ffffh and laainc is set to 1, the low-order 16-bit portion of the flash address will roll over to 0000h. when the laainc bit is set to 0, the flash address register will not be affected in any way after an access to the flash data register. this bit is an alias of bcr29, bit 14. 30-24 res reserved locations. written as zeros and read as undefined. 23-0 flash_ addr flash address. this field selects the byte of the external flash/rom device that will be accessed when the flash data register is accessed. this field is an alias of bcr29, bits [7:0] concatenated with bcr28, bits [15:0]. bit name description 15-8 res reserved locations. written as zeros and read as undefined. 7-0 flash_data flash data. this field contains data written to or read from the external flash/rom device. when the host cpu writes to this register, the contents of this field are written to the external flash device at the location selected by the flash address register. when the host cpu reads this register, the am79c976 device first reads the location in the flash device selected by the flash address register, then returns the value read in this field. 8/01/00 am79c976 151 preliminary flow: flow control register offset 0c8h flow is a command-style register. all bits in this reg- ister are cleared to 0 when the rst pin is asserted, be- fore the serial eeprom is read, and after a serial eeprom read error. table 57. flow: flow control register bit name description 31-24 res reserved locations. written as zeros and read as undefined. 23 val2 value bit for byte 2. the value of this bit is written to any bits in the flow register that correspond to bits in the flow[22:16] bit map field that are set to 1. 22-21 res reserved locations. written as zeros and read as undefined. 20 fpa force pause ability. when this bit is set, pause ability is enabled regardless of the pause ability state of the external phy ? s link partner. when pause ability is enabled, the receipt of a mac control pause frame causes the device to stop transmitting for a time period that is determined by the contents of the pause frame. if a logical 1 is written to this bit position, the corresponding bit in the register will be loaded with the contents of the val2 bit. if a logical 0 is written to this bit position, the corresponding bit in the register will not be altered. 19 npa negotiate pause ability. when this bit is set and the force pause ability bit is not set, pause ability is enabled only if the auto-negotiation process determines that the external phy ? s link partner supports ieee 802.3 flow control. when pause ability is enabled, the receipt of a mac control pause frame causes the device to stop transmitting for a time period that is determined by the contents of the pause frame. if a logical 1 is written to this bit position, the corresponding bit in the register will be loaded with the contents of the val2 bit. if a logical 0 is written to this bit position, the corresponding bit in the register will not be altered. 18 fixp fixed length pause. when this bit is set to 1, all mac control pause frames transmitted from the device will contain a request_operand field that is copied from the pause_len field of this register. when this bit is cleared to 0, a pause frame with its request_operand field set to 0ffffh will be sent when the fccmd bit in this register is changed from 0 to 1 or when the signal on the fc pin changes from 0 to 1 while the fcpen bit has the value 1. also a pause frame with its request_operand field set to 0000h will be sent when the fccmd bit in this register is changed from 1 to 0 or when the signal on the fc pin changes from 1 to 0 while the fcpen bit has the value 1. if a logical 1 is written to this bit position, the corresponding bit in the register will be loaded with the contents of the val2 bit. if a logical 0 is written to this bit position, the corresponding bit in the register will not be altered. 17 fcpen flow control pin enable. when the value of this bit is 1, mac control pause frames will be transmitted or half-duplex back pressure will be applied when the fc pin is asserted. when the value of this bit is 0, the state of the fc pin is ignored. if a logical 1 is written to this bit position, the corresponding bit in the register will be loaded with the contents of the val2 bit. if a logical 0 is written to this bit position, the corresponding bit in the register will not be altered. 152 am79c976 8/01/00 preliminary ?-!'( 0 offset 18ch the contents of this register are set to 3ch when the rst pin is asserted, before the serial eeprom is read, and after a serial eeprom read error. table 58. ifs1: inter-frame spacing part 1 register 16 fccmd flow control command. in full-duplex mode this bit allows the host cpu to cause a pause frame to be sent by issuing a single command. in half-duplex mode, setting this bit puts the device into back-pressure mode, which has the effect of forcing the remote transmitter to delay transmissions while the local system is freeing up congested resources. if the device is operating in full-duplex mode and the value of the fixp bit is 1, when fccmd is changed from 0 to 1, a pause frame is sent with its request_operand field copied from the pause_len field of this register. after the pause frame is sent, the fccmd bit is automatically reset to 0. if the device is operating in full-duplex mode and the value of the fixp bit is 0, when fccmd is changed from 0 to 1, a pause frame is sent with its request_operand field filled with all 1s, and the fccmd bit is not automatically reset to 0. when fccmd is changed from 1 to 0, a pause frame is sent with its request_operand field filled with all 0s. if the device is operating in half-duplex mode, setting fccmd to 1 puts the mac into back-pressure mode. in back-pressure mode, whenever the mac detects receiver activity, it transmits a series of alternating 1s and 0s to force a collision. if a logical 1 is written to this bit position, the corresponding bit in the register will be loaded with the contents of the val2 bit. if a logical 0 is written to this bit position, the corresponding bit in the register will not be altered. 15-0 pause_len pause length. the contents of this field are copied into the request_operand fields of mac control pause frames that are transmitted while the fixp bit in this register is set to 1. bit name description bit name description 7-0 ifs1 interframespacingpart1. changing ifs1 allows the user to program the value of the interframe- spacepart1 timing. the am79c976 controller sets the default value at 60 bit times (3ch). see the subsection on medium allocation in the section media access management for more details. the equation for setting ifs1 when ipg 96 bit times is: ifs1 = ipg - 36 bit times ipg should be programmed to the nearest nibble. the two least significant bits are ignored. for example, programming ipg to 63h has the same effect as programming it to 60h. this register is an alias for csr125, bits [7:0]. 8/01/00 am79c976 153 preliminary int0: interrupt0 offset 038h int0 identifies the source or sources of an interrupt. with the exception of intr, all bits in this register are ? write 1 to clear ? so that the cpu can clear the interrupt condition by reading the register and then writing back the same data that it read. writing a 0 to a bit in this reg- ister has no effect. all bits in this register are cleared to 0 by h_reset. in addition, tint, txdnint, txstrtint, and rint are cleared when the run bit in cmd0 is cleared. table 59. int0: interrupt0 register bit name description 31 intr interrupt summary. this bit indicates that one or more of the other interrupt bits in this register are set and the associated enable bit or bits in inten0 are also set. if intren in cmd0 is set to 1 and intr is set, inta will be active. when intr is set by sint, inta will be active independent of the state of inea. intr is read only. intr is cleared by clearing all of the active individual interrupt bits that have not been masked out. 31-28 res reserved locations. written as zeros and read as undefined. 27 lcint link change interrupt. this bit is set when the port manager detects a change in the link status of the external phy. 26 apint5 auto-poll interrupt from register 5. this bit is set when the auto-poll state machine has detected a change in the external phy register whose address is stored in auto-poll register 5. 25 apint4 auto-poll interrupt from register 4. this bit is set when the auto-poll state machine has detected a change in the external phy register whose address is stored in auto-poll register 4. 24 apint3 auto-poll interrupt from register 3. this bit is set when the auto-poll state machine has detected a change in the external phy register whose address is stored in auto-poll register 3. 23 res reserved locations. written as zeros and read as undefined. 22 apint2 auto-poll interrupt from register 2. this bit is set when the auto-poll state machine has detected a change in the external phy register whose address is stored in auto-poll register 2. 21 apint1 auto-poll interrupt from register 1. this bit is set when the auto-poll state machine has detected a change in the external phy register whose address is stored in auto-poll register 1. 20 apint0 auto-poll interrupt from register 0. this bit is set when the auto-poll state machine has detected a change in the external phy register whose address is stored in auto-poll register 0. 19 miipdtint mii phy detect transition interrupt. the mii phy detect transition interrupt is set by the am79c976 controller whenever the miipd bit in stat0 transitions from 0 to 1 or vice versa. this bit is an alias of csr7, bit 1. 18 mcciint mii management command complete internal interrupt. the mii management command complete interrupt is set by the am79c976 controller when a read or write operation on the mii management port is complete from an internal operation. examples of internal operations are auto- poll or network port manager generated mii management frames. this bit is an alias of csr7, bit 3. 17 mccint mii management command complete interrupt. the mii management command complete interrupt is set by the am79c976 controller when a read or write operation to the mii data port (phy access register) is complete. this bit is an alias of csr7, bit 5. 154 am79c976 8/01/00 preliminary 16 mreint mii management read error interrupt. the mii read error interrupt is set by the am79c976 controller to indicate that the currently read register from the external phy is invalid. the contents of the phy access register are incorrect and that the operation should be performed again. the indication of an incorrect read comes from the phy. during the read turnaround time of the mii management frame the external phy should drive the mdio pin to a low state. if this does not happen, it indicates that the phy and the am79c976 controller have lost synchronization. this bit is an alias of csr7, bit 9 15 res reserved locations. written as zeros and read as undefined. 14 spndint suspend interrupt. this bit is set when a receiver or transmitter suspend operation has finished. 13 mpint magic packet interrupt. magic packet interrupt is set by the am79c976 controller when the device is in the magic packet mode and the am79c976 controller receives a magic packet frame. this bit is an alias of csr5, bit 4. 12 sint system interrupt is set by the am79c976 controller when it detects a system error during a bus master transfer on the pci bus. system errors are data parity error, master abort, or a target abort. the setting of sint due to data parity error is not dependent on the setting of perren (pci command register, bit 6). note that because inea is cleared by the stop reset generated by the system error, the system interrupt bypasses the global interrupt enable bits inea and intren. this means that if sinten in inten0 or sinte in csr5 is set to 1, inta will be asserted when sint is 1 regardless of the state of inea and intren. the state of sint is not affected by clearing any of the pci status register bits that get set when a data parity error (dataperr, bit 8), master abort (rmabort, bit 13), or target abort (rtabort, bit 12) occurs. this bit is an alias of csr5, bit 11. 11-9 res reserved locations. written as zeros and read as undefined. 8tint transmit interrupt is set by the am79c976 controller after the own bit in the last descriptor of a transmit frame has been cleared to indicate the frame has been copied to the transmit fifo. this bit is an alias of csr0, bit 9. 7uint user interrupt. uint is set by the am79c976 controller after the host has issued a user interrupt command by setting uintcmd in the cmd0 register. this bit is an alias of csr4, bit 6. 6 txdnint transmission done interrupt. this bit is set when the transmitter has finished sending a frame. this bit is included for debugging purposes. 5 txstrtint transmit start interrupt. this bit is set when the transmitter begins the transmission of a frame. this bit is included for debugging purposes. this bit is an alias of csr4, bit 3. 4stint software timer interrupt. the software timer interrupt is set by the am79c976 controller when the software timer counts down to 0. the software timer will immediately load the contents of the software timer value register, stval, into the software timer and begin counting down. this bit is an alias of csr7, bit 11. 3-1 res reserved locations. written as zeros and read as undefined. 0rint receive interrupt is set by the am79c976 controller after the last descriptor of a receive frame has been updated by writing a 0 to the ownership bit. rint may also be set when the first descriptor of a receive frame has been updated by writing a 0 to the ownership bit if the lappen bit in cmd2 has been set to a 1. this bit is an alias of csr0, bit 10. bit name description 8/01/00 am79c976 155 preliminary inten0: interrupt0 enable offset 040h this register allows the software to specify which types of interrupt events will cause the intr bit in the interrupt0 register to be set, which in turn will cause inta pin to be asserted if the intren bit in cmd0 is set. each bit in this register corresponds to a bit in the interrupt0 register. setting a bit in this register enables the corresponding bit in the interrupt0 register to cause the intr bit to be set. inten0 is a command style register. the high order bit of each byte of this register is a ? value ? bit that specifies the value that will be written to selected bits of the reg- ister. the seven low order bits of each byte make up a bit map that selects which register bits will be altered. all bits in this register are cleared to 0 by h_reset. all bits are also cleared before eeprom data are loaded or after an eeprom read failure. the rinten and tinten bits are set after s_reset (but not h_reset). table 60. inten0: interrupt0 enable register bit name description 31 val3 value bit for byte 3. the value of this bit is written to any bits in the inten0 register that correspond to bits in the inten0[30:24] bit map field that are set to 1. 30-28 res reserved locations. written as zeros and read as undefined. 27 lcinten link change interrupt enable. when this bit is set, the intr bit will be set when the lcint bit in int0 is set. 26 apint5en auto-poll interrupt from register 5 enable. when this bit is set, the intr bit will be set when the apint5 bit in int0 is set. 25 apint4en auto-poll interrupt from register 4 enable. when this bit is set, the intr bit will be set when the apint4 bit in int0 is set. 24 apint3en auto-poll interrupt from register 3 enable. when this bit is set, the intr bit will be set when the apint3 bit in int0 is set. 23 val2 value bit for byte 2. the value of this bit is written to any bits in the inten0 register that correspond to bits in the inten0[22:16] bit map field that are set to 1. 22 apint2en auto-poll interrupt from register 2 enable. when this bit is set, the intr bit will be set when the apint2 bit in int0 is set. 21 apint1en auto-poll interrupt from register 1 enable. when this bit is set, the intr bit will be set when the apint1 bit in int0 is set. 20 apint0en auto-poll interrupt from register 0 enable. when this bit is set, the intr bit will be set when the apint0 bit in int0 is set. 19 miipdtinten mii phy detect transition interrupt enable. when this bit is set, the intr bit will be set when the miipdtint bit in int0 is set. this bit is an alias of csr7, bit 0. 18 mcciinten mii management command complete internal interrupt enable. when this bit is set, the intr bit will be set when the mcciint bit in int0 is set. this bit is an alias of csr7, bit 2. 17 mccinten mii management command complete interrupt enable. when this bit is set, the intr bit will be set when the mccint bit in int0 is set. this bit is an alias of csr7, bit 4. 16 mreinten mii management read error interrupt enable. when this bit is set, the intr bit will be set when the mreint bit in int0 is set. this bit is an alias of csr7, bit 8 15 val1 value bit for byte 1. the value of this bit is written to any bits in the inten0 register that correspond to bits in the inten0[14:8] bit map field that are set to 1. 14 spndinten suspend interrupt enable. when this bit is set, the intr bit will be set when the spndint bit in int0 is set. 156 am79c976 8/01/00 preliminary 13 mpinten magic packet interrupt enable. when this bit is set, the intr bit will be set when the mpint bit in int0 is set. this bit is an alias of csr5, bit 3. 12 sinten system interrupt enable. when this bit is set, the intr bit will be set when the sint bit in int0 is set. this bit is an alias of csr5, bit 10. 11-9 res reserved locations. written as zeros and read as undefined. 8tinten transmit interrupt enable. when this bit is set, the intr bit will be set when the tint bit in int0 is set. this bit is an alias of csr3, bit 9 with reversed polarity. (when tintm in csr3 is set, the transmit interrupt is disabled.) previous devices in the pcnet family enable receive and transmit interrupts following reset. the am79c976 controller disables these interrupts following h_reset (but not s_reset). for compatibility with legacy software, the am79c976 controller will set rinten and tinten following s_reset. if, in addition, the user programs the eeprom to load ones into rinten and tinten, these interrupts will also be enabled after h_reset. this matches the behavior of the previous pcnet devices. 7val1 value bit for byte 1. the value of this bit is written to any bits in the inten0 register that correspond to bits in the inten0[6:0] bit map field that are set to 1. 6 txdninten transmission done interrupt enable. when this bit is set, the intr bit will be set when the txdnint bit in int0 is set. this bit is an alias of csr5, bit 12. 5 txstrtinten transmit start interrupt enable. when this bit is set, the intr bit will be set when the txstrtint bit in int0 is set. this bit is an alias of csr4, bit 2. 4stinten software timer interrupt enable. when this bit is set, the intr bit will be set when the stint bit in int0 is set. this bit is an alias of csr7, bit 10. 3-1 res reserved locations. written as zeros and read as undefined. 0rinten receive interrupt enable. when this bit is set, the intr bit will be set when the rint bit in int0 is set. this bit is an alias of csr3, bit 10 with reversed polarity. (when rintm in csr3 is set, the receive interrupt is disabled.) previous devices in the pcnet family enable receive and transmit interrupts following reset. the am79c976 controller disables these interrupts following h_reset (but not s_reset). for compatibility with legacy software, the am79c976 controller will set rinten and tinten following s_reset. if, in addition, the user programs the eeprom to load ones into rinten and tinten, these interrupts will also be enabled after h_reset. this matches the behavior of the previous pcnet devices. bit name description 8/01/00 am79c976 157 preliminary ipg: inter-packet gap register offset 18dh the contents of this register are set to 60h when the rst pin is asserted, before the serial eeprom is read, and after a serial eeprom read error. table 61. ipg: inter-packet gap register <*?< ( offset 168h the contents of this register are cleared to 0 when the rst pin is asserted. this register is not cleared by the serial eeprom read operation or by a serial eeprom read error. table 62. logical address filter register bit name description 7-0 ipg inter packet gap. this value indicates the minimum number of network bit times after the end of a frame that the transmitter will wait before it starts transmitting another frame. in half-duplex mode the end of the frame is determined by crs, while in full-duplex mode the end of the frame is determined by tx_en. the ipg value can be adjusted to compensate for delays through the external phy device. ipg should be programmed to the nearest nibble. the two least significant bits are ignored. for example, programming ipg to 63h has the same effect as programming it to 60h. caution : use this parameter with care. by lowering the ipg below the ieee 802.3 standard 96 bit times, the am79c976 controller can interrupt normal network behavior. this register is an alias for csr125, bits [15:8]. bit name description 63-0 ladrf logical address filter, ladrf[63:0]. this register contains a 64-bit mask that is used to accept incoming logical (or multicast) addresses. if the first bit in the incoming address (as transmitted on the wire) is a 1, the destination address is a logical address. a logical address is passed through the crc generator to produce a 32-bit result. the high order 6 bits of this result are used to select one of the 64-bit positions in the logical address filter. if the selected filter bit is set, the address is accepted, and the frame is copied into host system memory. the logical address filter is used in multicast addressing schemes. the acceptance of the incoming frame based on the filter value indicates that the message may be intended for the node. it is the responsibility of the host cpu to compare the destination address of the stored message with a list of acceptable multicast addresses to determine whether or not the message is actually intended for the node. the contents of this register should be loaded from eeprom. this register can also be loaded from the initialization block after the init bit in csr0 has been set. this register is an alias for csr8, csr9, csr10, and csr11. 158 am79c976 8/01/00 preliminary led0 control register offset 0e0h this register controls the function(s) that the led0 pin displays. multiple functions can be simultaneously en- abled on this led pin. the led display will indicate the logical or of the enabled functions. this register de- faults to link status (lnkst) with pulse stretcher en- abled (pse = 1) and is fully programmable. all bits in this register are restored to their default val- ues when the rst pin is asserted, before the serial eeprom is read, and after a serial eeprom read er- ror. this register is an alias of bcr4. table 63. led0 control register bit name description 15 ledout this bit indicates the current (non-stretched) value of the led output pin. a value of 1 in this bit indicates that the or of the enabled signals is true. the logical value of the ledout status signal is determined by the settings of the individual status enable bits of the led register (bits 8 and 6-0). 14 ledpol led polarity. when this bit has the value 0, then the led pin will be driven to a low level whenever the or of the enabled signals is true, and the led pin will be disabled and allowed to float high whenever the or of the enabled signals is false (i.e., the led output will be an open drain output and the output value will be the inverse of the ledout status bit). when this bit has the value 1, then the led pin will be driven to a high level whenever the or of the enabled signals is true, and the led pin will be driven to a low level whenever the or of the enabled signals is false (i.e., the led output will be a totem pole output and the output value will be the same polarity as the ledout status bit.). the setting of this bit will not effect the polarity of the ledout bit for this register. the default value of this bit is 0. 13 leddis led disable. this bit is used to disable the led output. when leddis has the value 1, then the led output will always be disabled. when leddis has the value 0, then the led output value will be governed by the ledout and ledpol values. the default value of this bit is 0. 12 100e 100 mbps enable. when this bit is set to 1, a value of 1 is passed to the ledout bit in this register when the am79c976 controller is operating in 100 mbps mode. the default value of this bit is 0. 11-10 res reserved locations. written and read as undefined. 9 mpse magic packet status enable. when this bit is set to 1, a value of 1 is passed to the ledout bit in this register when magic packet frame mode is enabled and a magic packet frame is detected on the network. the default value of this bit is 0. 8fdlse full-duplex link status enable. indicates the full-duplex link test status. when this bit is set, a value of 1 is passed to the ledout signal when the am79c976 controller is functioning in a link pass state and full-duplex operation is enabled. when the am79c976 controller is not functioning in a link pass state with full-duplex operation being enabled, a value of 0 is passed to the ledout signal. the default value of this bit is 0. 7 pse pulse stretcher enable. when this bit is set, the led illumination time is extended for each new occurrence of the enabled function for this led output. a value of 0 disables the pulse stretcher. the default value of this bit is 1. 6 lnkse link status enable. when this bit is set, a value of 1 will be passed to the ledout bit in this register when in link pass state. the default value of this bit is 1. 8/01/00 am79c976 159 preliminary <%* offset 0e2h this register controls the function(s) that the led1 pin displays. multiple functions can be simultaneously en- abled on this led pin. the led display will indicate the logical or of the enabled functions. this register de- faults to transmit or receive activity (xmte = 1 and rcve = 1) with pulse stretcher enabled (pse = 1) and is fully programmable. all bits in this register are restored to their default val- ues when the rst pin is asserted, before the serial eeprom is read, and after a serial eeprom read er- ror. this register is an alias of bcr5. the functions of the bits in this register are identical to those of the led0 control register, except that for this register the default value for the xmte, rcve, and pse bits is 1, and the default value for all other bits is 0. <%* offset 0e4h this register controls the function(s) that the led2 pin displays. multiple functions can be simultaneously en- abled on this led pin. the led display will indicate the logical or of the enabled functions. this register de- faults to 100 mb/s speed indication (100e = 1) with pulse stretcher enabled (pse = 1) and is fully program- mable. all bits in this register are restored to their default val- ues when the rst pin is asserted, before the serial eeprom is read, and after a serial eeprom read error. this register is an alias of bcr6. the functions of the bits in this register are identical to those of the led0 control register, except that for this register the default value for the 100e and pse bits is 1, and the default value for all other bits is 0. <%* offset 0e6h this register controls the function(s) that the led3 pin displays. multiple functions can be simultaneously en- abled on this led pin. the led display will indicate the logical or of the enabled functions. this register de- faults to collision indication (cole = 1) with pulse stretcher enabled (pse = 1) and is fully programmable. all bits in this register are restored to their default val- ues when the rst pin is asserted, before the serial eeprom is read, and after a serial eeprom read er- ror. this register is an alias of bcr7. the functions of the bits in this register are identical to those of the led0 control register, except that for this register the default value for the cole and pse bits is 1, and the default value for all other bits is 0. 5 rcvme receive match status enable. when this bit is set, a value of 1 is passed to the ledout bit in this register when there is receive activity on the network that has passed the address match function for this node. all address matching modes are included: physical, logical filtering, broadcast and promiscuous. the default value of this bit is 0. 4xmte transmit status enable. when this bit is set, a value of 1 is passed to the ledout bit in this register when there is transmit activity on the network. the default value of this bit is 0. 3 res reserved location. written and read as undefined. 2 rcve receive status enable. when this bit is set, a value of 1 is passed to the ledout bit in this register when there is receive activity on the network. the default value of this bit is 0. 1sfbde start frame/byte delimiter enable. when this bit is set, a value of 1 is passed to the ledout bit in this register when the rxd[3:0] pins are presenting the least significant nibble of valid frame data. the default value of this bit is 0. 0cole collision status enable. when this bit is set, a value of 1 is passed to the ledout bit in this register when there is collision activity on the network. the default value of this bit is 0. bit name description 160 am79c976 8/01/00 preliminary max_lat_a: pci maximum latency alias register offset 1b1h this register is a writable alias of the maximum latency field at offset 3fh in pci configuration space, which is read only. the purpose of this register is to allow the pci maximum latency value to be loaded from the se- rial eeprom. the contents of this register are set to 18h when the rst pin is asserted, before the serial eeprom is read, and after a serial eeprom read error. table 64. max_lat_a: pci maximum latency alias register # @9 @?0# !!9 offset 1b0h this register is a writable alias of the minimum grant field at offset 3eh in pci configuration space, which is read only. the purpose of this register is to allow the pci minimum grant value to be loaded from the serial eeprom. the contents of this register are set to 18h when the rst pin is asserted, before the serial eeprom is read, and after a serial eeprom read error. table 65. min_gnt_a: pci minimum grant alias register 0*?0+$ ( offset 160h the contents of this register are cleared to 0 when the rst pin is asserted. this register is not cleared by the serial eeprom read operation or by a serial eeprom read error. bit name description 7-0 max_lat maximum latency. specifies the maximum arbitration latency the am79c976 controller can sustain without causing problems to the network activity. the register value specifies the time in units of 1/4 microseconds. max_lat is aliased to the pci configuration space register max_lat (offset 3fh). the host will use the value in the register to determine the setting of the am79c976 latency timer register. the default value for max_lat is 18h which corresponds to 6 s. this register is an alias of bcr22, bits [15:8] and of offset 3fh in pci configuration space. bit name description 7-0 min_gnt minimum grant. specifies the minimum length of a burst period the am79c976 controller needs to keep up with the network activity. the length of the burst period is calculated assuming a clock rate of 33 mhz. the register value specifies the time in units of 1/4 s. min_gnt is aliased to the pci configuration space register min_gnt (offset 3eh). the host will use the value in the register to determine the setting of the am79c976 latency timer register. the default value for min_gnt is 18h which corresponds to 6 s. this register is an alias of bcr22, bits [7:0] and of offset 3eh in pci configuration space. 8/01/00 am79c976 161 preliminary table 66. padr: physical address register 0 offset 0deh all bits in this register are cleared to 0 when the rst pin is asserted, before the serial eeprom is read, and after a serial eeprom read error. this register is read- only. table 67. pause_cnt: pause count register 0* 4?0* b offset 1bch this register contains the data that appears in the data_scale field of the pci power management control/status register (pmcsr) and the pci data register when the data_sel field of pmcsr is set to 0. since the data_scale and data fields in the con- figuration space are read only, this register provides a means of programming them indirectly, normally by loading them from the serial eeprom. this register is an alias of bcr37. the contents of this register are cleared to 0 when the rst pin is asserted, before the serial eeprom is read, and after a serial eeprom read error. table 68. pcidata0: pci data register zero alias register 0* ?0* offset 1beh this register is identical to the pci data register zero alias register except that it contains the data that ap- pears in the data_scale field of the pci power man- agement control/status register (pmcsr) and the pci data register when the data_sel field of pmcsr is set to 1. bit name description 47-0 padr mac physical address, padr[47:0]. this register contains 48-bit, globally unique station address assigned to this device. if the least significant bit of the first byte of a received frame is 0, the destination address of the frame is a unicast address, which will be compared with the contents of the padr. if this bit is 0 and the frame ? s destination address exactly matches the contents of padr, the frame is accepted and copied into the host system memory. the byte order is such that padr7[7:0] corresponds to the first address byte transferred over the network. unicast address matching can be disabled by setting the disable receive physical address bit (dcrvpa, bit 18 in cmd2). if drcvpa is set to 1, a match of a frame ? s destination address with the contents of padr will not cause the frame to be accepted and copied into the host memory. the contents of this register should be loaded from eeprom. this register can also be loaded from the initialization block after the init bit in csr0 has been set. this register is an alias for csr12, csr13, and csr14. bit name description 31-16 res reserved locations. written as zeros and read as undefined 15-0 pause_cnt pause count. this field indicates the pause time parameter that was contained in the request_operand field of the most recently received mac control pause frame. bit name description 15-10 res reserved locations. written as zeros and read as undefined. 9-8 d0_scale these bits correspond to the data_scale field of the pmcsr (offset register 44 of the pci configuration space, bits 14-13). refer to the description of data_scale for the meaning of this field. 7-0 data0 these bits correspond to the pci data register (offset register 47 of the pci configuration space, bits 7-0). refer to the description of data register for the meaning of this field. 162 am79c976 8/01/00 preliminary this register is an alias of bcr38. the contents of this register are cleared to 0 when the rst pin is asserted, before the serial eeprom is read, and after a serial eeprom read error. 0* ?0* 8 offset 1c0h this register is identical to the pci data register zero alias register except that it contains the data that ap- pears in the data_scale field of the pci power man- agement control/status register (pmcsr) and the pci data register when the data_sel field of pmcsr is set to 2. this register is an alias of bcr39. the contents of this register are cleared to 0 when the rst pin is asserted, before the serial eeprom is read, and after a serial eeprom read error. 0* ?0* + offset 1c2h this register is identical to the pci data register zero alias register except that it contains the data that ap- pears in the data_scale field of the pci power man- agement control/status register (pmcsr) and the pci data register when the data_sel field of pmcsr is set to 3. this register is an alias of bcr40. the contents of this register are cleared to 0 when the rst pin is asserted, before the serial eeprom is read, and after a serial eeprom read error. 0* "?0* offset 1c4h this register is identical to the pci data register zero alias register except that it contains the data that ap- pears in the data_scale field of the pci power man- agement control/status register (pmcsr) and the pci data register when the data_sel field of pmcsr is set to 4. this register is an alias of bcr41. the contents of this register are cleared to 0 when the rst pin is asserted, before the serial eeprom is read, and after a serial eeprom read error. 0* )?0* offset 1c6h this register is identical to the pci data register zero alias register except that it contains the data that ap- pears in the data_scale field of the pci power man- agement control/status register (pmcsr) and the pci data register when the data_sel field of pmcsr is set to 5. this register is an alias of bcr42. the contents of this register are cleared to 0 when the rst pin is asserted, before the serial eeprom is read, and after a serial eeprom read error. 0* ,?0* & offset 1c8h this register is identical to the pci data register zero alias register except that it contains the data that ap- pears in the data_scale field of the pci power man- agement control/status register (pmcsr) and the pci data register when the data_sel field of pmcsr is set to 6. this register is an alias of bcr43. the contents of this register are cleared to 0 when the rst pin is asserted, before the serial eeprom is read, and after a serial eeprom read error. 0* /?0* offset 1cah this register is identical to the pci data register zero alias register except that it contains the data that ap- pears in the data_scale field of the pci power man- agement control/status register (pmcsr) and the pci data register when the data_sel field of pmcsr is set to 7. this register is an alias of bcr44. the contents of this register are cleared to 0 when the rst pin is asserted, before the serial eeprom is read, and after a serial eeprom read error. 8/01/00 am79c976 163 preliminary phy access register offset 0d0h this register gives the host cpu indirect access to the mii management bus (mdc/mdio). through this reg- ister the host cpu can read or write any external phy register that is accessible through the mii management bus. all bits in this register are cleared to 0 when the rst pin is asserted. this register is not affected by the serial eeprom read operation or by a serial eeprom read error. table 69. phy_access: phy access register bit name description 31 phy_cmd_done phy command complete. this read-only bit is set to 0 after a write access to this register and remains 0 until the end of the mii management frame that is generated by the write access. when the value of this bit is 1, the phy_data field contains valid data. 30 phy_wr_cmd phy write command. when this bit is set, an mii management frame will be sent to write the contents of the phy_data field to the external phy register addressed by the phy_addr and phy_reg_addr fields. this bit must not be set at the same time that the phy_blk_rd_cmd bit or the phy_nblk_rd_cmd bit is set. 29 phy_blk_rd_cmd phy blocking read command. when the bit is set, an mii management frame will be sent to read the contents of the phy_data field to the external phy register addressed by the phy_addr and phy_reg_addr fields. after this bit is set, the next attempt to read this register will cause pci bus retries to occur until the phy_data field has been updated with data read from the selected phy register. this bit must not be set at the same time that the phy_wr_cmd bit or the phy_nblk_rd_cmd bit is set. 28 phy_nblk_rd_cm d phy non-blocking read command. when the bit is set, an mii management frame will be sent to read the contents of the phy_data field to the external phy register addressed by the phy_addr and phy_reg_addr fields. after this bit is set, the host cpu can read this register again and again until the phy_cmd_done bit returns the value 1, indicating that the phy_data field contains valid data read from the selected phy register. alternatively, the host cpu can wait for the mccint interrupt (int0, bit 17). this bit must not be set at the same time that the phy_wr_cmd bit or the phy_blk_rd_cmd bit is set. 27 phy_pre_sup preamble suppression. if this bit is set, the mii management frame will be sent without a preamble. before setting this bit the host cpu must make sure that the external phy addressed by the phy_addr field is capable of accepting mii management frames without preambles. 26 res reserved location. written as zero and read as undefined. 25-21 phy_addr phy address. the address of the external phy device to be accessed. 20-16 phy_reg_addr phy register address. the address of the register in the external phy device to be accessed. 15-0 phy_data phy data. data written to or read from the external phy register specified by phy_addr and phy_reg_addr. 164 am79c976 8/01/00 preliminary pmat0: onnow pattern register 0 offset 190h this register is used to control and indirectly access the pattern match ram (pmr). when the pmat_mode bit (cmd7, bit3) is 1, pattern match logic is enabled. no bus accesses into pmr are possible, and pmat0 and pmat1 are ignored. when pmat_mode is set, a read of pmat0 or pmat1 returns all undefined bits. when the pmat_mode bit (cmd7, bit3) is 0, the pat- tern match logic is disabled and accesses to the pmr are possible. bits 6-0 of pmat0 specify the address of the pmr word to be accessed. following the write to pmat0, the pmr word may be read by reading pmat1 and the high order bytes of pmat0 in any order. to write to pmr word, the write to pmat0 must be fol- lowed by a write to pmat1 to complete the operation. the ram will not actually be written until the write to pmat1 is complete. the write to pmat1 causes all 5 bytes (two bytes of pmat1 and the upper three bytes of pmat0) to be written to whatever pmr word is ad- dressed by bits 6:0 of pmat0. the contents of this register are cleared to 0 when the rst pin is asserted. the register is not cleared at the start of a serial eeprom read operation or after a se- rial eeprom read error. table 70. pmat0: onnow pattern register 0 0# ? 80 offset 194h this register is used to control and indirectly access the pattern match ram (pmr). when the pmat_mode bit (cmd7, bit3) is 1, pattern match logic is enabled. no bus accesses into pmr are possible, and pmat0 and pmat1 are ignored. when pmat_mode is set, a read of pmat0 or pmat1 returns all undefined bits. when the pmat_mode bit (cmd7, bit3) is 0, the pat- tern match logic is disabled and accesses to the pmr are possible. bits 6-0 of pmat0 specify the address of the pmr word to be accessed. following the write to pmat0, the pmr word may be read by reading pmat1 and the high order bytes of pmat0 in any order. to write to pmr word, the write to pmat0 must be fol- lowed by a write to pmat1 to complete the operation. the ram will not actually be written until the write to pmat1 is complete. the write to pmat1 causes all 5 bytes (two bytes of pmat1 and the upper three bytes of pmat0) to be written to whatever pmr word is ad- dressed by bits 6:0 of pmat0. the contents of this register are cleared to 0 when the rst pin is asserted. the register is not cleared at the start of a serial eeprom read operation or after a se- rial eeprom read error. table 71. pmat1: onnow pattern register 1 bit name description 31-24 pmr_b2 pattern match ram byte 2. this byte is written into or read from byte 2 of the pattern match ram. this field is an alias of bcr46, bits [15:8]. 23-16 pmr_b1 pattern match ram byte 1. this byte is written into or read from byte 1 of the pattern match ram. this field is an alias of bcr46, bits [7:0]. 15-8 pmr_b0 pattern match ram byte 0. this byte is written into or read from byte 0 of the pattern match ram. this field is an alias of bcr45, bits [15:8]. 7 res reserved location. written as zero and read as undefined. 6-0 pmr_addr pattern match ram address. these bits are the pattern match ram address to be written to or read from. bit name description 15-8 pmr_b4 pattern match ram byte 4. this byte is written into or read from byte 4 of the pattern match ram. this field is an alias of bcr47, bits [15:8]. 7-0 pmr_b3 pattern match ram byte 3. this byte is written into or read from byte 3 of the pattern match ram. this field is an alias of bcr47, bits [7:0]. 8/01/00 am79c976 165 preliminary 0#@?008# !'5 offset 1b8h this register is an alias of the pmc register located at offset 42h of the pci configuration space. since the pmc register is read only, this register provides a means of programming it through the eeprom. for the definition of the bits in this register, refer to the pmc register definition. the contents of this register are set to the default value of 0c802h when the rst pin is asserted, before the serial eeprom is read, and after a serial eeprom read error. ( 0( offset 0dch the contents of this register are set to the default value 64 when the rst pin is asserted. this register is not af- fected by the serial eeprom read operation or by a se- rial eeprom read error. table 72. receive protect register =@ 9@<% ?( < + offset 150h the contents of this register are set to the default value 0 when the rst pin is asserted. this register is not af- fected by the serial eeprom read operation or by a serial eeprom read error. table 73. rcv_ring_len: receive ring length register bit name description 15-0 rcv_ protect receive protect. this register indicates the number of bytes of an incoming frame that must be received before the dma controller starts to copy the frame data into the host system memory. if the size of the frame (in bytes) is less than the contents of this register and the frame contains a valid fcs, the dma transfer can start any time after the end of the frame is received. the receive protect register also determines the period during which the external address reject (ear ) pin is monitored when the external address detection interface (eadi) is used. the state of the ear pin is ignored except for a period of time that starts when the start of frame delimiter of an incoming frame is received and ends when the number of frame data bytes indicated by the receive protect register have been received. bit name description 15-0 rcv_ring_ len receive ring length. contains the two ? s complement of the receive descriptor ring length. this register is initialized during the optional am79c976 controller initialization routine based on the value in the rlen field of the initialization block. however, this register can be manually altered. the actual receive ring length is defined by the current value in this register. the ring length can be defined as any value from 1 to 65535. this register is an alias of csr76. 166 am79c976 8/01/00 preliminary rom_cfg: rom base address configuration register offset 18eh this register, which should normally be loaded from the serial eeprom, determines which bits in the expan- sion rom base address register (rombase) in pci configuration space can be altered by pci configura- tion space write accesses. therefore this register indi- rectly determines the amount of pci memory space that the am79c976 device will claim for the pci expan- sion rom. the contents of this register are cleared to 0 when the rst pin is asserted, before the serial eeprom is read, and after a serial eeprom read error. table 74. rom_cfg: rom base address configuration register *@?05 $ !* offset 1b4h this register is a writable alias of the subsystem id field at offset 2eh in pci configuration space, which is read only. the purpose of this register is to allow the pci subsystem vendor id value to be loaded from the serial eeprom. the contents of this register are cleared to 0 when the rst pin is asserted, before the serial eeprom is read, and after a serial eeprom read error. table 75. sid_a: pci subsystem id alias register bit name description 15-3 rombase [23:11] this field contains write enable bits for bits [23:11] of the expansion rom base address register (rombase) in pci configuration space. if a bit in this field is set to 1, the corresponding bit in the rombase register can be written by pci configuration space accesses. if a bit in this field is cleared to 0, the corresponding bit in the rombase register will be fixed at 0, and can not be altered by pci configuration space accesses. bits 15-3 of this field correspond to bits 23-11 of the rombase register. 2-1 res reserved locations. written as zeros; read as undefined. 0 rombase[0] this bit is the write enable bit for bit [0] of the expansion rom base address register (rombase) in pci configuration space. if this bit is set to 1, the expansion rom enable bit in the rombase register can be written by pci configuration space accesses. if a bit in this field is cleared to 0, the expansion rom enable bit in the rombase register will be fixed at 0, and can not be altered by pci configuration space accesses. this bit should be set to 1, normally by the eeprom read operation, if an expansion rom is present in the system. it should be cleared to 0 (the default state) if there is no expansion rom in the system. bit name description 15-0 sid subsystem id. sid is used together with svid (bcr23, bits 15-0) to uniquely identify the add-in board or subsystem the am79c976 controller is used in. the value of sid is determined by the system vendor. a value of 0 (the default) indicates that the am79c976 controller does not support subsystem identification. this register is an alias of bcr24 and of the pci configuration space subsystem id field at offset 2eh. 8/01/00 am79c976 167 preliminary sram boundary register offset 17ah all bits in this register are cleared to 0 when the rst pin is asserted, before the serial eeprom is read, and after a serial eeprom read error. table 76. sram boundary register # 6 offset 178h all bits in this register are cleared to 0 when the rst pin is asserted, before the serial eeprom is read, and after a serial eeprom read error. table 77. sram size register bit name description 15-0 sram_bnd sram boundary. specifies the size of the transmit buffer portion of the sram in units of 512-byte pages. for example, if sram_bnd is set to 10, then 5120 bytes of the sram will be allocated for the transmit buffer and the rest will be allocated for the receive buffer. the transmit buffer in the sram begins at address 0 and ends at the address (sram_bnd*512)- 1. therefore, the receive buffer always begins on a 512-byte boundary. sram_bnd must be initialized to an appropriate value, either by the eeprom or by the host cpu. sram_bnd must be set to a value less than or equal to iffch. values larger than iffch will cause incorrect behavior. note : the minimum allowed number of pages for normal network operation is four, and the maximum is sram_size - 4. this register is an alias of bcr26. bit name description 15-0 sram_size sram size. specifies the total size of the ssram buffer in units of 512-byte pages. for example, assume that the external memory consists of one 64k x 32 bit ssram, for a total of 256k bytes. in this case sram_size should be set to 512 (256k divided by 512). this field must be initialized to the appropriate value, either by the eeprom or by the host cpu. sram_size must be set to a value less than or equal to 2000h. values larger than 2000h will cause incorrect behavior. note : the minimum allowed number of pages is eight for normal network operation. this register is an alias of bcr25. 168 am79c976 8/01/00 preliminary stat0: status0 offset 030h stat0 indicates the status of various am79c976 func- tions. all bits in this register except for bits 12:10 indi- cate current status and are read only. bits 12:10 are latches that indicate the cause of a wake-up event. these three bits are cleared to 0 when power is first ap- plied to the device (power-on reset), but they are not af- fected by the state of the rst pin so that they are not disturbed when pci bus power is removed and reap- plied. bits 12:10 are ? write 1 to clear ? . therefore, the cpu can clear bits 12:10 by reading the register and then writing back the same data that it read. table 78. stat0: status0 register bit name description 31-15 res reserved locations. written as zeros and read as undefined. 14 pause_pend pause pending. this bit is set to 1 during the interval between the time that the am79c976 device receives a command to transmit a mac control pause frame and the time that the device finishes transmitting the frame. the host cpu should not attempt to write to the pause length register while this bit is 1. this bit is read only and is cleared by h_reset. 13 pausing pausing. this bit indicates that the device has received a mac control pause frame, and the pause timer has not yet timed out. this bit is read only and is cleared by h_reset. 12 pmat_det pattern match detected. this bit indicates that an onnow pattern match has occurred while the am79c976 device was in the onnow pattern match mode. this bit is an alias of pmat in csr116. this bit can be cleared to 0 either by writing 0 to csr116, bit 7, or by writing 1 to stat0, bit 12. this bit is cleared to 0 when power is first applied to the device, but not by the assertion of rst . 11 mp_det magic packet frame detected. this bit indicates that a magic packet pattern match has occurred while the am79c976 device was in the magic packet mode. this bit is an alias of mpmat in csr116. this bit can be cleared to 0 either by writing 0 to csr116, bit 5, or by writing 1 to stat0, bit 11. this bit is cleared to 0 when power is first applied to the device, but not by the assertion of rst . 10 lc_det link change detected. this bit indicates that a change in the link status of the external phy device has been detected while the device was in the link change wake-up mode. this bit is an alias of lcdet in csr116. this bit can be cleared to 0 either by writing 1 to csr116, bit 9, or by writing 1 to stat0, bit 10. this bit is cleared to 0 when power is first applied to the device, but not by the assertion of rst . 9-7 speed speed. this field indicates the bit rate at which the network is running. the following encoding is used: 000 unknown 001 reserved 010 10 mb/s 011 100 mb/s 100-111 reserved these bits are read only and are cleared by h_reset. 6 full_dplx full duplex. this bit is set when the device is operating in full-duplex mode. this bit is read only and is cleared by h_reset. 8/01/00 am79c976 169 preliminary software timer value register offset 0d8h the contents of this register are set to the default value (0ffffh) when the rst pin is asserted. this register is not affected by the serial eeprom read operation or by a serial eeprom read error. table 79. software timer value register 5 link_stat link status. this bit is set to the value of the link status bit in the status register (r1) of the default external phy. (the default external phy is the phy addressed by the ap_phy0_addr field of the autopoll0 register.) this bit is updated each time the external phy ? s status register is read, either by the auto-poll state machine, by the network port manager, or by a cpu-initiated read. however, when the force link status bit in cmd3 is set to 1, this bit is forced to 1, regardless of the contents of the external phy ? s status register. this bit is read only and is cleared by h_reset. 4 autoneg_ complete auto-negotiation complete. this bit is set to the value of the auto-negotiation complete bit in register 1 of the external phy as determined by the most recent port manager polling cycle. this bit is read only and is cleared by h_reset. 3 miipd mii phy detect. miipd reflects the quiescent state of the mdio pin. miipd is continuously updated whenever there is no management operation in progress on the mii interface. when a management operation begins on the interface, the state of miipd is preserved until the operation ends, when the quiescent state is again monitored and continuously updates the miipd bit. when the mdio pin is at a quiescent low state, miipd is cleared to 0. when the mdio pin is at a quiescent high state, miipd is set to 1. any transition on the miipd bit will set the miipdtint bit in int0. this bit is an alias of bcr32, bit 14. this bit is read only and is cleared by h_reset. 2 rx_ suspended receiver suspended. this bit has the value 1 while the receiver is suspended, and it has the value 0 when the receiver is not suspended. this bit is read only and is cleared by h_reset. 1 tx_ suspended transmitter suspended. this bit has the value 1 while the transmitter is suspended, and it has the value 0 when the transmitter is not suspended. this bit is read only and is cleared by h_reset. 0 running this bit is a read-only alias of the run bit in cmd0. when this bit is set, the device is enabled to transmit and receive frames and process descriptors. note that even though running is set, the receiver or transmitter might be disabled because rx_spnd or tx_spnd is set (in cmd0). this bit is read only and is cleared by h_reset. bit name description bit name description 15-0 stval software timer value. stval controls the maximum time for the software timer to count before generating the stint (csr7, bit 11) interrupt. the software timer is a free-running timer that is started upon the first write to stval. after the first write, the software timer will continually count and set the stint interrupt at the stval period. the stval value is interpreted as an unsigned number with a resolution of 10.24s. for instance, if stval is set to 48,828 (0bebch), the software timer period will be 0.5 s. the default value (0ffffh) corresponds to 0.6710784 s. setting stval to a value of 0 will result in erratic behavior. this register is an alias of bcr31. 170 am79c976 8/01/00 preliminary svid_a: pci subsystem vendor id alias register offset 1b6h this register is a writable alias of the subsystem ven- dor id field at offset 2ch in pci configuration space, which is read only. the purpose of this register is to allow the pci subsystem vendor id value to be loaded from the serial eeprom. the contents of this register are cleared to 0 when the rst pin is asserted, before the serial eeprom is read, and after a serial eeprom read error. table 80. svid: pci subsystem vendor id shadow register test0: test register offset 1a8h this register is used for factory test purposes only. all bits must be zero for normal operation. table 81. test0: test register bit name description 15-0 svid subsystem vendor id. svid is used together with the pci subsystem id register to uniquely identify the add-in board or subsystem the am79c976 controller is used in. subsystem vendor ids can be obtained form the pci sig. a value of 0 (the default) indicates that the am79c976 controller does not support subsystem identification. svid is aliased to the pci configuration space register subsystem vendor id (offset 2ch). this register is an alias of bcr23 and of the pci configuration space subsystem vendor id field at offset 2ch. bit name description 31:18 res factory test bits; must be 0 for normal operation. 17 cbio_en factory test bit; must be 0 for normal operation. 16:14 res factory test bits; must be 0 for normal operation. 13 eebusy_t factory test bit; must be 0 for normal operation. 12 res factory test bit; must be 0 for normal operation. 11 tsel factory test bit; must be 0 for normal operation. 10 mfsm_reset factory test bit; must be 0 for normal operation. 9 bfd_scale_down factory test bit; must be 0 for normal operation. 8 antst factory test bit; must be 0 for normal operation. 7:6 res factory test bits; must be 0 for normal operation. 5 ledchttst factory test bit; must be 0 for normal operation. 4 rtytst_bump factory test bit; must be 0 for normal operation. 3 rtytst_out factory test bit; must be 0 for normal operation. 2 rtytst_rangen factory test bit; must be 0 for normal operation. 1 rtytst_slot factory test bit; must be 0 for normal operation. 0 serrlevel factory test bit; must be 0 for normal operation. 8/01/00 am79c976 171 preliminary =*@?0=* offset 1b2h this register is a writable alias of the vendor id field at offset 0 in pci configuration space, which is read only. the purpose of this register is to allow the pci vendor id value to be loaded from the serial eeprom. the contents of this register are set to 1022h when the rst pin is asserted, before the serial eeprom is read, and after a serial eeprom read error. table 82. vid_a: pci vendor id alias register xmt_ring_len: transmit ring length register offset 140h the contents of this register are set to the default value 0 when the rst pin is asserted. this register is not af- fected by the serial eeprom read operation or by a se- rial eeprom read error. table 83. xmt_ring_len: transmit ring length register a# 0 << #%? ! 0 ! offset 188h the contents of this register are cleared to 0 when the rst pin is asserted, before the serial eeprom is read, and after a serial eeprom read error. bit name description 15-0 vid vendor id. the pci vendor id register is a 16-bit register that identifies the manufacturer of the am79c976 controller. amd ? s vendor id is 1022h. note that this vendor id is not the same as the manufacturer id in csr88 and csr89. the vendor id is assigned by the pci special interest group. the vendor id is not normally programmable, but the am79c976 controller allows this due to legacy operating systems that do not look at the pci subsystem vendor id and the vendor id to uniquely identify the add-in board or subsystem that the am79c976 controller is used in. note: if the operating system or the network operating system supports pci subsystem vendor id and subsystem id, use those to identify the add-in board or subsystem and program the vid with the default value of 1022h . software supplied by amd may not operate if the vid is anything other than 1022h. this register is an alias of the pci configuration space vendor id field at offset 00h and of bcr35. bit name description 15-0 xmt_ring_ len transmit ring length. contains the two's complement of the transmit descriptor ring length. this register is initialized during the optional am79c976 controller initialization routine based on the value in the tlen field of the initialization block. however, this register can be manually altered. the actual transmit ring length is defined by the current value in this register. the ring length can be defined as any value from 1 to 65535. this register is an alias of csr78. 172 am79c976 8/01/00 preliminary table 84. xmtpolltime: transmit polling interval register rap register the rap (register address pointer) register is used to gain access to csr and bcr registers on board the am79c976 controller. the rap contains the address of a csr or bcr. as an example of rap use, consider a read access to csr4. in order to access this register, it is necessary to first load the value 0004h into the rap by performing a write access to the rap offset of 12h (12h when wio mode has been selected, 14h when dwio mode has been selected). then a second access is performed, this time to the rdp offset of 10h (for either wio or dwio mode). the rdp access is a read access, and since rap has just been loaded with the value of 0004h, the rdp read will yield the contents of csr4. a read of the bdp at this time (offset of 16h when wio mode has been selected, 1ch when dwio mode has been select- ed) will yield the contents of bcr4, since the rap is used as the pointer into both bdp and rdp space. 0? 0 bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-8 res reserved locations. read and written as zeros. 7-0 rap register address port. the value of these 8 bits determines which csr or bcr will be accessed when an i/o access to the rdp or bdp port, respectively, is per- formed. a write access to undefined csr or bcr locations may cause un- expected reprogramming of the am79c976 control registers. a read access will yield undefined values. read/write accessible. rap is cleared by h_reset or s_reset and is unaffected by setting the stop bit. bit name description 15-0 xmtpolltime transmit polling interval. this register contains the time that the am79c976 controller will wait between successive polling operations. the xmtpolltime value is expressed as the two ? s complement of the desired interval, where each bit of xmtpolltime represents erclk clock periods. xmtpolltime[3:0] are ignored. (xmtpolltime[16] is implied to be a one, so xmtpolltime[15] is significant and does not represent the sign of the two ? s complement xmtpolltime value.) the default value of this register is 0000h. this corresponds to a polling interval of 65,536 clock periods (2.185 ms when erclk = 90 mhz). setting the init bit starts an initialization process that sets xmtpolltime to its default value. if the user wants to program a value for xmtpolltime other than the default, then he must change the value after the initialization sequence has completed. this register is an alias for csr47. 8/01/00 am79c976 173 preliminary control and status registers the control and status registers (csrs) are included for compatibility with older pcnet family software. all csr functions can be accessed more efficiently through the memory-mapped registers. the csr space is accessible by performing accesses to the rdp (register data port). the particular csr that is read or written during an rdp access will de- pend upon the current setting of the rap. rap serves as a pointer into the csr space. am79c976 csrs can be accessed at any time. for older pcnet family devices certain csrs could only be accessed when the device is stopped. 4?!/22/, certain bits in csr0 indicate the cause of an interrupt. the register is designed so that these indicator bits are cleared by writing ones to those bit locations. this means that the software can read csr0 and write back the value just read to clear the interrupt condition. bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15 err obsolete function. read/write accessible. read returns zero. 14 babl obsolete function. read/write accessible. read returns zero. 13 cerr obsolete function. read/write accessible. read returns zero. 12 miss obsolete function. read/write accessible. read returns zero. 11 merr obsolete function. read/write accessible. read returns zero. 10 rint receive interrupt is set by the am79c976 controller after the last descriptor of a receive frame has been updated by writing a 0 to the ownership bit. rint may also be set when the first descrip- tor of a receive frame has been updated by writing a 0 to the ownership bit if the lappen bit of csr3 has been set to a 1. when rint is set, inta is assert- ed if iena is 1 and the mask bit rintm (csr3, bit 10) is 0. read/write accessible. rint is cleared by the host by writing a 1. writing a 0 has no effect. rint is cleared by h_reset, s_reset, or by setting the stop bit. 9 tint transmit interrupt is set by the am79c976 controller after the own bit in the last descriptor of a transmit frame has been cleared to indicate the frame has been copied to the transmit fifo. when tint is set, inta is assert- ed if iena is 1 and the mask bit tintm (csr3, bit 9) is 0. read/write accessible. tint is cleared by the host by writing a 1. writing a 0 has no effect. tint is cleared by h_reset, s_reset, or by setting the stop bit. 8 idon initialization done is set by the am79c976 controller after the initialization sequence has com- pleted. when idon is set, the am79c976 controller has read the initialization block from mem- ory. when idon is set, inta is as- serted if iena is 1 and the mask bit idonm (csr3, bit 8) is 0. read/write accessible. idon is cleared by the host by writing a 1. writing a 0 has no effect. idon is cleared by h_reset, s_reset, or by setting the stop bit. 7 intr interrupt flag indicates that one or more following interrupt caus- ing conditions has occurred: idon, rint, sint, tint, tx- strt, uint, stint, mreint, mccint, mcciint, miipdtint, mapint, mpint, apint, lcint, spndint and the associated mask or enable bit is pro- grammed to allow the event to cause an interrupt. if iena is set to 1 and intr is set, inta will be active. when intr is set by sint or slpint, inta will be active in- dependent of the state of iena. 174 am79c976 8/01/00 preliminary intr is read only. intr is cleared by clearing all of the ac- tive individual interrupt bits that have not been masked out. 6 iena interrupt enable allows inta to be active if the interrupt flag is set. if iena = 0, then inta will be disabled regardless of the state of intr. read/write accessible. iena is set by writing a 1 and cleared by writing a 0. iena is cleared by h_reset or s_reset and set- ting the stop bit. 5 rxon receive on indicates that the re- ceive function is enabled. rxon is set if drx (csr15, bit 0) is set to 0 after the strt bit is set. if init and strt are set together, rxon will not be set until after the initialization block has been read in. rxon is read only. rxon is cleared by h_reset or s_reset and setting the stop bit. 4 txon transmit on indicates that the transmit function is enabled. txon is set if dtx (csr15, bit 1) is set to 0 after the strt bit is set. if init and strt are set to- gether, txon will not be set until after the initialization block has been read in. this bit will reset if the dxsuflo bit (csr3, bit 6) is reset and there is an underflow condition encoun- tered. txon is read only. txon is cleared by h_reset or s_reset and setting the stop bit. 3 tdmd transmit demand, when set, causes the buffer management unit to access the transmit de- scriptor ring without waiting for the poll-time counter to elapse. if txon is not enabled, tdmd bit will be reset and no transmit de- scriptor ring access will occur. tdmd is required to be set if the txdpoll bit in csr4 is set. set- ting tdmd while txdpoll = 0 merely hastens the am79c976 controller ? s next access to a transmit descriptor ring entry. read/write accessible. tdmd is set by writing a 1. writing a 0 has no effect. tdmd will be cleared by the buffer management unit when it fetches a transmit de- scriptor. tdmd is cleared by h_reset or s_reset and set- ting the stop bit. 2 stop stop assertion disables the chip from all dma activity. the chip re- mains inactive until either strt or init are set. if stop, strt and init are all set together, stop will override strt and init. read/write accessible. stop is set by writing a 1, by h_reset or s_reset. writing a 0 has no effect. stop is cleared by setting either strt or init. 1 strt strt assertion enables am79c976 controller to send and receive frames, and perform buff- er management operations. set- ting strt clears the stop bit. if strt and init are set together, the am79c976 controller initial- ization will be performed first. read/write accessible. strt is set by writing a 1. writing a 0 has no effect. strt is cleared by h_reset, s_reset, or by set- ting the stop bit. 0 init init assertion enables the am79c976 controller to begin the initialization procedure which reads in the initialization block from memory. setting init clears the stop bit. if strt and init are set together, the am79c976 controller initialization will be per- formed first. init is not cleared when the initialization sequence has completed. read/write accessible. init is set by writing a 1. writing a 0 has 8/01/00 am79c976 175 preliminary no effect. init is cleared by h_reset, s_reset, or by set- ting the stop bit. ? 6 (7 4 bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 iadr[15:0] lower 16 bits of the address of the initialization block. bit loca- tions 1 and 0 must both be 0 to align the initialization block to a dword boundary. this register is aliased with csr16. read/write accessible. unaffect- ed by h_reset or s_reset, or by setting the stop bit. ? 6 (7 bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-8 iadr[31:24] if ssize32 is set (bcr20, bit 8), then the iadr[31:24] bits will be used strictly as the upper 8 bits of the initialization block address. however, if ssize32 is reset (bcr20, bit 8), then the iadr[31:24] bits will be used to generate the upper 8 bits of all bus mastering addresses, as re- quired for a 32-bit address bus. note that the 16-bit software structures specified by the ssize32 = 0 setting will yield only 24 bits of address for the am79c976 bus master access- es, while the 32-bit hardware for which the am79c976 controller is intended will require 32 bits of ad- dress. therefore, whenever ssize32 = 0, the iadr[31:24] bits will be appended to the 24-bit initialization address, to each 24- bit descriptor base address and to each beginning 24-bit buffer address in order to form complete 32-bit addresses. the upper 8 bits that exist in the descriptor ad- dress registers and the buffer ad- dress registers which are stored on board the am79c976 control- ler will be overwritten with the iadr[31:24] value, so that csr accesses to these registers will show the 32-bit address that in- cludes the appended field. if ssize32 = 1, then software will provide 32-bit pointer values for all of the shared software struc- tures - i.e., descriptor bases and buffer addresses, and therefore, iadr[31:24] will not be written to the upper 8 bits of any of these resources, but it will be used as the upper 8 bits of the initializa- tion address. this register is aliased with csr17. read/write accessible. unaffect- ed by h_reset, s_reset, or by setting the stop bit. 7-0 iadr[23:16] bits 23 through 16 of the address of the initialization block. when- ever this register is written, csr17 is updated with csr2 ? s contents. read/write accessible unaffect- ed by h_reset, s_reset, or by setting the stop bit. ?'# 7 * bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-13 res reserved locations. read and written as zero. 12 missm obsolete function. writing has no effect. read as undefined. 11 merrm obsolete function. writing has no effect. read as undefined. 10 rintm receive interrupt mask. if rintm is set, the rint bit will be masked and unable to set the intr bit. read/write accessible. rintm is set by h_reset but cleared by s_reset and is not affected by stop. 176 am79c976 8/01/00 preliminary 9 tintm transmit interrupt mask. if tintm is set, the tint bit will be masked and unable to set the intr bit. read/write accessible. tintm is set by h_reset but cleared by s_reset and is not affected by stop. 8 idonm initialization done mask. if idonm is set, the idon bit will be masked and unable to set the intr bit. read/write accessible. idonm is cleared by h_reset or s_reset and is not affected by stop. 7 res reserved location. read and written as zeros. 6 dxsuflo obsolete function. writing has no effect. read as undefined. 5 lappen look ahead packet processing enable. when set to a 1, the lappen bit will cause the am79c976 controller to generate an interrupt following the descrip- tor write operation to the first buff- er of a receive frame. this interrupt will be generated in ad- dition to the interrupt that is gen- erated following the descriptor write operation to the last buffer of a receive packet. the interrupt will be signaled through the rint bit of csr0. setting lappen to a 1 also en- ables the am79c976 controller to read the stp bit of receive de- scriptors. the am79c976 con- troller will use the stp information to determine where it should begin writing a receive packet ? s data. note that while in this mode, the am79c976 con- troller can write intermediate packet data to buffers whose de- scriptors do not contain stp bits set to 1. following the write to the last descriptor used by a packet, the am79c976 controller will scan through the next descriptor entries to locate the next stp bit that is set to a 1. the am79c976 controller will begin writing the next packets data to the buffer pointed to by that descriptor. note that because several de- scriptors may be allocated by the host for each packet, and not all messages may need all of the de- scriptors that are allocated be- tween descriptors that contain stp = 1, then some descriptors/ buffers may be skipped in the ring. while performing the search for the next stp bit that is set to 1, the am79c976 controller will advance through the receive de- scriptor ring regardless of the state of ownership bits. if any of the entries that are examined during this search indicate am79c976 controller ownership of the descriptor but also indicate stp = 0, then the am79c976 controller will reset the own bit to 0 in these entries. if a scanned entry indicates host ownership with stp = 0, then the am79c976 controller will not al- ter the entry, but will advance to the next entry. when the stp bit is found to be true, but the descriptor that con- tains this setting is not owned by the am79c976 controller, then the am79c976 controller will stop advancing through the ring en- tries and begin periodic polling of this entry. when the stp bit is found to be true, and the descrip- tor that contains this setting is owned by the am79c976 control- ler, then the am79c976 control- ler will stop advancing through the ring entries, store the descrip- tor information that it has just read, and wait for the next re- ceive to arrive. this behavior allows the host software to pre-assign buffer space in such a manner that the header portion of a receive pack- et will always be written to a par- ticular memory area, and the data portion of a receive packet will al- ways be written to a separate memory area. the interrupt is 8/01/00 am79c976 177 preliminary generated when the header bytes have been written to the header memory area. read/write accessible. the lap- pen bit will be reset to 0 by h_reset or s_reset and will be unaffected by stop. see appendix b for more infor- mation on the look ahead pack- et processing concept. 4 dxmt2pd disable transmit two part defer- ral (see medium allocation sec- tion in the media access management section for more details). if dxmt2pd is set, transmit two part deferral will be disabled. read/write accessible. dxmt2pd is cleared by h_reset or s_reset and is not affected by stop. 3 emba enable modified back-off algo- rithm (see contention resolution section in media access man- agement section for more de- tails). if emba is set, a modified back-off algorithm is implement- ed. read/write accessible. emba is cleared by h_reset or s_reset and is not affected by stop. 2 bswp byte swap. this bit is used to choose between big and little en- dian modes of operation. when bswp is set to a 1, big endian mode is selected. when bswp is set to 0, little endian mode is se- lected. when big endian mode is select- ed, the am79c976 controller will swap the order of bytes on the ad bus during a data phase on ac- cesses to the fifos only. specif- ically, ad[31:24] becomes byte 0, ad[23:16] becomes byte 1, ad[15:8] becomes byte 2, and ad[7:0] becomes byte 3 when big endian mode is selected. when little endian mode is se- lected, the order of bytes on the ad bus during a data phase is: ad[31:24] is byte 3, ad[23:16] is byte 2, ad[15:8] is byte 1, and ad[7:0] is byte 0. byte swap only affects data transfers that involve the fifos. initialization block transfers are not affected by the setting of the bswp bit. descriptor transfers are not affected by the setting of the bswp bit. rdp, rap, bdp and pci configuration space ac- cesses are not affected by the setting of the bswp bit. address prom transfers are not affected by the setting of the bswp bit. expansion rom accesses are not affected by the setting of the bswp bit. note that the byte ordering of the pci bus is defined to be little en- dian. bswp should not be set to 1 when the am79c976 controller is used in a pci bus application. read/write accessible. bswp is cleared by h_reset or s_reset and is not affected by stop. 1-0 res reserved locations. the values written to these bits have no ef- fect on the operation of the de- vice. these bits should be read as undefined. "? certain bits in csr4 indicate the cause of an interrupt. the register is designed so that these indicator bits are cleared by writing ones to those bit locations. this means that the software can read csr4 and write back the value just read to clear the interrupt condition. bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15 res reserved location. the value written to this bit has no effect on the operation of the device. this bit should be read as undefined. 14 dmaplus writing and reading from this bit has no effect. dmaplus is al- ways 0. 178 am79c976 8/01/00 preliminary 13 res reserved location. written as zero and read as undefined. 12 txdpoll disable transmit polling. if txd- poll is set, the buffer manage- ment unit will disable transmit polling. likewise, if txdpoll is cleared, automatic transmit poll- ing is enabled. if txdpoll is set, tdmd bit in csr0 must be set in order to initiate a manual poll of a transmit descriptor. transmit de- scriptor polling will not take place if txon is reset. transmit polling will take place following receive activities. read/write accessible. txd- poll is cleared by h_reset or s_reset and is unaffected by the stop bit. 11 apad_xmt auto pad transmit. when set, apad_xmt enables the auto- matic padding feature. transmit frames will be padded to extend them to 64 bytes including fcs. the fcs is calculated for the en- tire frame, including pad, and ap- pended after the pad field. when the auto padding logic modifies a frame, a valid fcs field will be appended to the frame, regard- less of the state of the dxmtfcs bit (csr15, bit 3) and of the add_fcs bit in the transmit de- scriptor. read/write accessible. apad_xmt is cleared by h_reset or s_reset and is unaffected by the stop bit. 10 astrp_rcvauto strip receive. when set, astrp_rcv enables the auto- matic pad stripping feature. the pad and fcs fields will be stripped from receive frames and not placed in the fifo. read/write accessible. astrp_rcv is cleared by h_reset or s_reset and is unaffected by the stop bit. 9 mfco obsolete function. writing has no effect. read as undefined. 8 mfcom obsolete function. writing has no effect. read as undefined. 7 uintcmd user interrupt command. uintcmd can be used by the host to generate an interrupt un related to any network activity. writing a 1 to this bit causes uint to be set to 1, which in turn causes inta to be asserted if in- terrupts are enabled. read/write accessible. uintc- md is always read as 0. 6 uint user interrupt. uint is set by the am79c976 controller after the host has issued a user interrupt command by setting uintcmd (csr4, bit 7) to 1. read/write accessible. uint is cleared by the host by writing a 1. writing a 0 has no effect. uint is cleared by h_reset or s_reset or by setting the stop bit. 5 rcvcco obsolete function. writing has no effect. read as undefined. 4 rcvccom obsolete function. writing has no effect. read as undefined. 3 txstrt transmit start status is set by the am79c976 controller whenever it begins transmission of a frame. when txstrt is set, inta is as- serted if iena is 1 and the mask bit txstrtm is 0. read/write accessible. txstrt is cleared by the host by writing a 1. writing a 0 has no effect. tx- strt is cleared by h_reset, s_reset, or by setting the stop bit. 2 txstrtm transmit start mask. if tx- strtm is set, the txstrt bit will be masked and unable to set the intr bit. read/write accessible. tx- strtm is set to 1 by h_reset or s_reset and is not affected by the stop bit. 8/01/00 am79c976 179 preliminary 1-0 res reserved locations. written as zeros and read as undefined. )?%&' certain bits in csr5 indicate the cause of an interrupt. the register is designed so that these indicator bits are cleared by writing ones to those bit locations. this means that the software can read csr5 and write back the value just read to clear the interrupt condition. bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15 tokintd obsolete function. writing has no effect. read as undefined. 14 ltinten last transmit interrupt enable. when this bit is set to 1, the ltint bit in transmit descriptors can be used to determine when transmit interrupts occur. the transmit interrupt (tint) bit will be set after a frame has been copied to the transmit fifo if the ltint bit in the frame ? s last transmit descriptor is set. if the ltint bit in the frame ? s last de- scriptor is 0 tint will not be set after the frame has been copied to the transmit fifo. read/write accessible. ltinten is cleared by h_reset or s_reset and is unaffected by stop. 13 txdnint transmission done interrupt. this bit is set when the transmit- ter has finished sending a frame. this bit is included for debugging purposes. read/write accessible. txdn- int is cleared by the host by writ- ing a 1. writing a 0 has no effect. the state of txdnint is not af- fected by clearing any of the pci status register bits that get set when a data parity error (dataperr, bit 8), master abort (rmabort, bit 13), or target abort (rtabort, bit 12) occurs. txdnint is cleared by h_reset, s_reset, or by set- ting the stop bit. 12 txdninten transmission done interrupt en- able. when this bit is set, the intr bit will be set when the txdnint bit in int0 is set. read/write accessible. txdn- inten is cleared by h_reset or s_reset and is unaffected by stop. 11 sint system interrupt is set by the am79c976 controller when it de- tects a system error during a bus master transfer on the pci bus. system errors are data parity er- ror, master abort, or a target abort. the setting of sint due to data parity error is not dependent on the setting of perren (pci command register, bit 6). when sint is set, inta is assert- ed if the enable bit sinte is 1. note that the assertion of an in- terrupt due to sint is not depen- dent on the state of the inea bit, since inea is cleared by the stop reset generated by the system error. read/write accessible. sint is cleared by the host by writing a 1. writing a 0 has no effect. the state of sint is not affected by clearing any of the pci status register bits that get set when a data parity error (dataperr, bit 8), master abort (rmabort, bit 13), or target abort (rtabort, bit 12) occurs. sint is cleared by h_reset or s_reset and is not affected by setting the stop bit. 10 sinte system interrupt enable. if sin- te is set, the sint bit will be able to set the intr bit. read/write accessible. sinte is set to 0 by h_reset or s_reset and is not affected by setting the stop bit. 9-8 res reserved locations. written as zeros and read as undefined. 7 exdint obsolete function. writing has no effect. read as undefined. 180 am79c976 8/01/00 preliminary 6 exdinte obsolete function. writing has no effect. read as undefined. 5 mpplba magic packet physical logical broadcast accept. if mpplba is at its default value of 0, the am79c976 controller will only de- tect a magic packet frame if the destination address of the packet matches the content of the physi- cal address register (padr). if mpplba is set to 1, the destina- tion address of the magic packet frame can be unicast, multicast, or broadcast. note that the set- ting of mpplba only affects the address detection of the magic packet frame. the magic packet frame ? s data sequence must be made up of 16 consecutive phys- ical addresses (padr[47:0]) re- gardless of what kind of destination address it has. this bit is or ? ed with empplba bit (csr116, bit 6). read/write accessible. mpplba is set to 0 by h_reset or s_reset and is not affected by setting the stop bit. 4 mpint magic packet interrupt. magic packet interrupt is set by the am79c976 controller when the device is in the magic packet mode and the am79c976 con- troller receives a magic packet frame. when mpint is set to 1, inta is asserted if iena (csr0, bit 6) and the enable bit mpinte are set to 1. read/write accessible. mpint is cleared by the host by writing a 1. writing a 0 has no affect. mpint is cleared by h_reset, s_reset, or by setting the stop bit. 3 mpinte magic packet interrupt enable. if mpinte is set to 1, the mpint bit will be able to set the intr bit. read/write accessible. mpinte is cleared to 0 by h_reset or s_reset and is not affected by setting the stop bit. 2 mpen magic packet enable. mpen al- lows activation of the magic packet mode by the host. the am79c976 controller will enter the magic packet mode when both mpen and mpmode are set to 1. read/write accessible. mpen is cleared to 0 by h_reset or s_reset and is not affected by setting the stop bit. 1 mpmode the am79c976 controller will en- ter the magic packet mode when mpmode is set to 1 and either pg is asserted or mpen is set to 1. read/write accessible. mp- mode is cleared to 0 by h_reset or s_reset and is not affected by setting the stop bit. 0 spnd suspend. setting spnd to 1 will cause the am79c976 controller to start requesting entrance into suspend mode. the host must poll spnd until it reads back 1 to determine that the am79c976 controller has entered the sus- pend mode. setting spnd to 0 will get the am79c976 controller out of suspend mode. spnd can only be set to 1 if stop (csr0, bit 2) is set to 0. h_reset, s_reset or setting the stop bit will get the am79c976 controller out of suspend mode. requesting entrance into the suspend mode by the host de- pends on the setting of the fastspnde bit (csr7, bit 15). refer to the bit description of the fastspnde bit and the sus- pend section in detailed func- tions, buffer management unit for details. in suspend mode, all of the csr and bcr registers are accessi- ble. as long as the am79c976 controller is not reset while in suspend mode (by h_reset, s_reset or by setting the stop bit), no re-initialization of the de- vice is required after the device 8/01/00 am79c976 181 preliminary comes out of suspend mode. the am79c976 controller will contin- ue at the transmit and receive de- scriptor ring locations, from where it had left, when it entered the suspend mode. read/write accessible. spnd is cleared by h_reset, s_reset, or by setting the stop bit. ,? bit name description 31-0 res reserved locations. written as zeros and read as undefined. /?%&' certain bits in csr7 indicate the cause of an interrupt. the register is designed so that these indicator bits are cleared by writing ones to those bit locations. this means that the software can read csr7 and write back the value just read to clear the interrupt condition. bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15 fastspnde fast suspend enable. when fastspnde is set to 1, the am79c976 controller performs a fast suspend whenever the spnd bit is set. when a fast suspend is request- ed, the am79c976 controller per- forms a quick entry into the suspend mode. at the time the spnd bit is set, the am79c976 controller will complete the dma process of any transmit and/or re- ceive packet that had already be- gun dma activity. in addition, any transmit packet that had started transmission will be fully transmit- ted and any receive packet that had begun reception will be fully received. however, no additional packets will be transmitted or re- ceived and no additional transmit or receive dma activity will begin. hence, the am79c976 controller may enter the suspend mode with transmit and/or receive packets still in the fifos or the sram. when fastspnde is 0 and the spnd bit is set, the am79c976 controller may take longer before entering the suspend mode. at the time the spnd bit is set, the am79c976 controller will com- plete the dma process of a trans- mit packet if it had already begun and the am79c976 controller will completely receive a receive packet if it had already begun. additionally, all transmit packets stored in the transmit fifos and the transmit buffer area in the sram (if one is enabled) will be transmitted and all receive pack- ets stored in the receive fifos, and the receive buffer area in the sram (if one is enabled) will be transferred into system memory. since the fifo and sram con- tents are flushed, it may take much longer before the am79c976 controller enters the suspend mode. the amount of time that it takes depends on many factors including the size of the sram, bus latency, and net- work traffic level. when a write to csr5 is per- formed with bit 0 (spnd) set to 1, the value that is simultaneously written to fastspnde is used to determine which approach is used to enter suspend mode. read/write accessible. fastsp- nde is cleared by h_reset, s_reset or by setting the stop bit. 14 res reserved location. written as ze- ro, read as undefined. 13 rdmd receive demand, when set, causes the buffer management unit to access the receive de- scriptor ring without waiting for the chain poll-time counter to ex- pire. read/write accessible. rdmd is set by writing a 1. writing a 0 has no effect. rdmd will be cleared by the buffer management unit 182 am79c976 8/01/00 preliminary when it fetches a receive de- scriptor. rdmd is cleared by h_reset or by s_reset. rdmd is unaffected by setting the stop bit. 12 chdpoll disable chain polling. if chd- poll is set, the buffer manage- ment unit will disable chain polling. likewise, if chdpoll is cleared, automatic chain polling is enabled. if chdpoll is set and the buffer management unit is in the middle of a buffer-changing opera- tion, setting the rdmd bit in cmd0 or csr7 will cause a poll of the current receive descriptor, and setting the tdmd bit in cmd0 or crr0 will cause a poll of the current transmit descriptor. if chdpoll is set, the rdmd bit in csr7 can be set to initiate a manual poll of a receive or transmit descriptor if the buffer management unit is in the middle of a buffer-chaining operation. read/write accessible. chd- poll is cleared by h_reset. chdpoll is unaffected by s_reset or by setting the stop bit. 11 stint software timer interrupt. the software timer interrupt is set by the am79c976 controller when the software timer counts down to 0. the software timer will im- mediately load the stval (bcr 31, bits 5-0) into the software timer and begin counting down. when stint is set to 1, inta is asserted if the enable bit stinte is set to 1. read/write accessible. stint is cleared by the host by writing a 1. writing a 0 has no effect. stint is cleared by h_reset and is not affected by s_reset or set- ting the stop bit. 10 stinte software timer interrupt enable. if stinte is set, the stint bit will be able to set the intr bit. read/write accessible. stinte is set to 0 by h_reset and is not affected by s_reset or setting the stop bit. 9 mreint mii management read error in- terrupt. the mii read error inter- rupt is set by the am79c976 controller to indicate that the cur- rently read register from the ex- ternal phy is invalid. the contents of bcr34 are incorrect and that the operation should be performed again. the indication of an incorrect read comes from the phy. during the read turn- around time of the mii manage- ment frame the external phy should drive the mdio pin to a low state. if this does not hap- pen, it indicates that the phy and the am79c976 controller have lost synchronization. when mreint is set to 1, inta is asserted if the enable bit mrein- te is set to 1. read/write accessible. mreint is cleared by the host by writing a 1. writing a 0 has no effect. mre- int is cleared by h_reset and is not affected by s_reset or setting the stop bit. 8 mreinte mii management read error in- terrupt enable. if mreinte is set, the mreint bit will be able to set the intr bit. read/write accessible. mrein- te is set to 0 by h_reset and is not affected by s_reset or set- ting the stop bit 7 mapint mii management auto-poll inter- rupt. this bit is set when the auto-poll state machine detects a change in any phy register that is polled by the auto-poll state machine. when mapint is set to 1, inta is asserted if the enable bit map- inte is set to 1. read/write accessible. mapint is cleared by the host by writing a 1. writing a 0 has no effect. map- int is cleared by h_reset and 8/01/00 am79c976 183 preliminary is not affected by s_reset or setting the stop bit. 6 mapinte mii auto-poll interrupt enable. if mapinte is set, the mapint bit will be able to set the intr bit. read/write accessible. map- inte is set to 0 by h_reset and is not affected by s_reset or setting the stop bit 5 mccint mii management command complete interrupt. the mii man- agement command complete in- terrupt is set by the am79c976 controller when a read or write operation to the mii data port (bcr34) is complete. when mccint is set to 1, inta is asserted if the enable bit mccinte is set to 1. read/write accessible. mccint is cleared by the host by writing a 1. writing a 0 has no effect. mccint is cleared by h_reset and is not affected by s_reset or setting the stop bit. 4 mccinte mii management command complete interrupt enable. if mccinte is set to 1, the mccint bit will be able to set the intr bit when the host reads or writes to the mii data port (bcr34) only. internal mii man- agement commands will not gen- erate an interrupt. for instance, auto-poll state machine generat- ed mii management frames will not generate an interrupt upon completion unless there is a com- pare error which gets reported through the mapint (csr7, bit 6) interrupt or the mcciinte is set to 1. read/write accessible. mc- cinte is set to 0 by h_reset and is not affected by s_reset or setting the stop bit. 3 mcciint mii management command complete internal interrupt. the mii management command complete interrupt is set by the am79c976 controller when a read or write operation on the mii management port is complete from an internal operation. exam- ples of internal operations are auto-poll or mii management port generated mii management frames. these are normally hid- den to the host. when mcciint is set to 1, inta is asserted if the enable bit mccinte is set to 1. read/write accessible. mcciint is cleared by the host by writing a 1. writing a 0 has no effect. mcciint is cleared by h_reset and is not affected by s_reset or setting the stop bit. 2 mcciinte mii management command complete internal interrupt en- able. if mcciinte is set to 1, the mcciint bit will be able to set the intr bit when the internal state machines generate mii management frames. for in- stance, when mcciinte is set to 1 and the auto-poll state ma- chine generates a mii manage- ment frame, the mcciint will set the intr bit upon completion of the mii management frame re- gardless of the comparison out- come. read/write accessible. mcciinte is set to 0 by h_reset and is not affected by s_reset or setting the stop bit. 1 miipdtint mii phy detect transition inter- rupt. the mii phy detect transi- tion interrupt is set by the am79c976 controller whenever the miipd bit (bcr32, bit 14) transitions from 0 to 1 or vice ver- sa. read/write accessible. miip- dtint is cleared by the host by writing a 1. writing a 0 has no ef- fect. miipdtint is cleared by h_reset and is not affected by s_reset or setting the stop bit. 184 am79c976 8/01/00 preliminary 0 miipdtintemii phy detect transition inter- rupt enable. if miipdtinte is set to 1, the miipdtint bit will be able to set the intr bit. read/write accessible. miip- dtinte is set to 0 by h_reset and is not affected by s_reset or setting the stop bit. 1?< ( 4 bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 ladrf[15:0] logical address filter, ladrf-[15:0]. the content of this register is undefined until loaded from the initialization block after the init bit in csr0 has been set or a direct register write has been performed on this register. read/write accessible. these bits are cleared by h_reset but are unaffected by s_reset, or stop. 2?< ( bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 ladrf[31:16] logical address filter, ladrf- [31:16]. the content of this regis- ter is undefined until loaded from the initialization block after the init bit in csr0 has been set or a direct register write has been performed on this register. read/write accessible. these bits are cleared by h_reset but are unaffected by s_reset, or stop. 4?< ( bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 ladrf[47:32]logical address filter, ladrf[47:32]. the content of this register is undefined until loaded from the initialization block after the init bit in csr0 has been set or a direct register write has been performed on this register. read/write accessible. these bits are cleared by h_reset but are unaffected by s_reset, or stop. ?< ( bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 ladrf[63:48] logical address filter, ladrf[63:48]. the content of this register is undefined until loaded from the initialization block after the init bit in csr0 has been set or a direct register write has been performed on this register. read/write accessible. these bits are cleared by h_reset but are unaffected by s_reset, or stop. ?0+$ ( 4 note: bits 15-0 in this register are programmable through the eeprom. bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 padr[15:0] physical address register, padr[15:0]. the contents of this register are loaded from eeprom after h_reset or by an eeprom read command (pread, bcr19, bit 14). if the eeprom is not present, the con- tents of this register are unde- fined. this register can also be loaded from the initialization block after the init bit in csr0 has been set 8/01/00 am79c976 185 preliminary or a direct register write has been performed on this register. read/write accessible. these bits are cleared by h_reset but are unaffected by s_reset, or stop. ?0+$ ( note: bits 15-0 in this register are programmable through the eeprom. bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 padr[31:16]physical address register, padr[31:16]. the contents of this register are loaded from ee- prom after h_reset or by an eeprom read command (pread, bcr19, bit 14). if the eeprom is not present, the con- tents of this register are unde- fined. this register can also be loaded from the initialization block after the init bit in csr0 has been set or a direct register write has been performed on this register. read/write accessible. these bits are cleared by h_reset but are unaffected by s_reset, or stop. "?0+$ ( note: bits 15-0 in this register are programmable through the eeprom. bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 padr[47:32]physical address register, padr[47:32].the contents of this register are loaded from eeprom after h_reset or by an eeprom read command (pread, bcr19, bit 14). if the eeprom is not present, the con- tents of this register are unde- fined. this register can also be loaded from the initialization block after the init bit in csr0 has been set or a direct register write has been performed on this register. read/write accessible. these bits are cleared by h_reset but are unaffected by s_reset, or stop. )?# this register ? s fields are loaded during the am79c976 controller initialization routine with the corresponding initialization block values, or when a direct register write has been performed on this register. bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15 prom promiscuous mode. when prom = 1, all incoming receive frames are accepted. read/write accessible. 14 drcvbc disable receive broadcast. when set, disables the am79c976 controller from re- ceiving broadcast messages. used for protocols that do not support broadcast addressing, except as a function of multicast. drcvbc is cleared by activation of h_reset or s_reset (broadcast messages will be re- ceived) and is unaffected by stop. read/write accessible. 13 drcvpa disable receive physical ad- dress. when set, the physical ad- dress detection (station or node id) of the am79c976 controller will be disabled. frames ad- dressed to the node ? s individual physical address will not be rec- ognized. read/write accessible. 12-9 res reserved locations. written as zeros and read as undefined. 8-7 portsel[1:0]obsolete function. writing has no effect. read as undefined. 6 intl obsolete function. writing has no effect. read as undefined. 186 am79c976 8/01/00 preliminary 5 drty disable retry. when drty is set to 1, the am79c976 controller will attempt only one transmission. in this mode, the device will not pro- tect the first 64 bytes of frame data in the transmit fifo from being overwritten, because auto- matic retransmission will not be necessary. when drty is set to 0, the am79c976 controller will attempt 16 transmissions before signaling a retry error. read/write accessible. 4 fcoll force collision. this bit allows the collision logic to be tested. the am79c976 controller must be in internal loopback for fcoll to be valid. if fcoll = 1, a colli- sion will be forced during loop- back transmission attempts, which will result in a retry error. if fcoll = 0, the force collision logic will be disabled. fcoll is defined after the initialization block is read. read/write accessible. 3 dxmtfcs disable transmit crc (fcs). when dxmtfcs is set to 0, the transmitter will generate and ap- pend an fcs to the transmitted frame. when dxmtfcs is set to 1, no fcs is generated or sent with the transmitted frame. dxmtfcs is overridden when add_fcs and enp bits are set in the transmit descriptor. when the auto padding logic, which is enabled by the apad_xmt bit (csr4, bit11), adds padding to a frame, a valid fcs field is appended to the frame, regardless of the state of dxmtfcs. if dxmtfcs is set and add_fcs is clear for a particular frame, no fcs will be generated. if add_fcs is set for a particular frame, the state of dxmtfcs is ignored and a fcs will be ap- pended on that frame by the transmit circuitry. see also the add_fcs bit in the transmit de- scriptor. this bit was called dtcr in the lance (am7990) device. read/write accessible. 2 loop loopback enable allows the am79c976 controller to operate in full-duplex mode for test pur- poses. the setting of the full- duplex control bits in bcr9 have no effect when the device oper- ates in loopback mode. when loop = 1, loopback is enabled. in combination with intl and miiilp, various loopback modes are defined as follows:. refer to loop back operation section for more details. read/write accessible. loop is cleared by h_reset or s_reset and is unaffected by stop. 1 dtx disable transmit results in am79c976 controller not access- ing the transmit descriptor ring and, therefore, no transmissions are attempted. dtx = 0, will set txon bit (csr0 bit 4) if strt (csr0 bit 1) is asserted. read/write accessible. 0 drx disable receiver results in the am79c976 controller not access- ing the receive descriptor ring and, therefore, all receive frame data are ignored. drx = 0, will set rxon bit (csr0 bit 5) if strt (csr0 bit 1) is asserted. read/write accessible. ,- ? bit name description 31-0 res reserved locations. written as zeros and read as undefined. loop miiilp function 0 0 normal operation 0 1 internal loop 1 0 external loop 8/01/00 am79c976 187 preliminary "? ( <8 bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 badrl contains the lower 16 bits of the base address of the receive ring. read/write accessible. these bits are unaffected by h_reset, s_reset, or stop. )? ( '' bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 badru contains the upper 16 bits of the base address of the receive ring. read/write accessible. these bits are unaffected by h_reset, s_reset, or stop. ,- 2? bit name description 31-0 res reserved locations. written as zeros and read as undefined. 4? ! <8 bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 badxl contains the lower 16 bits of the base address of the transmit ring. read/write accessible. these bits are unaffected by h_reset, s_reset, or stop. ? ! '' bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 badxu contains the upper 16 bits of the base address of the transmit ring. 188 am79c976 8/01/00 preliminary read/write accessible. these bits are unaffected by h_reset, s_reset, or stop. -",? bit name description 31-0 res reserved locations. written as zeros and read as undefined. "/? ! 0 bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 txpollint transmit polling interval. this register contains the time that the am79c976 controller will wait be- tween successive polling opera- tions. the txpollint value is expressed as the two ? s comple- ment of the desired interval, where each bit of txpollint represents 1 pci clock period. txpollint[3:0] are ignored. (txpollint[16] is implied to be a one, so txpollint[15] is sig- nificant and does not represent the sign of the two ? s complement txpollint value.) the default value of this register is 0000h. this corresponds to a polling interval of 65,536 clock periods (1.966 ms when clk = 33 mhz). setting the init bit starts an ini- tialization process that sets tx- pollint to its default value. if the user wants to program a val- ue for txpollint other than the default, then he must change the value after the initialization se- quence has completed. if the user does not use the initial- ization block to initialize the am79c976 device, but instead, chooses to write directly to each of the registers that are involved in the init operation, then it is im- perative that the user also writes an acceptable value to csr47 as part of the alternative initialization sequence. read/write accessible. these bits are unaffected by h_reset, s_reset, or stop. "1? bit name description 31-0 res reserved locations. written as zeros and read as undefined. "2?+ 0 bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 chpollint chain polling interval. this regis- ter contains the time that the am79c976 controller will wait be- tween successive polling opera- tions when the buffer management unit is in the middle of a buffer chaining operation. the chpollint value is ex- pressed as the two ? s complement of the desired interval, where each bit of chpollint approxi- mately represents one pci clock time period. chpollint[3:0] are ignored. (chpollint[16] is im- plied to be a 1, so chpol- lint[15] is significant and does not represent the sign of the two ? s complement chpollint value.) the default value of this register is 0000h. this corresponds to a polling interval of 65,536 clock periods (1.966 ms when clk = 33 mhz). setting the init bit starts an ini- tialization process that sets chpollint to its default value. if the user wants to program a value for chpollint other than the default, then he must change the value after the initialization sequence has completed. if the user does not use the initial- ization block to initialize the am79c976 device, but instead, chooses to write directly to each of the registers that are involved in the init operation, then it is im- perative that the user also writes an acceptable value to csr49 as 8/01/00 am79c976 189 preliminary part of the alternative initialization sequence. read/write accessible. these bits are unaffected by h_reset, s_reset, or stop. )4-)/? bit name description 31-0 res reserved locations. written as zeros and read as undefined. )1?8$ this register is an alias of the location bcr20. accesses to and from this register are equivalent to accesses to bcr20. bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-11 res reserved locations. written as zeros and read as undefined. 10 aperren obsolete function. writing has no effect. read as undefined. 9 res reserved locations. written as zeros and read as undefined. 8 ssize32 software size 32 bits. when set, this bit indicates that the am79c976 controller utilizes 32- bit software structures for the ini- tialization block and the transmit and receive descriptor entries. when cleared, this bit indicates that the am79c976 controller uti- lizes 16-bit software structures for the initialization block and the transmit and receive descriptor entries. in this mode, the am79c976 controller is back- wards compatible with the am7990 lance and am79c960 pcnet-isa controllers. the value of ssize32 is deter- mined by the am79c976 control- ler according to the setting of the software style (swstyle, bits 7-0 of this register). ssize32 is read only; write oper- ations will be ignored. ssize32 will be cleared after h_reset (since swstyle defaults to 0) and is not affected by s_reset or stop. if ssize32 is reset, then bits iadr[31:24] of csr2 will be used to generate values for the upper 8 bits of the 32-bit address bus during master accesses initi- ated by the am79c976 controller. this action is required, since the 16-bit software structures speci- fied by the ssize32 = 0 setting will yield only 24 bits of address for the am79c976 controller bus master accesses. if ssize32 is set, then the soft- ware structures that are common to the am79c976 controller and the host system will supply a full 32 bits for each address pointer that is needed by the am79c976 controller for performing master accesses. the value of the ssize32 bit has no effect on the drive of the upper 8 address bits. the upper 8 ad- dress pins are always driven, re- gardless of the state of the ssize32 bit. note that the setting of the ssize32 bit has no effect on the defined width for i/o resources. i/o resource width is determined by the state of the dwio bit (bcr18, bit 7). 7-0 swstyle software style register. the val- ue in this register determines the style of register and memory re- sources that shall be used by the am79c976 controller. the soft- ware style selection will affect the interpretation of a few bits within the csr space, the order of the descriptor entries and the width of the descriptors and initializa- tion block entries. all am79c976 controller csr bits and bcr bits and all descrip- tor, buffer, and initialization block entries not cited in table 85 are unaffected by the software style selection and are, therefore, al- ways fully functional as specified in the csr and bcr sections. 190 am79c976 8/01/00 preliminary read/write accessible. the sw- style register will contain the value 00h following h_reset and will be unaffected by s_reset or stop. table 85. software styles swstyle [7:0] style name ssize32 initialization block entries descriptor ring entries 00h lance/ pcnet-isa controller 0 16-bit software structures, non-burst or burst access 16-bit software structures, non-burst access only 01h res 1 res res 02h pcnet-pci controller 1 32-bit software structures, non-burst or burst access 32-bit software structures, non-burst access only 03h pcnet-pci controller 1 32-bit software structures, non-burst or burst access 32-bit software structures, non-burst or burst access 04h vlan 1 not used 32-bit software structures, non-burst or burst access 05h 64-bit address 1 not used 32-bit software structures, 32-byte descriptors, non- burst or burst access all other reserved undefined undefined undefined 8/01/00 am79c976 191 preliminary )2-/)? bit name description 31-0 res reserved locations. written as zeros and read as undefined. /,?( < + bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 rcvrl receive ring length. contains the two ? s complement of the re- ceive descriptor ring length. this register is initialized during the optional am79c976 controller ini- tialization routine based on the value in the rlen field of the ini- tialization block. however, this register can be manually altered. the actual receive ring length is defined by the current value in this register. the ring length can be defined as any value from 1 to 65535. read/write accessible. these bits are unaffected by h_reset, s_reset, or stop. //? bit name description 31-0 res reserved locations. written as zeros and read as undefined. /1? ! < + bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 xmtrl transmit ring length. contains the two ? s complement of the transmit descriptor ring length. this register is initialized during the optional am79c976 control- ler initialization routine based on the value in the tlen field of the initialization block. however, this register can be manually altered. the actual transmit ring length is defined by the current value in this register. the ring length can be defined as any value from 1 to 65535. read/write accessible. these bits are unaffected by h_reset, s_reset, or stop. /2? bit name description 31-0 res reserved locations. written as zeros and read as undefined. 14?*# + + bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-14 res reserved locations. written as zeros and read as undefined. 13-12 rcvfw[1:0]receive fifo watermark. rcvfw controls the point at which receive dma is requested in relation to the number of re- ceived bytes in the receive fifo. rcvfw specifies the num- ber of bytes which must be present (once the frame has been verified as a non-runt) be- fore receive dma is requested. note however that, if the network interface is operating in half-du- plex mode, in order for receive dma to be performed for a new frame, at least 64 bytes must have been received. this effec- tively avoids having to react to re- ceive frames which are runts or suffer a collision during the slot time (512 bit times). if the runt packet accept feature is enabled or if the network interface is oper- ating in full-duplex mode, receive dma will be requested as soon as either the rcvfw threshold is reached, or a complete valid re- ceive frame is detected (regard- less of length). when the full duplex runt packet accept dis- able (fdrpad) bit (bcr9, bit 2) is set and the am79c976 control- ler is in full-duplex mode, in order for receive dma to be performed for a new frame, at least 64 bytes must have been received. this effectively disables the runt pack- et accept feature in full duplex. 192 am79c976 8/01/00 preliminary table 86. receive watermark programming read/write accessible. rcvfw[1:0] is set to a value of 01b (64 bytes) after h_reset or s_reset and is unaffected by stop. 11-10 xmtsp[1:0] transmit start point. xmtsp controls the point at which pre- amble transmission attempts to commence in relation to the num- ber of bytes written to the mac transmit fifo for the current transmit frame. when the entire frame is in the mac transmit fifo, transmission will start re- gardless of the value in xmtsp. if the network interface is operat- ing in half-duplex mode, regard- less of xmtsp, the fifo will not internally overwrite its data until at least 64 bytes (or the entire frame if shorter than 64 bytes) have been transmitted onto the network. this ensures that for collisions within the slot time win- dow, transmit data need not be rewritten to the transmit fifo, and retries will be handled auton- omously by the mac. if the dis- able retry feature is enabled, or if the network is operating in full- duplex mode, the am79c976 controller can overwrite the be- ginning of the frame as soon as the data is transmitted, because no collision handling is required in these modes. note that when the no underflow (nouflo) bit (bcr18, bit 11) is set to 1, there is the additional re- striction that the complete trans- mit frame must be dma ? d into the am79c976 controller and reside within the mac transmit fifo. this mode is useful in a system where high latencies cannot be avoided. see table 87. read/write accessible. xmtsp is set to a value of 01b (64 bytes) after h_reset or s_reset and is unaffected by stop. table 87. transmit start point programming 9-8 xmtfw[1:0] transmit fifo watermark. xmt- fw specifies the point at which transmit dma is requested, based upon the number of bytes that could be written to the trans- mit fifo without fifo overflow. transmit dma is requested at any time when the number of bytes specified by xmtfw could be written to the fifo without causing transmit fifo overflow, and the internal state machine has reached a point where the transmit fifo is checked to de- termine if dma servicing is re- quired. see table 88. table 88. transmit watermark programming read/write accessible. xmtfw is set to a value of 00b (16 bytes) after h_reset or s_reset and is unaffected by stop. 7-0 dmatc[7:0]obsolete function. writing has no effect. read as undefined. rcvfw[1:0] bytes received 00 48 01 64 10 128 11 256 xmtsp[1:0] nouflo bytes written 00 0 16 01 0 64 10 0 128 11 0 full frame xx 1 full frame xmtfw[1:0] bytes available 00 16 01 64 10 128 11 256 8/01/00 am79c976 193 preliminary 1-1/? bit name description 31-0 res reserved locations. written as zeros and read as undefined. 11?+ '* <8 bit name description 31-16 res reserved locations. read as undefined. 15-12 partidl lower 4 bits of the am79c976 controller part number, i.e. 1000b (8h). partidn and partidl comprise the 16-bit code for the am79c976 controller, which is 0010 0110 0010 1000b (2628h). this register is exactly the same as the device id register in the jtag description. however, this part number is different from that stored in the device id register in the pci configuration space. partidl is read only. write op- erations are ignored. 11-1 manfid manufacturer id. the 11-bit man- ufacturer code for amd is 00000000001b. this code is per the jedec publication 106-a. note that this code is not the same as the vendor id in the pci configuration space. manfid is read only. write oper- ations are ignored. 0 one always a logic 1. one is read only. write opera- tions are ignored. 12?+ '* '' bit name description 31-16 res reserved locations. read as un- defined. 15-12 ver version. this 4-bit pattern is sili- con-revision dependent. ver is read only. write opera- tions are ignored. 11-0 partidu upper 12 bits of the am79c976 controller part number, i.e., 0010 0110 0010b (262h). partidu is read only. write op- erations are ignored. 24-22? bit name description 31-0 res reserved locations. written as zeros and read as undefined. 44? ! bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 merrto obsolete function. writing has no effect. read as undefined. 4-? bit name description 31-0 res reserved locations. written as zeros and read as undefined. ?# ! bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 mfc obsolete function. replaced by mib counter. writing has no ef- fect. read as undefined. ? bit name description 31-0 res reserved locations. written as zeros and read as undefined. "?( bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 rcc obsolete function. replaced by mib counter. writing has no ef- fect. read as undefined. )? bit name description 194 am79c976 8/01/00 preliminary 31-0 res reserved locations. written as zeros and read as undefined. ,? 808# note: bits 10-0 in this register are programmable through the eeprom. bit name description 31-11 res reserved locations. written as zeros and read as undefined. 10 pme_en_ovr pme_en overwrite. when this bit is set and the mpmat or lc- det bit is set, the pme pin will al- ways be asserted regardless of the state of pme_en bit. read/write accessible. cleared by h_reset and is not affected by s_reset or setting the stop bit. 9 lcdet link change detected. this bit is set when the mii auto-polling log- ic detects a change in link status and the lcmode bit is set. this bit can be cleared to 0 either by writing 1 to csr116, bit 9 or by writing 1 to stat0, bit 10. lcdet is cleared when power is initially applied (por). read/write accessible. 8 lcmode link change wake-up mode. when this bit is set to 1, the lc- det bit gets set when the mii auto polling logic detects a link change. read/write accessible. cleared by h_reset and is not affected by s_reset or setting the stop bit. 7 pmat pattern matched. this bit is set when the pmmode bit is set and an onnow pattern match occurs. this bit can be cleared to 0 either by writing 0 to csr116, bit 7 or by writing 1 to stat0, bit 12. pmat is cleared when power is initially applied (por). read/write accessible. 6 empplba magic packet physical logical broadcast accept. if both emp- plba and mpplba (csr5, bit 5) are at their default value of 0, the am79c976 controller will only de- tect a magic packet frame if the destination address of the packet matches the content of the physi- cal address register (padr). if ei- ther empplba or mpplba is set to 1, the destination address of the magic packet frame can be unicast, multicast, or broadcast. note that the setting of emppl- ba and mpplba only affects the address detection of the magic packet frame. the magic packet frame ? s data sequence must be made up of 16 consecutive phys- ical addresses (padr[47:0]) re- gardless of what kind of destination address it has. read/write accessible. empplba is set to 0 by h_reset or s_reset and is not affected by setting the stop bit. 5 mpmat magic packet match. this bit is set when pcnet-fast+ detects a magic packet while it is in the magic packet mode. this bit can be cleared to 0 either by writing 0 to csr116, bit 5 or by writing 1 to stat0, bit 11. mpmat is cleared when power is initially applied (por). read/write accessible. 4 mppen magic packet pin enable. when this bit is set, the device enters the magic packet mode when the pg input goes low or mpen bit (csr5, bit 2) gets set to 1. this bit is or ? ed with mpen (csr5, bit 2). read/write accessible. cleared by h_reset and is not affected 8/01/00 am79c976 195 preliminary by s_reset or setting the stop bit. 3 rwu_driver rwu driver type. if this bit is set to 1, rwu is a totem pole driver; otherwise rwu is an open drain output. read/write accessible. cleared by h_reset and is not affected by s_reset or setting the stop bit. 2 rwu_gate rwu gate control. if this bit is set, rwu is forced to the high im- pedance state when pg is low, regardless of the state of the mpmat and lcdet bits. read/write accessible. cleared by h_reset and is not affected by s_reset or setting the stop bit. 1 rwu_pol rwu pin polarity. if rwu_pol is set to 1, the rwu pin is normal- ly high and asserts low; other- wise, rwu is normally low and asserts high. read/write accessible. cleared by h_reset and is not affected by s_reset or setting the stop bit. 0 rst_pol phy_rst pin polarity. if the phy_pol is set to 1, the phy_rst pin is active low; oth- erwise, phy_rst is active high. read/write accessible. cleared by h_reset and is not affected by s_reset or setting the stop bit. /- ? bit name description 31-0 res reserved locations. written as zeros and read as undefined. ?( bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-2 res reserved locations. written as zeros and read as undefined. 0 rcvalgn receive packet align. when set, this bit forces the data field of iso 8802-3 (ieee/ansi 802.3) pack- ets to align to 0 mod 4 address boundaries (i.e., dword aligned addresses). it is important to note that this feature will only function correctly if all receive buffer boundaries are dword aligned and all receive buffers have 0 mod 4 lengths. in order to ac- complish the data alignment, the am79c976 controller simply in- serts two bytes of random data at the beginning of the receive packet (i.e., before the iso 8802- 3 (ieee/ansi 802.3) destination address field). the mcnt field reported to the receive descriptor will not include the extra two bytes. read/write accessible. rcvalgn is cleared by h_reset or s_reset and is not affected by stop. ? bit name description 31-0 res reserved locations. written as zeros and read as undefined. "? this register is used to place the am79c976 controller into various test modes. the runt packet accept is the only user accessible test mode. all other test modes are for amd internal use only. bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-4 res reserved locations. written as zeros and read as undefined. 3 rpa runt packet accept. this bit forc- es the am79c976 controller to accept runt packets (packets shorter than 64 bytes). the minimum packet size that can be received is 12 bytes. 196 am79c976 8/01/00 preliminary read/write accessible. rpa is cleared by h_reset or s_reset and is not affected by stop. 2-0 res reserved locations. written as zeros and read as undefined. )?#%+( bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-8 ipg inter packet gap. this value indi- cates the minimum number of network bit times after the end of a frame that the transmitter will wait before it starts transmitting another frame. in half-duplex mode the end of the frame is de- termined by crs, while in full-du- plex mode the end of the frame is determined by tx_en. the ipg value can be adjusted to com- pensate for delays through the external phy device. ipg should be programmed to the nearest nibble. the two least significant bits are ignored. for example, programming ipg to 63h has the same effect as pro- gramming it to 60h. caution : use this parameter with care. by lowering the ipg below the ieee 802.3 standard 96 bit times, the am79c976 con- troller can interrupt normal net- work behavior. read/write accessible. ipg is set to 60h (96 bit times) by h_reset or s_reset and is not affected by stop. 7-0 ifs1 interframespacingpart1. changing ifs1 allows the user to program the value of the inter- frame-spacepart1 timing. the am79c976 controller sets the de- fault value at 60 bit times (3ch). see the subsection on medium allocation in the section media access management for more details. the equation for setting ifs1 when ipg 96 bit times is: ifs1 = ipg - 36 bit times ipg should be programmed to the nearest nibble. the two least significant bits are ignored. for example, programming ipg to 63h has the same effect as pro- gramming it to 60h. read/write accessible. ifs1 is set to 3ch (60 bit times) by h_reset or s_reset and is not affected by stop. 8/01/00 am79c976 197 preliminary bus configuration registers the bus configuration registers (bcrs) are included for compatibility with older pcnet family software all bcr functions can be accessed more efficiently through the memory-mapped registers. bcrs are used to program the configuration of the bus interface and other special features of the am79c976 controller that are not related to the ieee 8802-3 mac functions. the bcrs are accessed by first setting the appropriate rap value and then by performing a slave access to the bdp. see table 89. all bcr registers are 16 bits in width in word i/o mode (dwio = 0, bcr18, bit 7) and 32 bits in width in dword i/o mode (dwio = 1). the upper 16 bits of all bcr reg- isters is undefined when in dword i/o mode. these bits should be written as zeros and should be treated as undefined when read. the default value given for any bcr is the value in the register after h_reset. some of these values may be changed shortly after h_reset when the contents of the external eeprom is automatically read in. none of the bcr register val- ues are affected by the assertion of the stop bit or s_reset. note that several registers have no default value. bcr0, bcr1, bcr3, bcr8, bcr10-17, and bcr21 are reserved and have undefined values. bcr2 and bcr34 are not observable without first being pro- grammed through the eeprom read operation or a user register write operation. bcr0, bcr1, bcr16, bcr17, and bcr21 are regis- ters that are used by other devices in the pcnet family. writing to these registers have no effect on the opera- tion of the am79c976 controller. writes to those registers marked as ? reserved ? will have no effect. reads from these locations will produce undefined values. table 89. bcr registers rap mnemonic default name programmability user eeprom 0 msrda 0005h reserved no no 1 mswra 0005h reserved no no 2 mc 0000h miscellaneous configuration yes yes 3 reserved n/a reserved no no 4 led0 00c0h led0 status yes yes 5 led1 0094h led1 status yes yes 6 led2 1080h led2 status yes yes 7 led3 0081h led3 status yes yes 8 reserved n/a reserved no no 9 fdc 0004h full-duplex control yes yes 10-15 reserved n/a reserved no no 16 iobasel n/a reserved no no 17 iobaseu n/a reserved no no 18 bsbc 9000h burst and bus control yes yes 19 eecas 0000h eeprom control and status yes no 20 sws 0000h software style yes no 21 reserved n/a reserved no no 22 pcilat 1818h pci latency yes yes 23 pcisid 0000h pci subsystem id no yes 24 pcisvid 0000h pci subsystem vendor id no yes 198 am79c976 8/01/00 preliminary 4?# #( bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 msrda reserved locations. after h_reset, the value in this regis- ter will be 0005h. the setting of this register has no effect on any am79c976 controller function. it is only included for software com- patibility with other pcnet family devices. read always. msrda is read only. write operations have no ef- fect. ?# # ( bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 mswra reserved locations. after h_reset, the value in this regis- ter will be 0005h. the setting of this register has no effect on any am79c976 controller function. it is only included for software com- patibility with other pcnet family devices. read always. mswra is read only. write operations have no ef- fect. 25 sramsiz 0000h sram size yes yes 26 sramb 0000h sram boundary yes yes 27 reserved n/a reserved no no 28 ebaddrl n/a expansion bus address lower yes no 29 ebaddru n/a expansion bus address upper yes no 30 ebdr n/a expansion bus data port yes no 31 stval ffffh software timer value yes no 32 miicas 0400h mii control and status yes yes 33 miiaddr n/a mii address yes yes 34 miimdr n/a mii management data yes no 35 pcivid 1022h pci vendor id no yes 36 pmc_a c802h pci power management capabilities (pmc) alias register no yes 37 data0 0000h pci data register zero alias register no yes 38 data1 0000h pci data register one alias register no yes rap mnemonic default name programmability user eeprom 39 data2 0000h pci data register two alias register no yes 40 data3 0000h pci data register three alias register no yes 41 data4 0000h pci data register four alias register no yes 42 data5 0000h pci data register five alias register no yes 43 data6 0000h pci data register six alias register no yes 44 data7 0000h pci data register seven alias register no yes 45 pmr1 n/a pattern matching register 1 yes no 46 pmr2 n/a pattern matching register 2 yes no 47 pmr3 n/a pattern matching register 3 yes no 8/01/00 am79c976 199 preliminary ?# ( note: bits 15-0 in this register are programmable through the eeprom. bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-13 res reserved locations. written and read as zeros. 12 ledpe led program enable. when ledpe is set to 1, programming of the led0 (bcr4), led1 (bcr5), led2 (bcr6), and led3 (bcr7) registers is en- abled. when ledpe is cleared to 0, programming of led0 (bcr4), led1 (bcr5), led2 (bcr6), and led3 (bcr7) registers is disabled. writes to those regis- ters will be ignored. read/write accessible. ledpe is cleared to 0 by h_reset and is unaffected by s_reset or by setting the stop bit. 11-9 res reserved locations. written and read as zeros. 8 apromwe address prom write enable. the am79c976 controller con- tains a shadow ram on board for storage of the first 16 bytes load- ed from the serial eeprom. accesses to address prom i/o resources will be directed to- ward this ram. when aprom- we is set to 1, then write access to the shadow ram will be en- abled. read/write accessible. aprom- we is cleared to 0 by h_reset and is unaffected by s_reset or by setting the stop bit. 7 intlevel interrupt level. this bit allows the interrupt output signals to be pro- grammed for level or edge- sensitive applications. when intlevel is cleared to 0, the inta pin is configured for level-sensitive applications. in this mode, an interrupt request is signaled by a low level driven on the inta pin by the am79c976 controller. when the interrupt is cleared, the inta pin is tri-stated by the am79c976 controller and allowed to be pulled to a high lev- el by an external pull-up device. this mode is intended for systems which allow the interrupt signal to be shared by multiple devices. when intlevel is set to 1, the inta pin is configured for edge- sensitive applications. in this mode, an interrupt request is sig- naled by a high level driven on the inta pin by the am79c976 controller. when the interrupt is cleared, the inta pin is driven to a low level by the am79c976 controller. this mode is intended for systems that do not allow interrupt channels to be shared by multiple devices. intlevel should not be set to 1 when the am79c976 controller is used in a pci bus application. read/write accessible. intlev- el is cleared to 0 by h_reset and is unaffected by s_reset or by setting the stop bit. 6-4 res reserved locations. written as zeros and read as undefined. 3 eadisel obsolete function. writing has no effect. read as undefined. 2 res reserved location. written and read as zeros. 1 asel obsolete function. writing has no effect. read as undefined. 0 res reserved location. written and read as zeros. "?<%*4 bcr4 controls the function(s) that the led0 pin dis- plays. multiple functions can be simultaneously en- abled on this led pin. the led display will indicate the logical or of the enabled functions. bcr4 defaults to link status (lnkst) with pulse stretcher enabled (pse = 1) and is fully programmable. note: when ledpe (bcr2, bit 12) is set to 1, pro- gramming of the led0 status register is enabled. 200 am79c976 8/01/00 preliminary when ledpe is cleared to 0, programming of the led0 register is disabled. writes to this register will be ignored. note: bits 15-0 in this register are programmable through the eeprom. bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15 ledout this bit indicates the current (non-stretched) value of the led output pin. a value of 1 in this bit indicates that the or of the enabled signals is true. the logical value of the ledout status signal is determined by the settings of the individual status enable bits of the led register (bits 8 and 6-0). this bit is read only; writes have no effect. ledout is unaffected by h_reset, s_reset, or stop. 14 ledpol led polarity. when this bit has the value 0, then the led pin will be driven to a low level whenev- er the or of the enabled signals is true, and the led pin will be disabled and allowed to float high whenever the or of the enabled signals is false (i.e., the led out- put will be an open drain output and the output value will be the inverse of the ledout status bit). when this bit has the value 1, then the led pin will be driven to a high level whenever the or of the enabled signals is true, and the led pin will be driven to a low level whenever the or of the enabled signals is false (i.e., the led output will be a totem pole output and the output value will be the same polarity as the ledout status bit.). the setting of this bit will not ef- fect the polarity of the ledout bit for this register. read/write accessible. ledpol is cleared by h_reset and is not affected by s_reset or set- ting the stop bit. 13 leddis led disable. this bit is used to disable the led output. when leddis has the value 1, then the led output will always be dis- abled. when leddis has the val- ue 0, then the led output value will be governed by the ledout and ledpol values. read/write accessible. leddis is cleared by h_reset and is not affected by s_reset or set- ting the stop bit. 12 100e 100 mbps enable. when this bit is set to 1, a value of 1 is passed to the ledout bit in this register when the am79c976 controller is operating at 100 mbps mode. read/write accessible. 100e is cleared by h_reset and is not affected by s_reset or setting the stop bit. 11-10 res reserved locations. written and read as zeros. 9 mpse magic packet status enable. when this bit is set to 1, a value of 1 is passed to the ledout bit in this register when magic pack- et frame mode is enabled and a magic packet frame is detected on the network. read/write accessible. mpse is cleared by h_reset and is not affected by s_reset or setting the stop bit. 8 fdlse full-duplex link status enable. indicates the full-duplex link test status. when this bit is set, a value of 1 is passed to the led- out signal when the am79c976 controller is functioning in a link pass state and full-duplex opera- tion is enabled. when the am79c976 controller is not func- tioning in a link pass state with full-duplex operation being en- abled, a value of 0 is passed to the ledout signal. 8/01/00 am79c976 201 preliminary read/write accessible. fdlse is cleared by h_reset and is not affected by s_reset or setting the stop bit. 7 pse pulse stretcher enable. when this bit is set, the led illumination time is extended for each new oc- currence of the enabled function for this led output. a value of 0 disables the pulse stretcher. read/write accessible. pse is set to 1 by h_reset and is not affected by s_reset or setting the stop bit. 6 lnkse link status enable. when this bit is set, a value of 1 will be passed to the ledout bit in this register when in link pass state. read/write accessible. lnkse is set to 1 by h_reset and is not affected by s_reset or setting the stop bit. 5 rcvme receive match status enable. when this bit is set, a value of 1 is passed to the ledout bit in this register when there is receive ac- tivity on the network that has passed the address match func- tion for this node. all address matching modes are included: physical, logical filtering, broad- cast and promiscuous. read/write accessible. rcvme is cleared by h_reset and is not affected by s_reset or set- ting the stop bit. 4 xmte transmit status enable. when this bit is set, a value of 1 is passed to the ledout bit in this register when there is transmit activity on the network. read/write accessible. xmte is cleared by h_reset and is not affected by s_reset or setting the stop bit. 3 res reserved location. written and read as zeros. 2 rcve receive status enable. when this bit is set, a value of 1 is passed to the ledout bit in this register when there is receive ac- tivity on the network. read/write accessible. rcve is cleared by h_reset and is not affected by s_reset or setting the stop bit. 1 sfbde start frame/byte delimiter en- able. when this bit is set, a value of 1 is passed to the ledout bit in this register when the rxd[3:0] pins are presenting the least sig- nificant nibble of valid frame data. read/write accessible. rcve is cleared by h_reset and is not affected by s_reset or setting the stop bit. 0 cole collision status enable. when this bit is set, a value of 1 is passed to the ledout bit in this register when there is collision activity on the network. read/write accessible. cole is cleared by h_reset and is not affected by s_reset or setting the stop bit. )?<%* bcr5 controls the function(s) that the led1 pin dis- plays. multiple functions can be simultaneously en- abled on this led pin. the led display will indicate the logical or of the enabled functions. bcr5 defaults to transmit or receive activity (xmte = 1 and rcve = 1) with pulse stretcher enabled (pse = 1) and is fully pro- grammable. note: when ledpe (bcr2, bit 12) is set to 1, pro- gramming of the led1 status register is enabled. when ledpe is cleared to 0, programming of the led1 register is disabled. writes to this register will be ignored. note: bits 15-0 in this register are programmable through the eeprom. bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15 ledout this bit indicates the current (non-stretched) value of the led output pin. a value of 1 in this bit indicates that the or of the en- abled signals is true. 202 am79c976 8/01/00 preliminary the logical value of the ledout status signal is determined by the settings of the individual status enable bits of the led register (bits 8 and 6-0). this bit is read only, writes have no effect. ledout is unaffected by h_reset, s_reset, or stop. 14 ledpol led polarity. when this bit has the value 0, then the led pin will be driven to a low level whenev- er the or of the enabled signals is true, and the led pin will be disabled and allowed to float high whenever the or of the enabled signals is false (i.e., the led out- put will be an open drain output and the output value will be the inverse of the ledout status bit). when this bit has the value 1, then the led pin will be driven to a high level whenever the or of the enabled signals is true, and the led pin will be driven to a low level whenever the or of the enabled signals is false (i.e., the led output will be a totem pole output and the output value will be the same polarity as the ledout status bit). the setting of this bit will not ef- fect the polarity of the ledout bit for this register. read/write accessible. ledpol is cleared by h_reset and is not affected by s_reset or set- ting the stop bit. 13 leddis led disable. this bit is used to disable the led output. when leddis has the value 1, then the led output will always be dis- abled. when leddis has the val- ue 0, then the led output value will be governed by the ledout and ledpol values. read/write accessible. leddis is cleared by h_reset and is not affected by s_reset or set- ting the stop bit. 12 100e 100 mbps enable. when this bit is set to 1, a value of 1 is passed to the ledout bit in this register when the am79c976 controller is operating at 100 mbps mode. read/write accessible. 100e is cleared by h_reset and is not affected by s_reset or setting the stop bit. 11-10 res reserved locations. written and read as zeros. 9 mpse magic packet status enable. when this bit is set to 1, a value of 1 is passed to the ledout bit in this register when magic pack- et mode is enabled and a magic packet frame is detected on the network. read/write accessible. mpse is cleared by h_reset and is not affected by s_reset or setting the stop bit. 8 fdlse full-duplex link status enable. indicates the full-duplex link test status. when this bit is set, a value of 1 is passed to the led- out signal when the am79c976 controller is functioning in a link pass state and full-duplex opera- tion is enabled. when the am79c976 controller is not func- tioning in a link pass state with full-duplex operation being en- abled, a value of 0 is passed to the ledout signal. read/write accessible. fdlse is cleared by h_reset and is not affected by s_reset or setting the stop bit. 7 pse pulse stretcher enable. when this bit is set, the led illumination time is extended for each new oc- currence of the enabled function for this led output. a value of 0 disables the pulse stretcher. read/write accessible. pse is set to 1 by h_reset and is not affected by s_reset or setting the stop bit. 8/01/00 am79c976 203 preliminary 6 lnkse link status enable. when this bit is set, a value of 1 will be passed to the ledout bit in this register in link pass state. read/write accessible. lnkse is cleared by h_reset and is not affected by s_reset or set- ting the stop bit. 5 rcvme receive match status enable. when this bit is set, a value of 1 is passed to the ledout bit in this register when there is receive ac- tivity on the network that has passed the address match func- tion for this node. all address matching modes are included: physical, logical filtering, broad- cast, and promiscuous. read/write accessible. rcvme is cleared by h_reset and is not affected by s_reset or set- ting the stop bit. 4 xmte transmit status enable. when this bit is set, a value of 1 is passed to the ledout bit in this register when there is transmit activity on the network. read/write accessible. xmte is set to 1 by h_reset and is not affected by s_reset or setting the stop bit. 3 res reserved location. written and read as zeros. 2 rcve receive status enable. when this bit is set, a value of 1 is passed to the ledout bit in this register when there is receive ac- tivity on the network. read/write accessible. rcve is set to 1 by h_reset and is not affected by s_reset or setting the stop bit. 1 sfbde start frame/byte delimiter en- able. when this bit is set, a value of 1 is passed to the ledout bit in this register when the rxd[3:0] pins are presenting the least sig- nificant nibble of valid frame data. read/write accessible. rcve is cleared by h_reset and is not affected by s_reset or setting the stop bit. 0 cole collision status enable. when this bit is set, a value of 1 is passed to the ledout bit in this register when there is collision activity on the network. read/write accessible. cole is cleared by h_reset and is not affected by s_reset or setting the stop bit. ,?<%* bcr6 controls the function(s) that the led2 pin dis- plays. multiple functions can be simultaneously enabled on this led pin. the led display will indicate the logical or of the enabled functions. bcr5 defaults to 100 mb/ s speed indication (100e = 1) with pulse stretcher en- abled (pse = 1). note: when ledpe (bcr2, bit 12) is set to 1, pro- gramming of the led2 status register is enabled. when ledpe is cleared to 0, programming of the led2 register is disabled. writes to this register will be ignored. note: bits 15-0 in this register are programmable through the eeprom pread operation. bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15 ledout this bit indicates the current (non-stretched) value of the led output pin. a value of 1 in this bit indicates that the or of the en- abled signals is true. the logical value of the ledout status signal is determined by the settings of the individual status enable bits of the led register (bits 8 and 6-0). this bit is read only; writes have no effect. ledout is unaffected by h_reset, s_reset, or stop. 14 ledpol led polarity. when this bit has the value 0, the led pin will be driven to a low level whenever the or of the enabled signals is true. the led pin will be disabled 204 am79c976 8/01/00 preliminary and allowed to float high whenev- er the or of the enabled signals is false (i.e., the led output will be an open drain output and the output value will be the inverse of the ledout status bit). when this bit has the value 1, the led pin will be driven to a high level whenever the or of the en- abled signals is true. the led pin will be driven to a low level whenever the or of the enabled signals is false (i.e., the led out- put will be a totem pole output and the output value will be the same polarity as the ledout status bit). the setting of this bit will not ef- fect the polarity of the ledout bit for this register. read/write accessible. ledpol is cleared by h_reset and is not affected by s_reset or set- ting the stop bit. 13 leddis led disable. this bit is used to disable the led output. when leddis has the value 1, then the led output will always be dis- abled. when leddis has the val- ue 0, then the led output value will be governed by the ledout and ledpol values. read/write accessible. leddis is cleared by h_reset and is not affected by s_reset or set- ting the stop bit. 12 100e 100 mbps enable. when this bit is set to 1, a value of 1 is passed to the ledout bit in this register when the am79c976 controller is operating at 100 mbps mode. read/write accessible. 100e is set to 1 by h_reset and is not affected by s_reset or setting the stop bit. 11-10 res reserved locations. written and read as zeros. 9 mpse magic packet status enable. when this bit is set to 1, a value of 1 is passed to the ledout bit in this register when magic pack- et frame mode is enabled and a magic packet frame is detected on the network. read/write accessible. mpse is cleared by h_reset and is not affected by s_reset or setting the stop bit. 8 fdlse full-duplex link status enable. indicates the full-duplex link test status. when this bit is set, a value of 1 is passed to the led- out signal when the am79c976 controller is functioning in a link pass state and full-duplex opera- tion is enabled. when the am79c976 controller is not func- tioning in a link pass state with full-duplex operation being en- abled, a value of 0 is passed to the ledout signal. read/write accessible. fdlse is cleared by h_reset and is not affected by s_reset or setting the stop bit. 7 pse pulse stretcher enable. when this bit is set, the led illumination time is extended for each new oc- currence of the enabled function for this led output. a value of 0 disables the pulse stretcher. read/write accessible. pse is set to 1 by h_reset and is not affected by s_reset or setting the stop bit. 6 lnkse link status enable. when this bit is set, a value of 1 will be passed to the ledout bit in this register in link pass state. read/write accessible. lnkse is cleared by h_reset and is not affected by s_reset or setting the stop bit. 5 rcvme receive match status enable. when this bit is set, a value of 1 is passed to the ledout bit in this register when there is receive ac- tivity on the network that has passed the address match func- tion for this node. all address matching modes are included: 8/01/00 am79c976 205 preliminary physical, logical filtering, broad- cast, and promiscuous. read/write accessible. rcvme is cleared by h_reset and is not affected by s_reset or set- ting the stop bit. 4 xmte transmit status enable. when this bit is set, a value of 1 is passed to the ledout bit in this register when there is transmit activity on the network. read/write accessible. xmte is cleared by h_reset and is not affected by s_reset or setting the stop bit. 3 res reserved location. written and read as zeros. 2 rcve receive status enable. when this bit is set, a value of 1 is passed to the ledout bit in this register when there is receive ac- tivity on the network. read/write accessible. rcve is cleared by h_reset and is not affected by s_reset or setting the stop bit. 1 sfbde start frame/byte delimiter en- able. when this bit is set, a value of 1 is passed to the ledout bit in this register when the rxd[3:0] pins are presenting the least sig- nificant nibble of valid frame data. read/write accessible. rcve is cleared by h_reset and is not affected by s_reset or setting the stop bit. 0 cole collision status enable. when this bit is set, a value of 1 is passed to the ledout bit in this register when there is collision activity on the network. read/write accessible. cole is cleared by h_reset and is not affected by s_reset or setting the stop bit. /?<%* bcr7 controls the function(s) that the led3 pin dis- plays. multiple functions can be simultaneously enabled on this led pin. the led display will indicate the logical or of the enabled functions. bcr7 defaults to collision indication (cole = 1) with pulse stretcher enabled (pse = 1) and is fully programmable. note: when ledpe (bcr2, bit 12) is set to 1, pro- gramming of the led3 status register is enabled. when ledpe is cleared to 0, programming of the led3 register is disabled. writes to this register will be ignored. note: bits 15-0 in this register are programmable through the eeprom. bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15 ledout this bit indicates the current (non-stretched) value of the led output pin. a value of 1 in this bit indicates that the or of the en- abled signals is true. the logical value of the ledout status signal is determined by the settings of the individual status enable bits of the led register (bits 8 and 6-0). this bit is read only; writes have no effect. ledout is unaffected by h_reset, s_reset, or stop. 14 ledpol led polarity. when this bit has the value 0, the led pin will be driven to a low level whenever the or of the enabled signals is true. the led pin will be disabled and allowed to float high whenev- er the or of the enabled signals is false (i.e., the led output will be an open drain output and the output value will be the inverse of the ledout status bit). when this bit has the value 1, the led pin will be driven to a high level whenever the or of the en- abled signals is true. the led pin will be driven to a low level whenever the or of the enabled signals is false (i.e., the led out- put will be a totem pole output and the output value will be the 206 am79c976 8/01/00 preliminary same polarity as the ledout status bit). the setting of this bit will not ef- fect the polarity of the ledout bit for this register. read/write accessible. ledpol is cleared by h_reset and is not affected by s_reset or set- ting the stop bit. 13 leddis led disable. this bit is used to disable the led output. when leddis has the value 1, then the led output will always be dis- abled. when leddis has the val- ue 0, then the led output value will be governed by the ledout and ledpol values. read/write accessible. leddis is cleared by h_reset and is not affected by s_reset or set- ting the stop bit. 12 100e 100 mbps enable. when this bit is set to 1, a value of 1 is passed to the ledout bit in this register when the am79c976 controller is operating at 100 mbps mode. read/write accessible. 100e is cleared by h_reset and is not affected by s_reset or setting the stop bit. 11-10 res reserved locations. written and read as zeros. 9 mpse magic packet status enable. when this bit is set to 1, a value of 1 is passed to the ledout bit in this register when magic frame mode is enabled and a magic frame is detected on the network. read/write accessible. mpse is cleared by h_reset and is not affected by s_reset or setting the stop bit. 8 fdlse full-duplex link status enable. indicates the full-duplex link test status. when this bit is set, a value of 1 is passed to the led- out signal when the am79c976 controller is functioning in a link pass state and full-duplex opera- tion is enabled. when the am79c976 controller is not func- tioning in a link pass state with full-duplex operation being en- abled, a value of 0 is passed to the ledout signal. read/write accessible. fdlse is cleared by h_reset and is not affected by s_reset or setting the stop bit. 7 pse pulse stretcher enable. when this bit is set, the led illumination time is extended for each new oc- currence of the enabled function for this led output. a value of 0 disables the pulse stretcher. read/write accessible. pse is set to 1 by h_reset and is not affected by s_reset or setting the stop bit. 6 lnkse link status enable. when this bit is set, a value of 1 will be passed to the ledout bit in this register in link pass state. read/write accessible. lnkse is cleared by h_reset and is not affected by s_reset or set- ting the stop bit. 5 rcvme receive match status enable. when this bit is set, a value of 1 is passed to the ledout bit in this register when there is receive ac- tivity on the network that has passed the address match func- tion for this node. all address matching modes are included: physical, logical filtering, broad- cast, and promiscuous. read/write accessible. rcvme is cleared by h_reset and is not affected by s_reset or set- ting the stop bit. 4 xmte transmit status enable. when this bit is set, a value of 1 is passed to the ledout bit in this register when there is transmit activity on the network. read/write accessible. xmte is cleared by h_reset and is not 8/01/00 am79c976 207 preliminary affected by s_reset or setting the stop bit. 3 res reserved location. written and read as zeros. 2 rcve receive status enable. when this bit is set, a value of 1 is passed to the ledout bit in this register when there is receive ac- tivity on the network. read/write accessible. rcve is cleared by h_reset and is not affected by s_reset or setting the stop bit. 1 sfbde start frame/byte delimiter en- able. when this bit is set, a value of 1 is passed to the ledout bit in this register when the rxd[3:0] pins are presenting the least sig- nificant nibble of valid frame data. read/write accessible. rcve is cleared by h_reset and is not affected by s_reset or setting the stop bit. 0 cole collision status enable. when this bit is set, a value of 1 is passed to the ledout bit in this register when there is collision activity on the network. read/write accessible. cole is set to 1 by h_reset and is not affected by s_reset or setting the stop bit. 2?-*'& note: bits 15-0 in this register are programmable through the eeprom. bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-3 res reserved locations. written as zeros and read as undefined. 2 fdrpad full-duplex runt packet accept disable. when fdrpad is set to 1 and full-duplex mode is en- abled, the am79c976 controller will only receive frames that meet the minimum ethernet frame length of 64 bytes. receive dma will not start until at least 64 bytes or a complete frame have been received. when fdrpad is cleared to 0, the am79c976 con- troller will accept any frame of 12 bytes or greater, and receive dma will start according to the programming of the receive fifo watermark. read/write accessible. fdrpad is set to 1 by h_reset and is not affected by s_reset or by set- ting the stop bit. 1 res reserved locations. written as zeros and read as undefined. 0 fden full-duplex enable. fden con- trols whether full-duplex opera- tion is enabled. when fden is cleared and the auto-negotiation is disabled, full-duplex operation is not enabled and the am79c976 controller will always operate in the half-duplex mode. when fden is set, the am79c976 controller will operate in full-duplex mode when the mii port is enabled. do not set this bit when auto-negotiation is enabled . read/write accessible. fden is reset to 0 by h_reset, and is unaffected by s_reset and the stop bit. ,? <8 bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-5 iobasel reserved locations. after h_reset, the value of these bits will be undefined. the settings of these bits will have no effect on any am79c976 controller func- tion. it is only included for soft- ware compatibility with other pcnet family devices. read/write accessible. io- basel is not affected by s_reset or stop. 4-0 res reserved locations. written as zeros, read as undefined. 208 am79c976 8/01/00 preliminary /? '' bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 iobaseu reserved locations. after h_reset, the value in this regis- ter will be undefined. the settings of this register will have no effect on any am79c976 controller function. it is only included for software compatibility with other pcnet family devices. read/write accessible. io- baseu is not affected by s_reset or stop. 1? note: bits 15-0 in this register are programmable through the eeprom. bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-12 romtmg expansion rom timing. the val- ue of romtmg is used to tune the timing for all accesses to the external flash/eprom. romtmg defines the amount of time that a valid address is driven on the era[19:0] pins. the register value specifies delay in number of romclk cycles, where romclk is an internal clock signal that runs at one fourth the speed of erclk. note : programming romtng with a value of 0 is not permitted. to ensure adequate expansion rom setup time, romtmg should be set to 1 plus tacc / (romclk period), where tacc is the access time of the expan- sion rom device (flash or eprom). (the extra romclk cycle is added to account for the era[19:0] output delay from romclk plus the erd[7:0] set- up time to romclk.) this field is an alias of ctrl0, bits 11-8. read/write accessible. romt- mg is set to the value of 1001b by h_reset and is not affected by s_reset or stop. the default value allows the use of an expan- sion rom with an access time of 350 ns if erclk is running at 90 mhz. 11 nouflo no underflow on transmit. when the nouflo bit is set to 1, the am79c976 controller will not start transmitting the preamble for a packet until the transmit start point (ctrl1, bits 16-17) requirement has been met and the complete packet has been copied into the transmit fifo. when the nouflo bit is cleared to 0, the transmit start point is the only restriction on when pre- amble transmission begins for transmit packets. setting the nouflo bit guaran- tees that the am79c976 control- ler will never suffer transmit underflows, because the arbiter that controls transfers to and from the ssram guarantees a worst case latency on transfers to and from the mac and bus transmit fifos such that it will never un- derflow if the complete packet has been copied into the am79c976 controller before packet transmission begins. read/write accessible. nouflo is cleared to 0 after h_reset or s_reset and is unaffected by stop. 10 res reserved location. written as ze- ros and read as undefined. 9 memcmd obsolete function. writing has no effect. read as undefined. 8 extreq obsolete function. writing has no effect. read as undefined. 7 dwio double word i/o. when set, this bit indicates that the am79c976 controller is programmed for dword i/o (dwio) mode. when 8/01/00 am79c976 209 preliminary cleared, this bit indicates that the am79c976 controller is pro- grammed for word i/o (wio) mode. this bit affects the i/o re- source offset map and it affects the defined width of the am79c976 controllers i/o re- sources. see the dwio and wio sections for more details. the initial value of the dwio bit is determined by the programming of the eeprom. the value of dwio can be al- tered automatically by the am79c976 controller. specifical- ly, the am79c976 controller will set dwio if it detects a dword write access to offset 10h from the am79c976 controller i/o base address (corresponding to the rdp resource). once the dwio bit has been set to a 1, only a h_reset or an ee- prom read can reset it to a 0. (note that the eeprom read op- eration will only set dwio to a 0 if the appropriate bit inside of the eeprom is set to 0.) dwio is read only, write opera- tions have no effect. dwio is cleared by h_reset and is not affected s_reset or by setting the stop bit. 6 breade obsolete function. writing has no effect. read as undefined. 5 bwrite obsolete function. writing has no effect. read as undefined. 4-3 tstshdw reserved locations. written and read as zeros. 2-0 linbc reserved locations. written and read as zeros. 2?%%0 # bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15 pvalid eeprom valid status bit. pvalid is read only; write opera- tions have no effect. a value of 1 in this bit indicates that a pread operation has occurred, and that (1) there is an eeprom connect- ed to the am79c976 controller in- terface pins and (2) the contents read from the eeprom have passed the checksum verification operation. a value of 0 in this bit indicates a failure in reading the eeprom. the checksum for the eeprom contents is incorrect or no ee- prom is connected to the inter- face pins. pvalid is set to 0 during h_reset and is unaffected by s_reset or the stop bit. how- ever, following the h_reset op- eration, an automatic, sequential read of the eeprom will be per- formed. just as is true for the nor- mal pread command, at the end of this automatic, sequential read operation, the pvalid bit may be set to 1. therefore, h_reset will set the pvalid bit to 0 at first, but the automatic ee- prom read operation may later set pvalid to a 1. if pvalid becomes 0 following an eeprom read operation (ei- ther automatically generated af- ter h_reset, or requested through pread), then all ee- prom-programmable bcr loca- tions will be reset to their h_reset values. the content of the address prom locations, however, will not be cleared. if no eeprom is present at the eesk, eedi, and eedo pins, then all attempted pread com- mands will terminate early and pvalid will not be set. this ap- plies to the automatic read of the eeprom after h_reset, as well as to host-initiated pread commands. 14 pread eeprom read command bit. when this bit is set to a 1 by the host, the pvalid bit (bcr19, bit 15) will immediately be reset to a 0, and then the am79c976 con- troller will perform a sequential 210 am79c976 8/01/00 preliminary read operation of the eeprom through the interface. the ee- prom data that is fetched during the read will be stored in the ap- propriate internal registers on board the am79c976 controller. upon completion of the eeprom read operation, the am79c976 controller will assert the pvalid bit. eeprom contents will be in- directly accessible to the host through read accesses to the ad- dress prom (offsets 0h through fh) and through read accesses to other eeprom programmable registers. note that read access- es from these locations will not actually access the eeprom it- self, but instead will access the am79c976 controller ? s internal copy of the eeprom contents. write accesses to these locations may change the am79c976 con- troller register contents, but the eeprom locations will not be af- fected. eeprom locations may be accessed directly through bcr19. at the end of the sequential read operation, the pread bit will au- tomatically be reset to a 0 by the am79c976 controller and pvalid will be set, provided that an eeprom existed on the inter- face pins and that the checksum for the eeprom contents was correct. note that when pread is set to a 1, then the am79c976 controller will no longer respond to any ac- cesses directed toward it, until the pread operation has com- pleted successfully. the am79c976 controller will termi- nate these accesses with the as- sertion of devsel and stop while trdy is not asserted, sig- naling to the initiator to discon- nect and retry the access at a later time. if a pread command is given to the am79c976 controller but no eeprom is attached to the inter- face pins, the pread bit will be cleared to a 0, and the pvalid bit will remain reset with a value of 0. this applies to the automatic, se- quential read of the eeprom af- ter h_reset as well as to host initiated pread commands. ee- prom programmable locations on board the am79c976 control- ler will be set to their default val- ues by such an aborted pread operation. for example, if the aborted pread operation imme- diately followed the h_reset operation, then the final state of the eeprom programmable lo- cations will be equal to the h_reset programming for those locations. if a pread command is given to the am79c976 controller and the auto-detection pin (eesk/led1 / sfbd) indicates that no eeprom is present, then the eeprom read operation will still be attempted. note that at the end of the h_reset operation, a read of the eeprom will be performed automatically. this h_reset- generated eeprom read func- tion will not proceed if the auto- detection pin (eesk/led1 ) indi- cates that no eeprom is present. read/write accessible. pread is set to 0 during h_reset and is unaffected by s_reset or the stop bit. 13 eedet eeprom detect. this bit indi- cates the sampled value of the eesk/led1 pin at the end of h_reset. this value indicates whether or not an eeprom is present at the eeprom inter- face. if this bit is a 1, it indicates that an eeprom is present. if this bit is a 0, it indicates that an eeprom is not present. eedet is read only; write opera- tions have no effect. the value of this bit is determined at the end of the h_reset operation. it is un- affected by s_reset or the stop bit. 8/01/00 am79c976 211 preliminary table 90 indicates the possible combinations of eedet and the existence of an eeprom and the resulting operations that are pos- sible on the eeprom interface. table 90. eedet setting 12-5 res reserved locations. written as zeros; read as undefined. 4 een eeprom port enable. when this bit is set to a 1, it causes the val- ues of ecs, esk, and edi to be driven onto the eecs, eesk, and eedi pins, respectively. if een = 0 and no eeprom read function is currently active, then eecs will be driven low. when een = 0 and no eeprom read function is currently active, eesk and eedi pins will be driven by the led registers bcr5 and bcr4, respectively. see table 91. read/write accessible. een is set to 0 by h_reset and is unaf- fected by s_reset or stop. 3 res reserved location. written as zero and read as undefined. 2 ecs eeprom chip select. this bit is used to control the value of the eecs pin of the interface when the een bit is set to 1 and the pread bit is set to 0. if een = 1 and pread = 0 and ecs is set to a 1, then the eecs pin will be forced to a high level at the ris- ing edge of the next clock follow- ing bit programming. if een = 1 and pread = 0 and ecs is set to a 0, then the eecs pin will be forced to a low level at the rising edge of the next clock following bit programming. ecs has no effect on the output value of the eecs pin unless the pread bit is set to 0 and the een bit is set to 1. read/write accessible. ecs is set to 0 by h_reset and is not affected by s_reset or stop. eedet value (bcr19[13]) eeprom connected? result if pread is set to 1 result of automatic eeprom read operation following h_reset 0 no eeprom read operation is attempted. entire read sequence will occur; checksum failure will result; pvalid is reset to 0. first two eesk clock cycles are generated, then eeprom read operation is aborted and pvalid is reset to 0. 0 ye s eeprom read operation is attempted. entire read sequence will occur; checksum operation will pass; pvalid is set to 1. first two eesk clock cycles are generated, then eeprom read operation is aborted and pvalid is reset to 0. 1 no eeprom read operation is attempted. entire read sequence will occur; checksum failure will result; pvalid is reset to 0. eeprom read operation is attempted. entire read sequence will occur; checksum failure will result; pvalid is reset to 0. 1 ye s eeprom read operation is attempted. entire read sequence will occur; checksum operation will pass; pvalid is set to 1. eeprom read operation is attempted. entire read sequence will occur; checksum operation will pass; pvalid is set to 1. table 91. interface pin assignment pin *pread or auto read in progress een eecs eesk eedi low x x 0 tr i - s t a t e tr i - s t a t e high 1 x active active active high 0 1 from ecs bit of bcr19 from esk bit of bcr19 from eedi bit of bcr19 high 0 0 0 led1 led0 212 am79c976 8/01/00 preliminary 1 esk eeprom serial clock. this bit and the edi/edo bit are used to control host access to the eeprom. values programmed to this bit are placed onto the eesk pin at the rising edge of the next clock following bit program- ming, except when the pread bit is set to 1 or the een bit is set to 0. if both the esk bit and the edi/edo bit values are changed during one bcr19 write opera- tion, while een = 1, then setup and hold times of the eedi pin value with respect to the eesk signal edge are not guaranteed. esk has no effect on the eesk pin unless the pread bit is set to 0 and the een bit is set to 1. read/write accessible. esk is reset to 0 by h_reset and is not affected by s_reset or stop. 0 edi/edo eeprom data in/eeprom data out. data that is written to this bit will appear on the eedi output of the interface, except when the pread bit is set to 1 or the een bit is set to 0. data that is read from this bit reflects the value of the eedo input of the in- terface. edi/edo has no effect on the eedi pin unless the pread bit is set to 0 and the een bit is set to 1. read/write accessible. edi/edo is reset to 0 by h_reset and is not affected by s_reset or stop. 4?8$ this register is an alias of the location csr58. accesses to and from this register are equivalent to accesses to csr58. bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-11 res reserved locations. written as zeros and read as undefined. 10 aperren obsolete function. writing has no effect. read as undefined. 9 res reserved locations. written as zeros; read as undefined. 8 ssize32 software size 32 bits. when set, this bit indicates that the am79c976 controller utilizes 32-bit software structures for the initialization block and the trans- mit and receive descriptor en- tries. when cleared, this bit indicates that the am79c976 controller utilizes 16-bit software structures for the initialization block and the transmit and re- ceive descriptor entries. in this mode, the am79c976 controller is backwards compatible with the am7990 lance and am79c960 pcnet-isa controllers. the value of ssize32 is deter- mined by the am79c976 control- ler according to the setting of the software style (swstyle, bits 7-0 of this register). ssize32 is read only; write oper- ations will be ignored. ssize32 will be cleared after h_reset (since swstyle defaults to 0) and is not affected by s_reset or stop. if ssize32 is reset, then bits iadr[31:24] of csr2 will be used to generate values for the upper 8 bits of the 32-bit address bus during master accesses initi- ated by the am79c976 controller. this action is required, since the 16-bit software structures speci- fied by the ssize32 = 0 setting will yield only 24 bits of address for am79c976 controller bus master accesses. if ssize32 is set, then the soft- ware structures that are common to the am79c976 controller and the host system will supply a full 32 bits for each address pointer that is needed by the am79c976 controller for performing master accesses. 8/01/00 am79c976 213 preliminary the value of the ssize32 bit has no effect on the drive of the upper 8 address bits. the upper 8 ad- dress pins are always driven, re- gardless of the state of the ssize32 bit. note that the setting of the ssize32 bit has no effect on the defined width for i/o resources. i/o resource width is determined by the state of the dwio bit (bcr18, bit 7). 7-0 swstyle software style register. the val- ue in this register determines the style of register and memory re- sources that shall be used by the am79c976 controller. the soft- ware style selection will affect the interpretation of a few bits within the csr space, the order of the descriptor entries and the width of the descriptors and initializa- tion block entries. all am79c976 controller csr bits and all descriptor, buffer, and initialization block entries not cit- ed in the table 92 are unaffected by the software style selection and are, therefore, always fully functional as specified in the csr and bcr sections. read/write accessible. the sw- style register will contain the value 00h following h_reset and will be unaffected by s_reset or stop. 214 am79c976 8/01/00 preliminary ?0<($ note: bits 15-0 in this register are programmable through the eeprom. bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-8 max_lat maximum latency. specifies the maximum arbitration latency the am79c976 controller can sustain without causing problems to the network activity. the register val- ue specifies the time in units of 1/4 microseconds. max_lat is aliased to the pci configuration space register max_lat (offset 3fh). the host will use the value in the register to determine the setting of the am79c976 latency timer register. read/write accessible. max_lat is set to the value of 18h by h_reset which results in a default maximum latency of 6 microseconds. max_lat is not affected by s_reset or stop. 7-0 min_gnt minimum grant. specifies the min- imum length of a burst period the am79c976 controller needs to keep up with the network activity. the length of the burst period is calculated assuming a clock rate of 33 mhz. the register value speci- fies the time in units of 1/4 s. min_gnt is aliased to the pci configuration space register min_gnt (offset 3eh). the host will use the value in the register to determine the setting of the am79c976 latency timer register. read/write accessible. min_gnt is set to the value of 18h by h_reset which results in a default minimum grant of 6 s. min_gnt is not affected by s_reset or stop. ?05 $ !=* note: bits 15-0 in this register are programmable through the eeprom. bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 svid subsystem vendor id. svid is used together with sid (bcr24, bits 15-0) to uniquely identify the add-in board or subsystem the am79c976 controller is used in. subsystem vendor ids can be ob- tained from the pci sig. a value of 0 (the default) indicates that the am79c976 controller does not support subsystem identification. table 92. software styles swstyle [7:0] style name ssize32 initialization block entries descriptor ring entries 00h lance/ pcnet-isa controller 0 16-bit software structures, non-burst or burst access 16-bit software structures, non-burst access only 01h res 1 res res 02h pcnet-pci controller 1 32-bit software structures, non-burst or burst access 32-bit software structures, non-burst access only 03h pcnet-pci controller 1 32-bit software structures, non-burst or burst access 32-bit software structures, non-burst or burst access 04h vlan 1 not used 32-bit software structures, non-burst or burst access 05h 64-bit address 1 not used 32-bit software structures, 32-byte descriptors, non- burst or burst access all other reserved undefined undefined undefined 8/01/00 am79c976 215 preliminary svid is aliased to the pci config- uration space register subsystem vendor id (offset 2ch). svid is read only. write opera- tions are ignored. svid is cleared to 0 by h_reset and is not af- fected by s_reset or by setting the stop bit. "?05 $ !* note: bits 15-0 in this register are programmable through the eeprom. bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 sid subsystem id. sid is used to- gether with svid (bcr23, bits 15-0) to uniquely identify the add- in board or subsystem the am79c976 controller is used in. the value of sid is up to the sys- tem vendor. a value of 0 (the de- fault) indicates that the am79c976 controller does not support subsystem identification. sid is aliased to the pci configu- ration space register subsystem id (offset 2eh). sid is read only. write operations are ignored. sid is cleared to 0 by h_reset and is not affected by s_reset or by setting the stop bit. )?# 6 bit name description note: bits 7-0 in this register are programmable through the eeprom. 31-16 res reserved locations. written as zeros and read as undefined. 15-0 sram_size sram size. specifies the total size of the ssram buffer in units of 512-byte pages. for example, assume that the external memory consists of one 64k x 32 bit ss- ram, for a total of 256k bytes. in this case sram_size should be set to 512 (256k divided by 512). this field must be initialized to the appropriate value, either by the eeprom or by the host cpu. sram_size must be set to a val- ue less than or equal to 2000h. values larger than 2000h will cause incorrect behavior. note : the minimum allowed number of pages is eight for nor- mal network operation. the am79c976 controller will not op- erate correctly with less than the eight pages of memory. when the minimum number of pages is used, these pages must be allo- cated four each for transmit and receive. caution: programming sram_bnd and sram_size to the same value will cause data corruption. read/write accessible. sram_size is set to 000000b during h_reset and is unaffect- ed by s_reset or stop. ,?#$ bit name description note: bits 7-0 in this register are programmable through the eeprom. 31-16 res reserved locations. written as zeros and read as undefined. 15-0 sram_bnd sram boundary. specifies the size of the transmit buffer portion of the sram in units of 512-byte pages. for example if sram_bnd is set to 10, then 5120 bytes of the sram will be allocated for the transmit buffer and the rest will be allocated for the receive buffer. the transmit buffer in the sram begins at address 0 and ends at the address (sram_bnd*512)- 1. therefore, the receive buffer always begins on a 512-byte boundary. sram_bnd must be initialized to an appropriate value, either by the eeprom or by the host cpu. sram_bnd must be set to a val- ue less than or equal to iffch. 216 am79c976 8/01/00 preliminary values larger than iffch will cause incorrect behavior. note : the minimum allowed number of pages is four and the maximum is sram_size-4. the am79c976 controller will not op- erate correctly with less than four pages of memory per queue. see table 93 for sram_bnd pro- gramming details. caution : programming sram_bnd and sram_size to the same value will cause data corruption. read/write accessible. sram_bnd is set to 00000000b during h_reset and is unaffect- ed by s_reset or stop. /?#( bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15 ptr tst reserved. reserved for manu- facturing tests. written as zero and read as undefined. note : use of this bit will cause data corruption and erroneous operation. read/write accessible. ptr_tst is set to 0 by h_reset and is unaffected by s_reset and the stop bit. 14 lolatrx obsolete function. writing has no effect. read as undefined. 13-6 res reserved locations. written as zeros and read as undefined. 5-3 ebcs obsolete function. writing has no effect. read as undefined. 2-0 clk_fac obsolete function. writing has no effect. read as undefined. 1?%&' 0 <8: + %0 ##(( ; bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 epaddrl expansion port address lower. this address is used to provide addresses for the flash port ac- cesses. flash accesses are started when a read or write is performed on bcr30. during flash accesses all bits in epaddr are valid. read accessible always; write accessible only when stop is set or when sram_size (bcr25, bits 7-0) is 0. epaddrl is undefined after h_reset and is unaffected by s_reset or stop. 2?%&' 0 '': + %0 #(( ; bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15 flash obsolete function. read only. al- ways returns logic 1. 14 laainc lower address auto increment. when the laainc bit is set to 1, the expansion port lower ad- dress will automatically increment by one after a read or write ac- cess to ebdata (bcr30). when ebaddrl reaches ffffh and laainc is set to 1, the expansion port lower address (epaddrl) will roll over to 0000h. when the laainc bit is set to 0, the expan- sion port lower address will not be affected in any way after an access to ebdata (bcr30) and must be programmed. read accessible always; write accessible only when the stop bit is set. lainc is 0 after h_reset and is unaffected by s_reset or the stop bit. table 93. sram_bnd programming sram addresses sram_bnd 11:0] minimum sram_bnd address 004h maximum sram_bnd address sram_size - 4 8/01/00 am79c976 217 preliminary 13-8 res reserved locations. written as zeros and read as undefined. 7-0 epaddru expansion port address upper. this upper portion of the expan- sion bus address is used to pro- vide addresses for flash/eprom port accesses. read accessible always; write accessible only when the stop bit is set or when sram size (bcr25, bits 7-0) is 0. epadd- ru is undefined after h_reset and is unaffected by s_reset or the stop bit. 4?%&' *0 bit name description 31-8 res reserved locations. written as zeros and read as undefined. 7-0 ebdata expansion bus data port. ebda- ta is the data port for operations on the expansion port involving flash accesses. flash read cycles are performed when bcr30 is read. upon com- pletion of the read cycle, the 8-bit result for flash access is stored in ebdata[7:0]. flash write cy- cles are performed when bcr30 is written and the flash bit (bcr29, bit 15) is set to 1. read and write accessible. eb- data is undefined after h_reset, and is unaffected by s_reset and the stop bit. ?8 ! bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 stval software timer value. stval controls the maximum time for the software timer to count be- fore generating the stint (csr7, bit 11) interrupt. the soft- ware timer is a free-running tim- er that is started upon the first write to stval. after the first write, the software timer will continually count and set the stint interrupt at the stval pe- riod. the stval value is interpreted as an unsigned number with a resolution of 10.24s. for in- stance, if stval is set to 48,828 (0bebch), the software timer period will be 0.5 s. setting stval to a value of 0 will result in erratic behavior. read and write accessible. stval is set to ffffh after h_reset and is unaffected by s_reset and the stop bit. ?# note: bits 15-0 in this register are programmable through the eeprom. bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15 antst reserved for manufacturing tests. written as 0 and read as undefined. note : use of this bit will cause data corruption and erroneous operation. read/write accessible. antst is set to 0 by h_reset and is unaf- fected by s_reset and the stop bit. 14 miipd mii phy detect. miipd reflects the quiescent state of the mdio pin. miipd is continuously updat- ed whenever there is no manage- ment operation in progress on the mii interface. when a manage- ment operation begins on the in- terface, the state of miipd is preserved until the operation ends, when the quiescent state is again monitored and continuous- ly updates the miipd bit. when the mdio pin is at a quiescent low state, miipd is cleared to 0. when the mdio pin is at a quies- cent high state, miipd is set to 1. any transition on the miipd bit will set the miipdtint bit (csr7, bit 1). 218 am79c976 8/01/00 preliminary miipd is read only. write opera- tions are ignored. 13-12 fmdc fast management data clock. when fmdc is set to 2h the mii management data clock will run at 10 mhz max. the manage- ment data clock will no longer be ieee 802.3u-compliant and set- ting this bit should be used with care. the accompanying external phy must also be able to accept management frames at the new clock rate. when fmdc is set to 1h, the mii management data clock will run at 5 mhz max. the management data clock will no longer be ieee 802.3u-compliant and setting this bit should be used with care. the accompany- ing external phy must also be able to accept management frames at the new clock rate. when fmdc is set to 0h, the mii management data clock will run at 2.5 mhz max and will be fully compliant to ieee 802.3u stan- dards. see table 94. read/write accessible. fmdc is set to 0 during h_reset, and is unaffected by s_reset and the stop bit 11 apep mii auto-poll external phy. when apep is set to 1, the am79c976 controller will poll the mii status register in the external phy. this feature allows the soft- ware driver or upper layers to see any changes in the status of the external phy. an interrupt, when enabled, is generated when the contents of the new status is dif- ferent from the previous status. read/write accessible. apep is set to 0 during h_reset and is unaffected by s_reset and the stop bit. 10-8 apdw mii auto-poll dwell time. apdw determines the dwell time be- tween mii management frames accesses when auto-poll is turned on. see table 95. read/write accessible. apdw is set to 100b after h_reset and is unaffected by s_reset and the stop bit. 7 dispm disable port manager. (the cor- responding bit in older pcnet family devices is called disable auto-negotiation auto setup or danas. the name has been changed, but not the function.) when dispm is set, the am79c976 controller after a h_reset or s_reset will re- main dormant and not automati- cally start up the auto- negotiation section or the en- hanced automatic port selection section. instead, the am79c976 controller will wait for the soft- ware driver to set up the auto-ne- gotiation portions of the device. the mii programming in bcr33 and bcr34 is still valid. the am79c976 controller will not generate any management frames unless auto-poll is en- abled. read/write accessible. dispm is set to 0 by h_reset and is unaf- fected by s_reset and the stop bit. 6 xphyrst external phy reset. when xph- yrst is set, the am79c976 con- troller after an h_reset or s_reset will issue an mii man- agement frame that will reset the table 94. fmdc values fmdc fast management data clock 00 2.5 mhz max 01 5 mhz max 10 10 mhz max 11 reserved table 95. apdw values apdw auto-poll dwell time 000 continuous (26 s @ 2.5 mhz) 001 every 64 mdc cycles (51 s @ 2.5 mhz) 010 every 128 mdc cycles (103 s @ 2.5 mhz) 011 every 256 mdc cycles (206 s @ 2.5 mhz) 100 every 512 mdc cycles (410 s @ 2.5 mhz) 101 every 1024 mdc cycles (819 s @ 2.5 mhz) 110-111 reserved 8/01/00 am79c976 219 preliminary external phy. this bit is needed when there is no way to guaran- tee the state of the external phy. this bit must be reprogrammed after every h_reset. read/write accessible. xph- yrst is set to 0 by h_reset and is unaffected by s_reset and the stop bit. xphyrst is only valid when the internal net- work port manager is scanning for a network port. 5 xphyane external phy auto-negotiation enable. this bit will force the ex- ternal phy into enabling auto- negotiation. when set to 0 the am79c976 controller will send a mii management frame disabling auto-negotiation. read/write accessible. xphyane is set to 0 by h_reset and is unaffected by s_reset and the stop bit. xphyane is only valid when the internal network port manager is scanning for a network port. 4 xphyfd external phy full duplex. when set, this bit will force the external phy into full duplex when auto- negotiation is not enabled. read/write accessible. xphyfd is set to 0 by h_reset, and is unaffected by s_reset and the stop bit. xphyfd is only valid when the internal network port manager is scanning for a net- work port. 3 xphysp external phy speed. when set, this bit will force the external phy into 100 mbps mode when auto- negotiation is not enabled. read/write accessible. xphysp is set to 0 by h_reset, and is unaffected by s_reset and the stop bit. xphysp is only valid when the internal network port manager is scanning for a net- work port. 2 res reserved location. written as ze- ros and read as undefined. 1 miiilp media independent interface in- ternal loopback. when set, this bit will cause the internal portion of the mii data port to loop back on itself. the interface is mapped in the following way. the txd[3:0] nibble data path is looped back onto the rxd[3:0] nibble data path. tx_clk is looped back as rx_clk. tx_en is looped back as rx_dv. crs is correctly or ? d with tx_en and rx_dv and always encompass- es the transmit frame. tx_er is looped back as rx_er. howev- er, tx_er will not get asserted by the am79c976 controller to signal an error. the tx_er func- tion is reserved for future use. read/write accessible. miiilp is set to 0 by h_reset and is unaf- fected by s_reset and the stop bit. 0 res reserved location. written as ze- ros and read as undefined. ?# bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-10 res reserved locations. written as zeros and read as undefined. 9-5 phyad mii management frame phy ad- dress. phyad contains the 5-bit phy address field that is used in the management frame that gets clocked out via the mii manage- ment port pins (mdc and mdio) whenever a read or write transac- tion occurs to bcr34. the phy address 1fh is not valid. read/write accessible. phyad is undefined after h_reset and is unaffected by s_reset and the stop bit. the phyad field is loaded from bits [9:5] of the autopoll0 reg- ister when autopoll0 is load- ed from eeprom. 4-0 regad mii management frame register address. regad contains the 220 am79c976 8/01/00 preliminary 5-bit register address field that is used in the management frame that gets clocked out via the mii management port pins (mdc and mdio) whenever a read or write transaction occurs to bcr34. read/write accessible. regad is undefined after h_reset and is unaffected by s_reset and the stop bit. "?## !* bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 miimd mii management data. miimd is the data port for operations on the mii management interface (mdio and mdc). the am79c976 device builds man- agement frames using the phy- ad and regad values from bcr33. the operation code used in each frame is based upon whether a read or write operation has been performed to bcr34. read cycles on the mii manage- ment interface are invoked when bcr34 is read. upon completion of the read cycle, the 16-bit result of the read operation is stored in miimd. write cycles on the mii management interface are in- voked when bcr34 is written. the value written to miimd is the value used in the data field of the management write frame. read/write accessible. miimd is undefined after h_reset and is unaffected by s_reset and the stop bit. )?0=* note: bits 15-0 in this register are programmable through the eeprom. bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-0 vid vendor id. the pci vendor id register is a 16-bit register that identifies the manufacturer of the am79c976 controller. amd ? s vendor id is 1022h. note that this vendor id is not the same as the manufacturer id in csr88 and csr89. the vendor id is as- signed by the pci special inter- est group. the vendor id is not normally programmable, but the am79c976 controller allows this due to legacy operating systems that do not look at the pci sub- system vendor id and the ven- dor id to uniquely identify the add-in board or subsystem that the am79c976 controller is used in. note: if the operating system or the network operating system supports pci subsystem vendor id and subsystem id, use those to identify the add-in board or subsystem and program the vid with the default value of 1022h . vid is aliased to the pci configu- ration space register vendor id (offset 00h). vid is read only. write operations are ignored. vid is set to 1022h by h_reset and is not affected by s_reset or by setting the stop bit. ,?008# !'5 :0#; this register is an alias of the pmc register located at offset 42h of the pci configuration space. it is included for compatibility with older pcnet devices. since the pmc register is read only, in older pcnet devices bcr36 provides a means of programming pmc through the eeprom. in the am79c976 controller there is a single pmc reg- ister that can be accessed through three different mem- ory spaces. it can be accessed as read-only through pci configuration space (at offset 42h), read-only through bcr36, or read-write through the memory- mapped pmc alias register at offset 1b8h. it can be loaded from the eeprom through offset 1b8h in the am79c976 controller ? s memory-mapped i/o space. for the definition of the bits in this register, refer to the pmc register definition. bcr36 is read only. it is set to 0c802h by h_reset and is not affected by s_reset or setting the stop bit. 8/01/00 am79c976 221 preliminary /?0* b:* 4; note: this register is an alias of the data register and also of the data_scale field of the pmcsr register. since these two are read only, bcr37 provides a means of programming them indirectly. the contents of this register are copied into the corresponding fields pointed with the data_sel field set to zero. bits 15-0 in this register are programmable through the ee- prom. bit name description 15-10 res reserved locations. written as zeros and read as undefined. 9-8 d0_scale these bits correspond to the data_scale field of the pmcsr (offset register 44 of the pci configuration space, bits 14- 13). refer to the description of data_scale for the meaning of this field. d0_scale is read only. cleared by h_reset and is not affected by s_reset or setting the stop bit. 7-0 data0 these bits correspond to the pci data register (offset register 47 of the pci configuration space, bits 7-0). refer to the description of data register for the meaning of this field. data0 is read only. cleared by h_reset and is not affected by s_reset or setting the stop bit. 1?0* :* ; note: this register is an alias of the data register and also of the data_scale field of the pmcsr register. since these two are read only, bcr38 provides a means of programming them through the eeprom. the contents of this register are copied into the corre- sponding fields pointed with the data_sel field set to one. bits 15-0 in this register are programmable through the eeprom. bit name description 15-10 res reserved locations. written as zeros and read as undefined. 9-8 d1_scale these bits correspond to the data_scale field of the pmc- sr (offset register 44 of the pci configuration space, bits 14-13). refer to the description of data_scale for the meaning of this field. d1_scale is read only. cleared by h_reset and is not affected by s_reset or setting the stop bit. 7-0 data1 these bits correspond to the pci data register (offset register 47 of the pci configuration space, bits 7-0). refer to the description of data register for the meaning of this field. data1 is read only. cleared by h_reset and is not affected by s_reset or setting the stop bit. 2?0* 8:* ; note: this register is an alias of the data register and also of the data_scale field of the pmcsr register. since these two are read only, bcr39 provides a means of programming them through the eeprom. the contents of this register are copied into the corre- sponding fields pointed to with the data_sel field set to two. bits 15-0 in this register are programmable through the eeprom. bit name description 15-10 res reserved locations. written as zeros and read as undefined. 9-8 d2_scale these bits correspond to the data_scale field of the pmcsr (offset register 44 of the pci configuration space, bits 14- 13). refer to the description of data_scale for the meaning of this field. d2_scale is read only. cleared by h_reset and is not affected by s_reset or setting the stop bit. 7-0 data2 these bits correspond to the pci data register (offset register 47 of the pci configuration space, bits 7-0). refer to the description of data register for the meaning of this field. data2 is read only. cleared by h_reset and is not affected by s_reset or setting the stop bit. 222 am79c976 8/01/00 preliminary "4?0* +:* ; note: this register is an alias of the data register and also of the data_scale field of the pcmcr register. since these two are read only, bcr40 provides a means of programming them through the eeprom. the contents of this register are copied into the corre- sponding fields pointed with the data_sel field set to three. bits 15-0 in this register are programmable through the eeprom. bit name description 15-10 res reserved locations. written as zeros and read as undefined. 9-8 d3_scale these bits correspond to the data_scale field of the pmc- sr (offset register 44 of the pci configuration space, bits 14-13). refer to the description of data_scale for the meaning of this field. d3_scale is read only. cleared by h_reset and is not affected by s_reset or setting the stop bit. 7-0 data3 these bits correspond to the pci data register (offset register 47 of the pci configuration space, bits 7-0). refer to the description of data register for the meaning of this field. data3 is read only. cleared by h_reset and is not affected by s_reset or setting the stop bit. "?0* :* "; note: this register is an alias of the data register and also of the data_scale field of the pcmcr register. since these two are read only, bcr41 provides a means of programming them through the eeprom. the contents of this register are copied into the corre- sponding fields pointed with the data_sel field set to four. bits 15-0 in this register are programmable through the eeprom. bit name description 15-10 res reserved locations. written as zeros and read as undefined. 9-8 d4_scale these bits correspond to the data_scale field of the pmc- sr (offset register 44 of the pci configuration space, bits 14-13). refer to the description of data_scale for the meaning of this field. d4_scale is read only. cleared by h_reset and is not affected by s_reset or setting the stop bit 7-0 data4 these bits correspond to the pci data register (offset register 47 of the pci configuration space, bits 7-0). refer to the description of data register for the meaning of this field. data4 is read only. cleared by h_reset and is not affected by s_reset or setting the stop bit. " ?0* :* ); note: this register is an alias of the data register and also of the data_scale field of the pcmcr register. since these two are read only, bcr42 provides a means of programming them through the eeprom. the contents of this register are copied into the corre- sponding fields pointed with the data_sel field set to five. bits 15-0 in this register are programmable through the eeprom. bit name description 15-10 res reserved locations. written as zeros and read as undefined. 9-8 d5_scale these bits correspond to the data_scale field of the pmc- sr (offset register 44 of the pci configuration space, bits 14-13). refer to the description of data_scale for the meaning of this field. d5_scale is read only. cleared by h_reset and is not affected by s_reset or setting the stop bit. 7-0 data5 these bits correspond to the pci data register (offset register 47 of the pci configuration space, bits 7-0). refer to the description of data register for the meaning of this field. data5 is read only. cleared by h_reset and is not affected by 8/01/00 am79c976 223 preliminary s_reset or setting the stop bit. " ?0* &:* ,; note: this register is an alias of the data register and also of the data_scale field of the pcmcr register. since these two are read only, bcr43 provides a means of programming them through the eeprom. the contents of this register are copied into the corre- sponding fields pointed with the data_sel field set to six. bits 15-0 in this register are programmable through the eeprom. bit name description 15-10 res reserved locations. written as zeros and read as undefined. 9-8 d6_scale these bits correspond to the data_scale field of the pmc- sr (offset register 44 of the pci configuration space, bits 14-13). refer to the description of data_scale for the meaning of this field. d6_scale is read only. cleared by h_reset and is not affected by s_reset or setting the stop bit 7-0 data6 these bits correspond to the pci data register (offset register 47 of the pci configuration space, bits 7-0). refer to the description of data register for the meaning of this field. data6 is read only. cleared by h_reset and is not affected by s_reset or setting the stop bit. ""?0* :* /; note: this register is an alias of the data register and also of the data_scale field of the pcmcr register. since these two are read only, bcr44 provides a means of programming them through the eeprom. the contents of this register are copied into the corre- sponding fields pointed with the data_sel field set to seven. bits 15-0 in this register are programmable through the eeprom. bit name description 15-10 res reserved locations. written as zeros and read as undefined. 9-8 d7_scale these bits correspond to the data_scale field of the pmc- sr (offset register 44 of the pci configuration space, bits 14-13). refer to the description of data_scale for the meaning of this field. d7_scale is read only. cleared by h_reset and is not affected by s_reset or setting the stop bit. 7-0 data7 these bits correspond to the pci data register (offset register 47 of the pci configuration space, bits 7-0). refer to the description of data register for the meaning of this field. data7 is read only. cleared by h_reset and is not affected by s_reset or setting the stop bit. ")? 80#(+ note: this register is used to control and indirectly ac- cess the pattern match ram (pmr). when bcr45 is written and the pmat_mode bit (bit 7) is 1, pattern match logic is enabled. no bus accesses into pmr are possible, and bcr46, bcr47, and all other bits in bcr45 are ignored. when pmat_mode is set, a read of bcr45, bcr46, or bcr47 returns all undefined bits except for pmat_mode. when bcr45 is written and the pmat_mode bit is 0, the pattern match logic is disabled and accesses to the pmr are possible. bits 6-0 of bcr45 specify the ad- dress of the pmr word to be accessed. following the write to bcr45, the pmr word may be read by reading bcr45, bcr46 and bcr47 in any order. to write to pmr word, the write to bcr45 must be followed by a write to bcr46 and a write to bcr47 in that order to complete the operation. the ram will not actually be written until the write to bcr47 is complete. the write to bcr47 causes all 5 bytes (four bytes of bcr46-47 and the upper byte of the bcr45) to be written to what- ever pmr word is addressed by bits 6:0 of bcr45. bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-8 pmr_b0 pattern match ram byte 0. this byte is written into or read from byte 0 of the pattern match ram. read and write accessible. pmr_b0 is undefined after 224 am79c976 8/01/00 preliminary h_reset, and is unaffected by s_reset and the stop bit. 7 pmat_mode pattern match mode. writing a 1 to this bit will enable pattern match mode and should only be done after the pattern match ram has been programmed. read and write accessible. pmat_mode is reset to 0 when power is initially applied to the de- vice, and is unaffected by s_reset and the stop bit. 6-0 pmr_addr pattern match ram address. these bits are the pattern match ram address to be written to or read from. read and write accessible. pmr_addr is reset to 0 when power is first applied to the de- vice (after power-on reset), and is unaffected by h_reset, s_reset and the stop bit. ",? 80#(+ note: this register is used to control and indirectly ac- cess the pattern match ram (pmr). when bcr45 is written and the pmat_mode bit (bit 7) is 1, pattern match logic is enabled. no bus accesses into pmr are possible, and bcr46, bcr47, and all other bits in bcr45 are ignored. when pmat_mode is set, a read of bcr45, bcr46, or bcr47 returns all undefined bits except for pmat_mode. when bcr45 is written and the pmat_mode bit is 0, the pattern match logic is disabled and accesses to the pmr are possible. bits 6-0 of bcr45 specify the ad- dress of the pmr word to be accessed. following the write to bcr45, the pmr word may be read by reading bcr45, bcr46 and bcr47 in any order. to write to pmr word, the write to bcr45 must be followed by a write to bcr46 and a write to bcr47 in that order to complete the operation. the ram will not actually be written until the write to bcr47 is complete. the write to bcr47 causes all 5 bytes (four bytes of bcr46-47 and the upper byte of the bcr45) to be written to what- ever pmr word is addressed by bits 6:0 of bcr45. bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-8 pmr_b2 pattern match ram byte 2. this byte is written into or read from byte 2 of the pattern match ram. read and write accessible. pmr_b2 is undefined after h_reset, and is unaffected by s_reset and the stop bit. 7-0 pmr_b1 pattern match ram byte 1. this byte is written into or read from byte 1 of pattern match ram. read and write accessible. pmr_b1 is undefined after h_reset, and is unaffected by s_reset and the stop bit. "/? 80#(+ note: this register is used to control and indirectly ac- cess the pattern match ram (pmr). when bcr45 is written and the pmat_mode bit (bit 7) is 1, pattern match logic is enabled. no bus accesses into pmr are possible, and bcr46, bcr47, and all other bits in bcr45 are ignored. when pmat_mode is set, a read of bcr45, bcr46, or bcr47 returns all undefined bits except for pmat_mode. when bcr45 is written and the pmat_mode bit is 0, the pattern match logic is disabled and accesses to the pmr are possible. bits 6-0 of bcr45 specify the ad- dress of the pmr word to be accessed. following the write to bcr45, the pmr word may be read by reading bcr45, bcr46 and bcr47 in any order. to write to pmr word, the write to bcr45 must be followed by a write to bcr46 and a write to bcr47 in that order to complete the operation. the ram will not actually be written until the write to bcr47 is complete. the write to bcr47 causes all 5 bytes (four bytes of bcr46-47 and the upper byte of the bcr45) to be written to what- ever pmr word is addressed by bits 6:0 of bcr45. when pmat_mode is 0, the contents of the word ad- dressed by bits 6:0 of bcr45 can be read by reading bcr45-47 in any order. bit name description 31-16 res reserved locations. written as zeros and read as undefined. 15-8 pmr_b4 pattern match ram byte 4. this byte is written into or read from byte 4 of pattern match ram. read and write accessible. pmr_b4 is undefined after h_reset, and is unaffected by s_reset and the stop bit. 8/01/00 am79c976 225 preliminary 7-0 pmr_b3 pattern match ram byte 3. this byte is written into or read from byte 3 of pattern match ram. read and write accessible. pmr_b3 is undefined after h_reset, and is unaffected by s_reset and the stop bit. initialization block note: when ssize32 (bcr20, bit 8) is set to 0, the software structures are defined to be 16 bits wide. the base address of the initialization block must be aligned to a word boundary, i.e., csr1, bit 0 must be cleared to 0. when ssize32 is set to 0, the initialization block looks like table 96. note: the am79c976 controller performs dword ac- cesses to read the initialization block. this statement is always true, regardless of the setting of the ssize32 bit. when ssize32 (bcr20, bit 8) is set to 1, the software structures are defined to be 32 bits wide. the base ad- dress of the initialization block must be aligned to a dword boundary, i.e., csr1, bits 1 and 0 must be cleared to 0. when ssize32 is set to 1, the initialization block looks like table 97. <% <% when ssize32 (bcr20, bit 8) is set to 0, the software structures are defined to be 16 bits wide, and the rlen and tlen fields in the initialization block are each three bits wide. the values in these fields determine the num- ber of transmit and receive descriptor ring entries (dre) which are used in the descriptor rings. their meaning is shown in table 98. if a value other than those listed in table 98 is desired, csr76 and csr78 can be written after initialization is complete. when ssize32 (bcr20, bit 8) is set to 1, the software structures are defined to be 32 bits wide, and the rlen table 96. initialization block (ssize32 = 0) address bits 15-13 bit 12 bits 11-8 bits 7-4 bits 3-0 iadr+00h mode 15-00 iadr+02h padr 15-00 iadr+04h padr 31-16 iadr+06h padr 47-32 iadr+08h ladrf 15-00 iadr+0ah ladrf 31-16 iadr+0ch ladrf 47-32 iadr+0eh ladrf 63-48 iadr+10h rdra 15-00 iadr+12h rlen 0 res rdra 23-16 iadr+14h tdra 15-00 iadr+16h tlen 0 res tdra 23-16 table 97. initialization block (ssize32 = 1) address bits bits bits bits bits bits bits bits 31-28 27-24 23-20 19-16 15-12 11-8 7-4 3-0 iadr+00h tlen res rlen res mode iadr+04h padr 31-00 iadr+08h res padr 47-32 iadr+0ch ladrf 31-00 iadr+10h ladrf 63-32 iadr+14h rdra 31-00 iadr+18h tdra 31-00 226 am79c976 8/01/00 preliminary and tlen fields in the initialization block are each 4 bits wide. the values in these fields determine the number of transmit and receive descriptor ring entries (dre) which are used in the descriptor rings. their meaning is shown in table 99. if a value other than those listed in table 99 is desired, csr76 and csr78 can be written after initialization is complete. * * rdra and tdra indicate where the transmit and re- ceive descriptor rings begin. each dre must be located at a 16-byte address boundary when ssize32 is set to 1 (bcr20, bit 8). each dre must be located at an 8-byte address boundary when ssize32 is set to 0 (bcr20, bit 8). <* the logical address filter (ladrf) is a 64-bit mask that is used to accept incoming logical addresses. if the first bit in the incoming address (as transmitted on the wire) is a 1, it indicates a logical address. if the first bit is a 0, it is a physical address and is compared against the physical address that was loaded through the initialization block. a logical address is passed through the crc generator, producing a 32-bit result. the high order 6 bits of the crc is used to select one of the 64 bit positions in the logical address filter. if the selected filter bit is set, the address is accepted and the frame is placed into mem- ory. the logical address filter is used in multicast address- ing schemes. the acceptance of the incoming frame based on the filter value indicates that the message may be intended for the node. it is the node ? s responsibility to determine if the message is actually intended for the node by comparing the destination address of the stored message with a list of acceptable logical addresses. if the logical address filter is loaded with all zeros and promiscuous mode is disabled, all incoming logical ad- dresses except broadcast will be rejected. if the drcvbc bit (csr15, bit 14) is set as well, the broad- cast packets will be rejected. see figure 4747. 0* this 48-bit value represents the unique node address assigned by the iso 8802-3 (ieee/ansi 802.3) and used for internal address comparison. padr[0] is com- pared with the first bit in the destination address of the incoming frame. it must be 0 since only the destination address of a unicast frames is compared to padr. the six hex-digit nomenclature used by the iso 8802-3 (ieee/ansi 802.3) maps to the am79c976 padr reg- ister as follows: the first byte is compared with padr[7:0], with padr[0] being the least significant bit of the byte. the second iso 8802-3 (ieee/ansi 802.3) byte is compared with padr[15:8], again from the least significant bit to the most significant bit, and so on. the sixth byte is compared with padr[47:40], the least sig- nificant bit being padr[40]. # the mode register field of the initialization block is cop- ied into csr15 and interpreted according to the description of csr15. table 98. r/tlen decoding (ssize32 = 0) r/tlen number of dres 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 table 99. r/tlen decoding (ssize32 = 1) r/tlen number of dres 0000 1 0001 2 0010 4 0011 8 0100 16 0101 32 0110 64 0111 128 1000 256 1001 512 1x1x 512 11xx 512 8/01/00 am79c976 227 preliminary "/ #(+< ( receive descriptors when swstyle (bcr20, bits 7-0) is set to 0, then the software structures are defined to be 16 bits wide, and receive descriptors look like table 100. when swstyle is set to 2, then the software struc- tures are defined to be 32 bits wide, and receive de- scriptors look like table 101. when swstyle is set to 3, then the software struc- tures are defined to be 32 bits wide, and receive de- scriptors look like table 102. when swstyle is set to 4, then the software struc- tures are defined to be 32 bits wide, and receive de- scriptors look like table 103. when swstyle is set to 5, then the software struc- tures are defined to be 32 bits wide, and receive de- scriptors look like table 104. also, when swstyle is 5, the am79c976 controller uses 64-bit addressing for software structures that are located above the 32-bit address boundary. 544( * ( ': ><%c4; 47 1 crc gen sel 31 26 mux 63 0 64 match = 1 packet accepted match = 0 packet rejected match logical address filter (ladrf) 0 6 32-bit resultant crc 1 0 received message destination address 21485b55 offset 15 14 13 12 11 10 9 8 7-0 00h rbadr[15:0] 02h own err fram oflo crc stp enp rbadr[23:16] 04h bcnt 06h 0 0 0 0 mcnt 54( * ( ': ><%c ; offset 31 30 29 28 27 26 25 24 23 22 21 20 19-16 15-0 00h rbadr[31:0] 04h own err fra m ofl o crc stp enp pa m lafm bam res bcnt 08h res rfrtag[14:0] mcnt 0ch user space 228 am79c976 8/01/00 preliminary 54 ( * ( ': ><%c ; offset 31 30 29 28 27 26 25 24 23 22 21 20 19-18 17-16 15-0 00h rfrtag[14:0] mcnt 04h own err fram oflo crc stp enp pa m lafm bam bcnt 08h rbadr[31:0] 0ch user space 54 ( * ( ': ><%c"; offset 31 30 29 28 27 26 25 24 23 22 21 20 19-18 17-16 15-0 00h tci[15:0] mcnt 04h own err fram oflo crc stp enp pa m lafm bam tt bcnt 08h rbadr[31:0] 0ch user space 54"( * ( ': ><%c); offset 31 30 29 28 27 26 25 24 23 22 21 20 19-18 17-16 15-0 00h rfrtag[31:0] 04h tci[15:0] mcnt 08h own err fram oflo crc stp enp pa m lafm bam tt bcnt 0ch rbadr[31:0] 10h rbadr[63:32] 14h user space 18h user space 1ch user space 8/01/00 am79c976 229 preliminary the following tables describe the bits of the receive descriptors in more detail. 54)( * ( 'd ><%c4 offset bit name description 0 15-0 rbadr receive buffer address. this field contains the address of the receive buffer that is associated with this descriptor. 2 15 own this bit indicates whether the descriptor entry is owned by the host (own = 0) or by the am79c976 controller (own = 1). the host sets the own bit after it has emptied the buffer pointed to by the descriptor entry. the am79c976 controller clears the own bit after filling the buffer that the description points to. both the am79c976 controller and the host must not alter a descriptor entry after it has relinquished ownership. 14 err error summary. err is the or of fram, oflo, and crc. err is set by the am79c976 controller and cleared by the host. 13 fram framing error indicates that the incoming frame contains a non-integer multiple of eight bits and there was an fcs error. if there was no fcs error on the incoming frame, then fram will not be set even if there was a non- integer multiple of eight bits in the frame. fram is not valid in internal loopback mode. fram is valid only when enp is set and oflo is not. fram is set by the am79c976 controller and cleared by the host. 12 oflo overflow error indicates that the receiver has lost all or part of the incoming frame, due to an inability to move data from the receive fifo into a memory buffer before the internal fifo overflowed. oflo is set by the am79c976 controller and cleared by the host. 11 crc crc indicates that the receiver has detected a crc (fcs) error on the incoming frame. crc is valid only when enp is set and oflo is not. crc is set by the am79c976 controller and cleared by the host. crc will also be set when am79c976 receives an rx_er indication from the external phy through the mii. 10 reserved. 9stp start of packet indicates that this is the first buffer used by the am79c976 controller for this frame. if stp and enp are both set to 1, the frame fits into a single buffer. otherwise, the frame is spread over more than one buffer. when lappen (csr3, bit 5) is cleared to 0, stp is set by the am79c976 controller and cleared by the host. when lappen is set to 1, stp must be set by the host. 8enp end of packet indicates that this is the last buffer used by the am79c976 controller for this frame. it is used for data chaining buffers. if both stp and enp are set, the frame fits into one buffer and there is no data chaining. enp is set by the am79c976 controller and cleared by the host. 7-0 rbadr[23:16] receive buffer address (high order bits) 4 15-0 bcnt buffer byte count is the length of the buffer pointed to by this descriptor, expressed as the two ? s complement of the length of the buffer. this field is written by the host and unchanged by the am79c976 controller. 6 15-12 zeros this field is reserved. am79c976 controller will write zeros to these locations. 11-0 mcnt message byte count is the number of bytes of the received message written to the receive buffer. this is the actual frame length (including fcs) unless stripping is enabled and the length field is < 46 bytes. in this case, mcnt is 14 + length_field. mcnt can take values in the range 15 to 59 and values greater than or equal to 64. mcnt is expressed as an unsigned binary integer. mcnt is valid only when err is clear and enp is set. mcnt is written by the am79c976 controller and cleared by the host. 230 am79c976 8/01/00 preliminary 54,( * ( 'd ><%c offset bit name description 0 31-0 rbadr[31:0] receive buffer address. this field contains the address of the receive buffer that is associated with this descriptor. 431 own this bit indicates whether the descriptor entry is owned by the host (own = 0) or by the am79c976 controller (own = 1). the host sets the own bit after it has emptied the buffer pointed to by the descriptor entry. the am79c976 controller clears the own bit after filling the buffer that the descriptor points to. both the am79c976 controller and the host must not alter a descriptor entry after it has relinquished ownership. 430 err error summary. err is the or of fram, oflo, and crc. err is set by the am79c976 controller and cleared by the host. 429 fram framing error indicates that the incoming frame contains a non-integer multiple of eight bits and there was an fcs error. if there was no fcs error on the incoming frame, then fram will not be set even if there was a non-integer multiple of eight bits in the frame. fram is not valid in internal loopback mode. fram is valid only when enp is set and oflo is not. fram is set by the am79c976 controller and cleared by the host. 428 oflo overflow error indicates that the receiver has lost all or part of the incoming frame, due to an inability to move data from the receive fifo into a memory buffer before the internal fifo overflowed. oflo is set by the am79c976 controller and cleared by the host. 4 27 crc crc indicates that the receiver has detected a crc (fcs) error on the incoming frame. crc is valid only when enp is set and oflo is not. crc is set by the am79c976 controller and cleared by the host. crc will also be set when am79c976 controller receives an rx_er indication from the external phy through the mii. 4 26 reserved. 425 stp start of packet indicates that this is the first buffer used by the am79c976 controller for this frame. if stp and enp are both set to 1, the frame fits into a single buffer. otherwise, the frame is spread over more than one buffer. when lappen (csr3, bit 5) is cleared to 0, stp is set by the am79c976 controller and cleared by the host. when lappen is set to 1, stp must be set by the host. 424 enp end of packet indicates that this is the last buffer used by the am79c976 controller for this frame. it is used for data chaining buffers. if both stp and enp are set, the frame fits into one buffer and there is no data chaining. enp is set by the am79c976 controller and cleared by the host. 4 23 reserved. 422 pam physical address match is set by the am79c976 controller when it accepts the received frame due to a match of the frame ? s destination address with the content of the physical address register. pam is valid only when enp is set. pam is set by the am79c976 controller and cleared by the host. this bit does not exist when the am79c976 controller is programmed to use 16-bit software structures for the descriptor ring entries (bcr20, bits 7-0, swstyle is cleared to 0). 8/01/00 am79c976 231 preliminary 421 lafm logical address filter match is set by the am79c976 controller when it accepts the received frame based on the value in the logical address filter register. lafm is valid only when enp is set. lafm is set by the am79c976 controller and cleared by the host. note that if drcvbc (csr15, bit 14) is cleared to 0, only bam, but not lafm will be set when a broadcast frame is received, even if the logical address filter is programmed in such a way that a broadcast frame would pass the hash filter. if drcvbc is set to 1 and the logical address filter is programmed in such a way that a broadcast frame would pass the hash filter, lafm will be set on the reception of a broadcast frame. this bit does not exist when the am79c976 controller is programmed to use 16-bit software structures for the descriptor ring entries (bcr20, bits 7-0, swstyle is cleared to 0). 4 20 bam broadcast address match is set by the am79c976 controller when it accepts the received frame, because the frame ? s destination address is of the type ? broadcast. ? bam is valid only when enp is set. bam is set by the am79c976 controller and cleared by the host. this bit does not exist when the am79c976 controller is programmed to use 16-bit software structures for the descriptor ring entries (bcr20, bits 7-0, swstyle is cleared to 0). 4 19-16 reserved. 415-0 bcnt buffer byte count is the length of the buffer pointed to by this descriptor, expressed as the two ? s complement of the length of the buffer. this field is written by the host and unchanged by the am79c976 controller. 8 31 reserved. 30-16 rfrtag[14:0] receive frame tag. indicates the receive frame tag applied from the eadi interface. this field is user defined and has a default value of all zeros. when rxfrtg (csr7, bit 14) is set to 0, rfrtag will be read as all zeros. see the section on receive frame tagging for details. 15-0 mcnt message byte count is the number of bytes of the received message written to the receive buffer. this is the actual frame length (including fcs) unless stripping is enabled and the length field is < 46 bytes. in this case, mcnt is 14 + length_field. mcnt can take values in the range 15 to 59 and values greater than or equal to 64. mcnt is expressed as an unsigned binary integer. mcnt is valid only when err is clear and enp is set. mcnt is written by the am79c976 controller and cleared by the host. 0ch 31:0 user space user space. reserved for user defined data. offset bit name description 232 am79c976 8/01/00 preliminary 54/( * ( 'd ><%c offset bit name description 0 31 reserved 30-16 rfrtag[14:0] receive frame tag. indicates the receive frame tag applied from the eadi interface. this field is user defined and has a default value of all zeros. when rxfrtg (csr7, bit 14) is set to 0, rfrtag will be read as all zeros. see the section on receive frame tagging for details. 15-0 mcnt message byte count is the number of bytes of the received message written to the receive buffer. this is the actual frame length (including fcs) unless stripping is enabled and the length field is < 46 bytes. in this case, mcnt is 14 + length_field. mcnt can take values in the range 15 to 59 and values greater than or equal to 64. mcnt is expressed as an unsigned binary integer. mcnt is valid only when err is clear and enp is set. mcnt is written by the am79c976 controller and cleared by the host. 431 own this bit indicates whether the descriptor entry is owned by the host (own = 0) or by the am79c976 controller (own = 1). the host sets the own bit after it has emptied the buffer pointed to by the descriptor entry. the am79c976 controller clears the own bit after filling the buffer that the descriptor points to. both the am79c976 controller and the host must not alter a descriptor entry after it has relinquished ownership. 430 err error summary. err is the or of fram, oflo, and crc. err is set by the am79c976 controller and cleared by the host. 429 fram framing error indicates that the incoming frame contains a non-integer multiple of eight bits and there was an fcs error. if there was no fcs error on the incoming frame, then fram will not be set even if there was a non-integer multiple of eight bits in the frame. fram is not valid in internal loopback mode. fram is valid only when enp is set and oflo is not. fram is set by the am79c976 controller and cleared by the host. 428 oflo overflow error indicates that the receiver has lost all or part of the incoming frame, due to an inability to move data from the receive fifo into a memory buffer before the internal fifo overflowed. oflo is set by the am79c976 controller and cleared by the host. 4 27 crc crc indicates that the receiver has detected a crc (fcs) error on the incoming frame. crc is valid only when enp is set and oflo is not. crc is set by the am79c976 controller and cleared by the host. crc will also be set when am79c976 controller receives an rx_er indication from the external phy through the mii. 4 26 reserved. 425 stp start of packet indicates that this is the first buffer used by the am79c976 controller for this frame. if stp and enp are both set to 1, the frame fits into a single buffer. otherwise, the frame is spread over more than one buffer. when lappen (csr3, bit 5) is cleared to 0, stp is set by the am79c976 controller and cleared by the host. when lappen is set to 1, stp must be set by the host. 424 enp end of packet indicates that this is the last buffer used by the am79c976 controller for this frame. it is used for data chaining buffers. if both stp and enp are set, the frame fits into one buffer and there is no data chaining. enp is set by the am79c976 controller and cleared by the host. 4 23 reserved. 8/01/00 am79c976 233 preliminary 541 ( * ( 'd ><%c" 422 pam physical address match is set by the am79c976 controller when it accepts the received frame due to a match of the frame ? s destination address with the content of the physical address register. pam is valid only when enp is set. pam is set by the am79c976 controller and cleared by the host. this bit does not exist when the am79c976 controller is programmed to use 16-bit software structures for the descriptor ring entries (bcr20, bits 7-0, swstyle is cleared to 0). 421 lafm logical address filter match is set by the am79c976 controller when it accepts the received frame based on the value in the logical address filter register. lafm is valid only when enp is set. lafm is set by the am79c976 controller and cleared by the host. note that if drcvbc (csr15, bit 14) is cleared to 0, only bam, but not lafm will be set when a broadcast frame is received, even if the logical address filter is programmed in such a way that a broadcast frame would pass the hash filter. if drcvbc is set to 1 and the logical address filter is programmed in such a way that a broadcast frame would pass the hash filter, lafm will be set on the reception of a broadcast frame. this bit does not exist when the am79c976 controller is programmed to use 16-bit software structures for the descriptor ring entries (bcr20, bits 7-0, swstyle is cleared to 0). 4 20 bam broadcast address match is set by the am79c976 controller when it accepts the received frame, because the frame ? s destination address is of the type ? broadcast. ? bam is valid only when enp is set. bam is set by the am79c976 controller and cleared by the host. this bit does not exist when the am79c976 controller is programmed to use 16-bit software structures for the descriptor ring entries (bcr20, bits 7-0, swstyle is cleared to 0). 4 19-16 reserved. 4 15-0 bcnt buffer byte count is the length of the buffer pointed to by this descriptor, expressed as the two ? s complement of the length of the buffer. this field is written by the host and unchanged by the am79c976 controller. 8 31-0 rbadr[31:0] receive buffer address. this field contains the address of the receive buffer that is associated with this descriptor. 0ch 31:0 user space user space. reserved for user defined data. offset bit name description 0 31-16 tci[15:0] vlan tag control information copied from the received frame. 15-0 mcnt message byte count is the number of bytes of the received message written to the receive buffer. this is the actual frame length (including fcs) unless stripping is enabled and the length field is < 46 bytes. in this case, mcnt is 14 + length_field. mcnt can take values in the range 15 to 59 and values greater than or equal to 64. mcnt is expressed as an unsigned binary integer. mcnt is valid only when err is clear and enp is set. mcnt is written by the am79c976 controller and cleared by the host. 431 own this bit indicates whether the descriptor entry is owned by the host (own = 0) or by the am79c976 controller (own = 1). the host sets the own bit after it has emptied the buffer pointed to by the descriptor entry. the am79c976 controller clears the own bit after filling the buffer that the descriptor points to. both the am79c976 controller and the host must not alter a descriptor entry after it has relinquished ownership. offset bit name description 234 am79c976 8/01/00 preliminary 430 err error summary. err is the or of fram, oflo, and crc. err is set by the am79c976 controller and cleared by the host. 429 fram framing error indicates that the incoming frame contains a non-integer multiple of eight bits and there was an fcs error. if there was no fcs error on the incoming frame, then fram will not be set even if there was a non-integer multiple of eight bits in the frame. fram is not valid in internal loopback mode. fram is valid only when enp is set and oflo is not. fram is set by the am79c976 controller and cleared by the host. 428 oflo overflow error indicates that the receiver has lost all or part of the incoming frame, due to an inability to move data from the receive fifo into a memory buffer before the internal fifo overflowed. oflo is set by the am79c976 controller and cleared by the host. 4 27 crc crc indicates that the receiver has detected a crc (fcs) error on the incoming frame. crc is valid only when enp is set and oflo is not. crc is set by the am79c976 controller and cleared by the host. crc will also be set when am79c976 controller receives an rx_er indication from the external phy through the mii. 4 26 reserved. 425 stp start of packet indicates that this is the first buffer used by the am79c976 controller for this frame. if stp and enp are both set to 1, the frame fits into a single buffer. otherwise, the frame is spread over more than one buffer. when lappen (csr3, bit 5) is cleared to 0, stp is set by the am79c976 controller and cleared by the host. when lappen is set to 1, stp must be set by the host. 424 enp end of packet indicates that this is the last buffer used by the am79c976 controller for this frame. it is used for data chaining buffers. if both stp and enp are set, the frame fits into one buffer and there is no data chaining. enp is set by the am79c976 controller and cleared by the host. 4 23 reserved. 422 pam physical address match is set by the am79c976 controller when it accepts the received frame due to a match of the frame ? s destination address with the content of the physical address register. pam is valid only when enp is set. pam is set by the am79c976 controller and cleared by the host. this bit does not exist when the am79c976 controller is programmed to use 16-bit software structures for the descriptor ring entries (bcr20, bits 7-0, swstyle is cleared to 0). 421 lafm logical address filter match is set by the am79c976 controller when it accepts the received frame based on the value in the logical address filter register. lafm is valid only when enp is set. lafm is set by the am79c976 controller and cleared by the host. note that if drcvbc (csr15, bit 14) is cleared to 0, only bam, but not lafm will be set when a broadcast frame is received, even if the logical address filter is programmed in such a way that a broadcast frame would pass the hash filter. if drcvbc is set to 1 and the logical address filter is programmed in such a way that a broadcast frame would pass the hash filter, lafm will be set on the reception of a broadcast frame. this bit does not exist when the am79c976 controller is programmed to use 16-bit software structures for the descriptor ring entries (bcr20, bits 7-0, swstyle is cleared to 0). offset bit name description 8/01/00 am79c976 235 preliminary 542( * ( 'd ><%c) 4 20 bam broadcast address match is set by the am79c976 controller when it accepts the received frame, because the frame ? s destination address is of the type ? broadcast. ? bam is valid only when enp is set. bam is set by the am79c976 controller and cleared by the host. this bit does not exist when the am79c976 controller is programmed to use 16-bit software structures for the descriptor ring entries (bcr20, bits 7-0, swstyle is cleared to 0). 4 19-18 tt[1:0] vlan tag type. indicates what type of vlan tag, if any, is included in the received frame. 00 = reserved 01 = frame is untagged 10 = frame is priority-tagged 11 = frame is vlan-tagged 4 17-16 reserved. 4 15-0 bcnt buffer byte count is the length of the buffer pointed to by this descriptor, expressed as the two ? s complement of the length of the buffer. this field is written by the host and unchanged by the am79c976 controller. 8 31-0 rbadr[31:0] receive buffer address. this field contains the address of the receive buffer that is associated with this descriptor. 0ch 31:0 user space user space. reserved for user defined data. offset bit name description 031-0rfrtag[31:0] receive frame tag. indicates the receive frame tag applied from the eadi interface. this field is user defined and has a default value of all zeros. when rxfrtg (csr7, bit 14) is set to 0, rfrtag will be read as all zeros. see the section on receive frame tagging for details. 4 31-16 tci[15:0] vlan tag control information copied from the received frame. 15-0 mcnt message byte count is the number of bytes of the received message written to the receive buffer. this is the actual frame length (including fcs) unless stripping is enabled and the length field is < 46 bytes. in this case, mcnt is 14 + length_field. mcnt can take values in the range 15 to 59 and values greater than or equal to 64. mcnt is expressed as an unsigned binary integer. mcnt is valid only when err is clear and enp is set. mcnt is written by the am79c976 controller and cleared by the host. 831 own this bit indicates whether the descriptor entry is owned by the host (own = 0) or by the am79c976 controller (own = 1). the host sets the own bit after it has emptied the buffer pointed to by the descriptor entry. the am79c976 controller clears the own bit after filling the buffer that the descriptor points to. both the am79c976 controller and the host must not alter a descriptor entry after it has relinquished ownership. 830 err error summary. err is the or of fram, oflo, and crc. err is set by the am79c976 controller and cleared by the host. 829 fram framing error indicates that the incoming frame contains a non-integer multiple of eight bits and there was an fcs error. if there was no fcs error on the incoming frame, then fram will not be set even if there was a non-integer multiple of eight bits in the frame. fram is not valid in internal loopback mode. fram is valid only when enp is set and oflo is not. fram is set by the am79c976 controller and cleared by the host. offset bit name description 236 am79c976 8/01/00 preliminary 828 oflo overflow error indicates that the receiver has lost all or part of the incoming frame, due to an inability to move data from the receive fifo into a memory buffer before the internal fifo overflowed. oflo is set by the am79c976 controller and cleared by the host. 8 27 crc crc indicates that the receiver has detected a crc (fcs) error on the incoming frame. crc is valid only when enp is set and oflo is not. crc is set by the am79c976 controller and cleared by the host. crc will also be set when am79c976 controller receives an rx_er indication from the external phy through the mii. 8 26 reserved. 825 stp start of packet indicates that this is the first buffer used by the am79c976 controller for this frame. if stp and enp are both set to 1, the frame fits into a single buffer. otherwise, the frame is spread over more than one buffer. when lappen (csr3, bit 5) is cleared to 0, stp is set by the am79c976 controller and cleared by the host. when lappen is set to 1, stp must be set by the host. 824 enp end of packet indicates that this is the last buffer used by the am79c976 controller for this frame. it is used for data chaining buffers. if both stp and enp are set, the frame fits into one buffer and there is no data chaining. enp is set by the am79c976 controller and cleared by the host. 8 23 reserved. 822 pam physical address match is set by the am79c976 controller when it accepts the received frame due to a match of the frame ? s destination address with the content of the physical address register. pam is valid only when enp is set. pam is set by the am79c976 controller and cleared by the host. this bit does not exist when the am79c976 controller is programmed to use 16-bit software structures for the descriptor ring entries (bcr20, bits 7-0, swstyle is cleared to 0). 821 lafm logical address filter match is set by the am79c976 controller when it accepts the received frame based on the value in the logical address filter register. lafm is valid only when enp is set. lafm is set by the am79c976 controller and cleared by the host. note that if drcvbc (csr15, bit 14) is cleared to 0, only bam, but not lafm will be set when a broadcast frame is received, even if the logical address filter is programmed in such a way that a broadcast frame would pass the hash filter. if drcvbc is set to 1 and the logical address filter is programmed in such a way that a broadcast frame would pass the hash filter, lafm will be set on the reception of a broadcast frame. this bit does not exist when the am79c976 controller is programmed to use 16-bit software structures for the descriptor ring entries (bcr20, bits 7-0, swstyle is cleared to 0). 8 20 bam broadcast address match is set by the am79c976 controller when it accepts the received frame, because the frame ? s destination address is of the type ? broadcast. ? bam is valid only when enp is set. bam is set by the am79c976 controller and cleared by the host. this bit does not exist when the am79c976 controller is programmed to use 16-bit software structures for the descriptor ring entries (bcr20, bits 7-0, swstyle is cleared to 0). 8 19-18 tt[1:0] vlan tag type. indicates what type of vlan tag, if any, is included in the received frame. 00 = reserved 01 = frame is untagged 10 = frame is priority-tagged 11 = frame is vlan-tagged 8 17-16 reserved. offset bit name description 8/01/00 am79c976 237 preliminary 815-0 bcnt buffer byte count is the length of the buffer pointed to by this descriptor, expressed as the two ? s complement of the length of the buffer. this field is written by the host and unchanged by the am79c976 controller. 0ch 31-0 rbadr[31:0] receive buffer address. this field contains the low order bits of the address of the receive buffer that is associated with this descriptor. 10h 31-0 rbadr[63:32] receive buffer address. this field contains the high order bits of the address of the receive buffer that is associated with this descriptor. 14h 31:0 user space user space. reserved for user defined data. 18h 31:0 user space user space. reserved for user defined data. 1ch 31:0 user space user space. reserved for user defined data. offset bit name description 238 am79c976 8/01/00 preliminary transmit descriptors when swstyle (bcr20, bits 7-0) is set to 0, the soft- ware structures are defined to be 16 bits wide, and transmit descriptors look like table 110. when swstyle is set to 2, the software structures are defined to be 32 bits wide, and transmit descriptors look like table 111. when swstyle is set to 3, then the software struc- tures are defined to be 32 bits wide, and transmit de- scriptors look like table 112. when swstyle is set to 4, then the software struc- tures are defined to be 32 bits wide, and transmit de- scriptors look like table 113. when swstyle is set to 5, then the software struc- tures are defined to be 32 bits wide, and transmit de- scriptors look like table 114. also when swstyle is 5, the am79c976 controller uses 64-bit addressing for software structures that are located above the 32-bit address boundary. 54 ! * ( ': ><%c4; offset 15 14 13 12 11 10 9 8 7-0 00h tbadr[15:0] 02h own add_ fcs lti n t stp enp tbadr[23:16] 04h bcnt 06h reserved 5 ! * ( ': ><%c ; offset 31 30 29 28 27 26 25 24 23 22-16 15-12 11-4 3-0 00h tbadr[31:0] 04h own add_ fcs lt in t stp enp bcnt 08h reserved 0ch user space 5 ! * ( ': ><%c ; offset 31 30 29 28 27 26 25 24 23 22-16 15-0 00h reserved 04h own add_ fcs lt in t stp enp bcnt 08h tbadr[31:0] 0ch user space 5 ! * ( ': ><%c"; offset 31 30 29 28 27-26 25 24 23 22 21-18 17-16 15-0 00h own add_ fcs lt in t stp enp kill bcnt 04h tcc[1:0] tci[15:0] 08h tbadr[31:0] 0ch user space 8/01/00 am79c976 239 preliminary the following tables describe the transmit descriptor bits in more detail. 5) ! * ( 'd ><%c4 5" ! * ( ': ><%c); offset 31 30 29 28 27-26 25 24 23 22 21-18 17-16 15-0 00h own add_ fcs lt in t stp enp kill bcnt 04h tcc[1:0] tci[15:0] 08h tbadr[31:0] 0ch tbadr[63:32] 10h reserved 14h user space 18h user space 1ch user space offset bit name description 0 15-0 tbadr[15:0] transmit buffer address. this field contains the high order bits of the address of the transmit buffer that is associated with this descriptor. 215 own this bit indicates whether the descriptor entry is owned by the host (own = 0) or by the am79c976 controller (own = 1). the host sets the own bit after filling the buffer pointed to by the descriptor entry. the am79c976 controller clears the own bit after transmitting the contents of the buffer. both the am79c976 controller and the host must not alter a descriptor entry after it has relinquished ownership. 2 14 reserved location . 2 13 add_fcs add_fcs dynamically controls the generation of fcs on a frame by frame basis. this bit should be set with the enp bit. however, for backward compatibility, it is recommended that this bit be set for every descriptor of the intended frame. when add_fcs is set, the state of dxmtfcs is ignored and transmitter fcs generation is activated. when add_fcs is cleared to 0, fcs generation is controlled by dxmtfcs. when apad_xmt (csr4, bit 11) is set to 1, the setting of add_fcs has no effect. add_fcs is set by the host, and is not changed by the am79c976 controller. this is a reserved bit in the c-lance (am79c90) controller. 212 ltint last transmit interrupt. when enabled by the ltinten bit (csr5, bit 14), ltint is used to suppress interrupts after selected frames have been copied to the transmit fifo. when ltint is cleared to 0 and enp is set to 1, the am79c976 controller will not set tint (csr0, bit 9) after the corresponding frame has been copied to the transmit fifo. tint will only be set when the last descriptor of a frame has both ltint and enp set to 1. when ltinten is cleared to 0, the ltint bit is ignored. 2 11-10 reserved. 29 stp start of packet indicates that this is the first buffer to be used by the am79c976 controller for this frame. it is used for data chaining buffers. the stp bit must be set in the first buffer of the frame, or the am79c976 controller will skip over the descriptor and poll the next descriptor(s) until the own and stp bits are set. stp is set by the host and is not changed by the am79c976 controller. 28 enp end of packet indicates that this is the last buffer to be used by the am79c976 controller for this frame. it is used for data chaining buffers. if both stp and enp are set, the frame fits into one buffer and there is no data chaining. enp is set by the host and is not changed by the am79c976 controller. 240 am79c976 8/01/00 preliminary 2 7-0 tbadr[23:16] transmit buffer address (high order bits) 4 15-0 bcnt buffer byte count is the usable length of the buffer pointed to by this descriptor, expressed as the two ? s complement of the length of the buffer. this is the number of bytes from this buffer that will be transmitted by the am79c976 controller. this field is written by the host and is not changed by the am79c976 controller. there are no minimum buffer size restrictions. 6 15-0 reserved. offset bit name description 5, ! * ( 'd ><%c offset bit name description 0 31-0 tbadr[31:0] transmit buffer address. this field contains the address of the transmit buffer that is associated with this descriptor. 431 own this bit indicates whether the descriptor entry is owned by the host (own = 0) or by the am79c976 controller (own = 1). the host sets the own bit after filling the buffer pointed to by the descriptor entry. the am79c976 controller clears the own bit after transmitting the contents of the buffer. both the am79c976 controller and the host must not alter a descriptor entry after it has relinquished ownership. 4 30 reserved location . 4 29 add_fcs add_fcs dynamically controls the generation of fcs on a frame by frame basis. this bit should be set with the enp bit. however, for backward compatibility, it is recommended that this bit be set for every descriptor of the intended frame. when add_fcs is set, the state of dxmtfcs is ignored and transmitter fcs generation is activated. when add_fcs is cleared to 0, fcs generation is controlled by dxmtfcs. when apad_xmt (csr4, bit 11) is set to 1, the setting of add_fcs has no effect. add_fcs is set by the host, and is not changed by the am79c976 controller. this is a reserved bit in the c-lance (am79c90) controller. 428 ltint last transmit interrupt. when enabled by the ltinten bit (csr5, bit 14), ltint is used to suppress interrupts after selected frames have been copied to the transmit fifo. when ltint is cleared to 0 and enp is set to 1, the am79c976 controller will not set tint (csr0, bit 9) after the corresponding frame has been copied to the transmit fifo. tint will only be set when the last descriptor of a frame has both ltint and enp set to 1. when ltinten is cleared to 0, the ltint bit is ignored. 4 27-26 reserved. 425 stp start of packet indicates that this is the first buffer to be used by the am79c976 controller for this frame. it is used for data chaining buffers. the stp bit must be set in the first buffer of the frame, or the am79c976 controller will skip over the descriptor and poll the next descriptor(s) until the own and stp bits are set. stp is set by the host and is not changed by the am79c976 controller. 424 enp end of packet indicates that this is the last buffer to be used by the am79c976 controller for this frame. it is used for data chaining buffers. if both stp and enp are set, the frame fits into one buffer and there is no data chaining. enp is set by the host and is not changed by the am79c976 controller. 4 23-16 reserved. 4 15-0 bcnt buffer byte count is the usable length of the buffer pointed to by this descriptor, expressed as the two ? s complement of the length of the buffer. this is the number of bytes from this buffer that will be transmitted by the am79c976 controller. this field is written by the host and is not changed by the am79c976 controller. there are no minimum buffer size restrictions. 8 31-0 reserved 0ch 31-0 user space user space. reserved for user defined data. 8/01/00 am79c976 241 preliminary 5/ ! * ( 'd ><%c offset bit name description 0 31-0 reserved. 431 own this bit indicates whether the descriptor entry is owned by the host (own = 0) or by the am79c976 controller (own = 1). the host sets the own bit after filling the buffer pointed to by the descriptor entry. the am79c976 controller clears the own bit after transmitting the contents of the buffer. both the am79c976 controller and the host must not alter a descriptor entry after it has relinquished ownership. 4 30 reserved location . 4 29 add_fcs add_fcs dynamically controls the generation of fcs on a frame by frame basis. this bit should be set with the enp bit. however, for backward compatibility, it is recommended that this bit be set for every descriptor of the intended frame. when add_fcs is set, the state of dxmtfcs is ignored and transmitter fcs generation is activated. when add_fcs is cleared to 0, fcs generation is controlled by dxmtfcs. when apad_xmt (csr4, bit 11) is set to 1, the setting of add_fcs has no effect. add_fcs is set by the host, and is not changed by the am79c976 controller. this is a reserved bit in the c-lance (am79c90) controller. 428 ltint last transmit interrupt. when enabled by the ltinten bit (csr5, bit 14), ltint is used to suppress interrupts after selected frames have been copied to the transmit fifo. when ltint is cleared to 0 and enp is set to 1, the am79c976 controller will not set tint (csr0, bit 9) after the corresponding frame has been copied to the transmit fifo. tint will only be set when the last descriptor of a frame has both ltint and enp set to 1. when ltinten is cleared to 0, the ltint bit is ignored. 4 27-26 reserved. 425 stp start of packet indicates that this is the first buffer to be used by the am79c976 controller for this frame. it is used for data chaining buffers. the stp bit must be set in the first buffer of the frame, or the am79c976 controller will skip over the descriptor and poll the next descriptor(s) until the own and stp bits are set. stp is set by the host and is not changed by the am79c976 controller. 424 enp end of packet indicates that this is the last buffer to be used by the am79c976 controller for this frame. it is used for data chaining buffers. if both stp and enp are set, the frame fits into one buffer and there is no data chaining. enp is set by the host and is not changed by the am79c976 controller. 4 23-16 reserved. 4 15-0 bcnt buffer byte count is the usable length of the buffer pointed to by this descriptor, expressed as the two ? s complement of the length of the buffer. this is the number of bytes from this buffer that will be transmitted by the am79c976 controller. this field is written by the host and is not changed by the am79c976 controller. there are no minimum buffer size restrictions. 8 31-0 tbadr[31:0] transmit buffer address. this field contains the address of the transmit buffer that is associated with this descriptor. 0ch 31-0 user space user space. reserved for user defined data. 242 am79c976 8/01/00 preliminary 51 ! * ( 'd ><%c" offset bit name description 031 own this bit indicates whether the descriptor entry is owned by the host (own = 0) or by the am79c976 controller (own = 1). the host sets the own bit after filling the buffer pointed to by the descriptor entry. the am79c976 controller clears the own bit after transmitting the contents of the buffer. both the am79c976 controller and the host must not alter a descriptor entry after it has relinquished ownership. 0 30 reserved location . 0 29 add_fcs add_fcs dynamically controls the generation of fcs on a frame by frame basis. this bit should be set with the enp bit. however, for backward compatibility, it is recommended that this bit be set for every descriptor of the intended frame. when add_fcs is set, the state of dxmtfcs is ignored and transmitter fcs generation is activated. when add_fcs is cleared to 0, fcs generation is controlled by dxmtfcs. when apad_xmt (csr4, bit 11) is set to 1, the setting of add_fcs has no effect. add_fcs is set by the host, and is not changed by the am79c976 controller. this is a reserved bit in the c-lance (am79c90) controller. 028 ltint last transmit interrupt. when enabled by the ltinten bit (csr5, bit 14), ltint is used to suppress interrupts after selected frames have been copied to the transmit fifo. when ltint is cleared to 0 and enp is set to 1, the am79c976 controller will not set tint (csr0, bit 9) after the corresponding frame has been copied to the transmit fifo. tint will only be set when the last descriptor of a frame has both ltint and enp set to 1. when ltinten is cleared to 0, the ltint bit is ignored. 0 27-26 reserved. 025 stp start of packet indicates that this is the first buffer to be used by the am79c976 controller for this frame. it is used for data chaining buffers. the stp bit must be set in the first buffer of the frame, or the am79c976 controller will skip over the descriptor and poll the next descriptor(s) until the own and stp bits are set. stp is set by the host and is not changed by the am79c976 controller. 024 enp end of packet indicates that this is the last buffer to be used by the am79c976 controller for this frame. it is used for data chaining buffers. if both stp and enp are set, the frame fits into one buffer and there is no data chaining. enp is set by the host and is not changed by the am79c976 controller. 0 23 reserved. 022 kill this bit causes the transmission of the corresponding frame to be aborted. if the transmitter has not started sending the frame at the time that the descriptor processing logic encounters the kill bit, no portion of the frame will be sent. if part of the frame has been sent, the frame will be truncated, and an fcs field containing the inverse of the correct crc will be appended. 0 21-16 reserved. 0 15-0 bcnt buffer byte count is the usable length of the buffer pointed to by this descriptor, expressed as the two ? s complement of the length of the buffer. this is the number of bytes from this buffer that will be transmitted by the am79c976 controller. this field is written by the host and is not changed by the am79c976 controller. there are no minimum buffer size restrictions. 4 31-18 reserved. 4 17-16 tcc[1:0] vlan tag control command. this field contains a command that causes the transmitter to add, modify, or delete a vlan tag or to transmit the frame unaltered. 00 = transmit the data in the buffer unaltered 01 = delete the vlan tag (the 13th through 16th bytes of the frame) 10 = insert a vlan tag containing the tci field from the descriptor 11 = replace the tci field of the frame with tci data from the descriptor 8/01/00 am79c976 243 preliminary 52 ! * ( 'd ><%c) 4 15-0 tci[15:0] tag control information. if the contents of the tcc field is 10 or 11, the controller will transmit the contents of the tci field as bytes 15 and 16 of the outgoing frame. 8 31-0 tbadr[31:0] transmit buffer address. this field contains the address of the transmit buffer that is associated with this descriptor. 0ch 31-0 user space user space. reserved for user defined data. offset bit name description 031 own this bit indicates whether the descriptor entry is owned by the host (own = 0) or by the am79c976 controller (own = 1). the host sets the own bit after filling the buffer pointed to by the descriptor entry. the am79c976 controller clears the own bit after transmitting the contents of the buffer. both the am79c976 controller and the host must not alter a descriptor entry after it has relinquished ownership. 0 30 reserved location . 0 29 add_fcs add_fcs dynamically controls the generation of fcs on a frame by frame basis. this bit should be set with the enp bit. however, for backward compatibility, it is recommended that this bit be set for every descriptor of the intended frame. when add_fcs is set, the state of dxmtfcs is ignored and transmitter fcs generation is activated. when add_fcs is cleared to 0, fcs generation is controlled by dxmtfcs. when apad_xmt (csr4, bit 11) is set to 1, the setting of add_fcs has no effect. add_fcs is set by the host, and is not changed by the am79c976 controller. this is a reserved bit in the c-lance (am79c90) controller. 028 ltint last transmit interrupt. when enabled by the ltinten bit (csr5, bit 14), ltint is used to suppress interrupts after selected frames have been copied to the transmit fifo. when ltint is cleared to 0 and enp is set to 1, the am79c976 controller will not set tint (csr0, bit 9) after the corresponding frame has been copied to the transmit fifo. tint will only be set when the last descriptor of a frame has both ltint and enp set to 1. when ltinten is cleared to 0, the ltint bit is ignored. 0 27-26 reserved. 025 stp start of packet indicates that this is the first buffer to be used by the am79c976 controller for this frame. it is used for data chaining buffers. the stp bit must be set in the first buffer of the frame, or the am79c976 controller will skip over the descriptor and poll the next descriptor(s) until the own and stp bits are set. stp is set by the host and is not changed by the am79c976 controller. 024 enp end of packet indicates that this is the last buffer to be used by the am79c976 controller for this frame. it is used for data chaining buffers. if both stp and enp are set, the frame fits into one buffer and there is no data chaining. enp is set by the host and is not changed by the am79c976 controller. 0 23 reserved. 022 kill this bit causes the transmission of the corresponding frame to be aborted. if the transmitter has not started sending the frame at the time that the descriptor processing logic encounters the kill bit, no portion of the frame will be sent. if part of the frame has been sent, the frame will be truncated, and an fcs field containing the inverse of the correct crc will be appended. 0 21-16 reserved. offset bit name description 244 am79c976 8/01/00 preliminary 0 15-0 bcnt buffer byte count is the usable length of the buffer pointed to by this descriptor, expressed as the two ? s complement of the length of the buffer. this is the number of bytes from this buffer that will be transmitted by the am79c976 controller. this field is written by the host and is not changed by the am79c976 controller. there are no minimum buffer size restrictions. 4 31-18 reserved. 4 17-16 tcc[1:0] vlan tag control command. this field contains a command that causes the transmitter to add, modify, or delete a vlan tag or to transmit the frame unaltered. 00 = transmit the data in the buffer unaltered 01 = delete the vlan tag (the 13th through 16th bytes of the frame) 10 = insert a vlan tag containing the tci field from the descriptor 11 = replace the tci field of the frame with tci data from the descriptor 4 15-0 tci[15:0] tag control information. if the contents of the tcc field are 10 or 11, the controller will transmit the contents of the tci field as bytes 15 and 16 of the outgoing frame. 8 31-0 tbadr[31:0] transmit buffer address. this field contains the low order bits of the address of the transmit buffer that is associated with this descriptor. 0ch 31-0 tbadr[63:32] transmit buffer address. this field contains the high order bits of the address of the transmit buffer that is associated with this descriptor. 10h 31-0 reserved. 14h 31-0 user space user space. reserved for user defined data. 18h 31-0 user space user space. reserved for user defined data. 1ch 31-0 user space user space. reserved for user defined data. offset bit name description 8/01/00 am79c976 245 preliminary register summary pci configuration registers note : ro = read only, rw = read/write offset name width in bit access mode default value 00h pci vendor id 16 ro 1022h 02h pci device id 16 ro 2000h 04h pci command 16 rw 0000h 06h pci status 16 rw 0290h 08h pci revision id 8 ro 51h 09h pci programming if 8 ro 00h 0ah pci sub-class 8 ro 00h 0bh pci base-class 8 ro 02h 0ch pci cache line size 8 r/w 00h 0dh pci latency timer 8 rw 00h 0eh pci header type 8 ro 00h 0fh reserved 8 ro 00h 10h pci i/o base address 32 rw 0000 0001h 14h pci memory mapped i/o base address 32 rw 0000 0000h 18h - 2bh reserved 8 ro 00h 2ch pci subsystem vendor id 16 ro 00h 2eh pci subsystem id 16 ro 00h 30h pci expansion rom base address 32 rw 0000 0000h 31h - 33h reserved 8 ro 00h 34h capabilities pointer 8 ro 44h 35h-3bh reserved 8 ro 00h 3ch pci interrupt line 8 rw 00h 3dh pci interrupt pin 8 ro 01h 3eh pci min_gnt 8 ro 06h 3fh pci max_lat 8 ro ffh 44h pci capability identifier 8 ro 01h 45h pci next item pointer 8 ro 00h 46h pci power management capabilities 16 ro c802h 48h pci power management control/status 16 ro 00h 4ah pci pmcsr bridge support extensions 8 ro 00h 4bh pci data 8 ro 00h 4ch - ffh reserved 8 ro 00h 246 am79c976 8/01/00 preliminary memory-mapped registers register offset, hex width, bits reset value reset type notes ap_value0 0a8 16 0 h auto-poll register 0 value ap_value1 0aa 16 0 h auto-poll register 1 value ap_value2 0ac 16 0 h auto-poll register 2 value ap_value3 0ae 16 0 h auto-poll register 3 value ap_value4 0b0 16 0 h auto-poll register 4 value ap_value5 0b2 16 0 h auto-poll register 5 value autopoll0 88 16 8100 e,h auto-poll register 1 autopoll1 8a 16 0 e,h auto-poll register 2 autopoll2 8c 16 0 e,h auto-poll register 3 autopoll3 8e 16 0 e,h auto-poll register 4 autopoll4 90 16 0 e,h auto-poll register 5 autopoll5 92 16 0 e,h auto-poll register 6 badr 120 64 0 h base address of receive descriptor ring badx 100 64 0 h base address of transmit descriptor ring chipid 0f0 32 x262 8003 h chip id. read only chpolltime 18a 16 0 e,h chain poll timer register cmd0 48 32 0 e,h command 0 cmd2 50 32 0 e,h command 2 cmd3 54 32 0 e,h command 3 cmd7 64 32 0 p command 7 ctrl0 68 32 0000 0900 e,h control 0 ctrl1 6c 32 0001 0001 e,h control 1 ctrl2 70 32 0000 0004 e,h control 2 ctrl3 74 32 0 h control 3 datambist 1a0 64 0 h mbist access register delayed_int 0c0 32 0 e,h delayed interrupts register eeprom_acc 17c 16 0 h eeprom access register flash_addr 198 32 0 h flash address register flash_data 19c 16 0 h flash data register flow 0c8 32 0 e,h flow control register ifs1 18c 8 3c e,h inter-frame spacing, part 1 register int0 38 32 0 interrupt 0. read only or write 1 to clear. all bits cleared by h_reset. bits 0, 5, 6, & 8 also cleared when run is cleared. inten0 40 32 0 e,h interrupt enable 0. ipg 18d 8 60 e,h inter-packet gap register 8/01/00 am79c976 247 preliminary note: h = h_reset, e = ee_reset, p = power on reset ladrf 168 64 0 h logical address filter register led0 0e0 16 00c0 e,h led 0 control led1 0e2 16 0094 e,h led 1 control led2 0e4 16 1080 e,h led 2 control led3 0e6 16 0081 e,h led 3 control max_lat_a 1b1 8 18h e,h pci maximum latency shadow register min_gnt_a 1b0 8 18h e,h pci minimum grant shadow register padr 160 48 0 h physical address register pause_cnt 0de 32 0 h pause count. read only. pcidata0 1bc 16 0 e,h pci data register 0 alias register pcidata1 1be 16 0 e,h pci data register 1 alias register pcidata2 1c0 16 0 e,h pci data register 2 alias register pcidata3 1c2 16 0 e,h pci data register 3 alias register pcidata4 1c4 16 0 e,h pci data register 4 alias register pcidata5 1c6 16 0 e,h pci data register 5 alias register pcidata6 1c8 16 0 e,h pci data register 6 alias register pcidata7 1ca 16 0 e,h pci data register 7 alias register phy_access 0d0 32 0 h phy access pmat0 190 32 0 h onnow pattern register 0 pmat1 194 16 0 h onnow pattern register 1 pmc_a 1b8 16 c802h e,h pci power management capabilities shadow register rcv_protect 0dc 16 40 h receive protect register. rcv_ring_len 150 16 0 h receive descriptor ring length. two ? s- complement. rom_cfg 18e 16 0 h rombase configuration register sid_a 1b4 16 0 e,h pci subsystem id shadow register sram_bnd 17a 16 0 e,h ssram boundary sram_size 178 16 0 e,h ssram size stat0 30 32 0 status 0. read only or write 1 to clear. bits 12-10 are reset by por. all others are reset by h_reset. stval 0d8 16 ffff h software timer value svid_a 1b6 16 0 e,h subsystem vendor id shadow register vid_a 1b2 16 1022 e,h pci vendor id shadow register xmt_ring_len 140 16 0 h transmit descriptor ring length. two ? s- complement. xmtpolltime 188 16 0 e,h transmit polling interval register register offset, hex width, bits reset value reset type notes 248 am79c976 8/01/00 preliminary control and status registers rap addr symbol default value comments use 00 csr0 uuuu 0004 am79c976 controller status and control register r 01 csr1 uuuu uuuu lower iadr: maps to location 16 s 02 csr2 uuuu uuuu upper iadr: maps to location 17 s 03 csr3 uuuu 0600 interrupt masks and deferral control s 04 csr4 uuuu 0004 test and features control r 05 csr5 uuuu 0000 extended control and interrupt 1 r 06 csr6 uuuu uuuu reserved 07 csr7 0uuu 0000 extended control and interrupt 2 r 08 csr8 uuuu uuuu ladrf0: logical address filter ? ladrf[15:0] s 09 csr9 uuuu uuuu ladrf1: logical address filter ? ladrf[31:16] s 10 csr10 uuuu uuuu ladrf2: logical address filter ? ladrf[47:32] s 11 csr11 uuuu uuuu ladrf3: logical address filter ? ladrf[63:48] s 12 csr12 uuuu uuuu padr0: physical address register ? padr[15:0] s 13 csr13 uuuu uuuu padr1: physical address register ? padr[31:16] s 14 csr14 uuuu uuuu padr2: physical address register ? padr[47:32] s 15 csr15 see register description mode: mode register s 16 csr16 uuuu uuuu reserved 17 csr17 uuuu uuuu reserved 18 csr18 uuuu uuuu reserved 19 csr19 uuuu uuuu reserved 20 csr20 uuuu uuuu reserved 21 csr21 uuuu uuuu reserved 22 csr22 uuuu uuuu reserved 23 csr23 uuuu uuuu reserved 24 csr24 uuuu uuuu badrl: base address of rcv ring lower s 25 csr25 uuuu uuuu badru: base address of rcv ring upper s 26 csr26 uuuu uuuu reserved 27 csr27 uuuu uuuu reserved 28 csr28 uuuu uuuu reserved 29 csr29 uuuu uuuu reserved 30 csr30 uuuu uuuu badxl: base address of xmt ring lower s 31 csr31 uuuu uuuu badxu: base address of xmt ring upper s 32 csr32 uuuu uuuu reserved 33 csr33 uuuu uuuu reserved 8/01/00 am79c976 249 preliminary 34 csr34 uuuu uuuu reserved 35 csr35 uuuu uuuu reserved 36 csr36 uuuu uuuu reserved 37 csr37 uuuu uuuu reserved 38 csr38 uuuu uuuu reserved 39 csr39 uuuu uuuu reserved 40 csr40 uuuu uuuu reserved 41 csr41 uuuu uuuu reserved 42 csr42 uuuu uuuu reserved 43 csr43 uuuu uuuu reserved 44 csr44 uuuu uuuu reserved 45 csr45 uuuu uuuu reserved 46 csr46 uuuu uuuu reserved 47 csr47 uuuu uuuu txpollint: transmit polling interval s 48 csr48 uuuu uuuu reserved 49 csr49 uuuu uuuu chpollint: chain polling interval 50 csr50 uuuu uuuu reserved 51 csr51 uuuu uuuu reserved 52 csr52 uuuu uuuu reserved 53 csr53 uuuu uuuu reserved 54 csr54 uuuu uuuu reserved 55 csr55 uuuu uuuu reserved 56 csr56 uuuu uuuu reserved 57 csr57 uuuu uuuu reserved 58 csr58 see register description sws: software style s 59 csr59 uuuu uuuu reserved t 60 csr60 uuuu uuuu reserved 61 csr61 uuuu uuuu reserved 62 csr62 uuuu uuuu reserved 63 csr63 uuuu uuuu reserved 64 csr64 uuuu uuuu reserved 65 csr65 uuuu uuuu reserved 66 csr66 uuuu uuuu reserved 67 csr67 uuuu uuuu reserved 68 csr68 uuuu uuuu reserved 69 csr69 uuuu uuuu reserved rap addr symbol default value comments use 250 am79c976 8/01/00 preliminary 70 csr70 uuuu uuuu reserved 71 csr71 uuuu uuuu reserved 72 csr72 uuuu uuuu reserved 73 csr73 uuuu uuuu reserved 74 csr74 uuuu uuuu reserved 75 csr75 uuuu uuuu reserved 76 csr76 uuuu uuuu rcvrl: rcv ring length s 77 csr77 uuuu uuuu reserved 78 csr78 uuuu uuuu xmtrl: xmt ring length s 79 csr79 uuuu uuuu reserved 80 csr80 uuuu 1400 dmatcfw: dma transfer counter and fifo threshold control s 81 csr81 uuuu uuuu reserved 82 csr82 uuuu uuuu reserved 83 csr83 uuuu uuuu reserved 84 csr84 uuuu uuuu reserved 85 csr85 uuuu uuuu reserved 86 csr86 uuuu uuuu reserved 87 csr87 uuuu uuuu reserved 88 csr88 x262 8003 chip id register lower t 89 csr89 uuuu x262 chip id register upper t 90 csr90 uuuu uuuu reserved 91 csr91 uuuu uuuu reserved 92 csr92 uuuu uuuu reserved 93 csr93 uuuu uuuu reserved 94 csr94 uuuu uuuu reserved 95 csr95 uuuu uuuu reserved 96 csr96 uuuu uuuu reserved 97 csr97 uuuu uuuu reserved 98 csr98 uuuu uuuu reserved 99 csr99 uuuu uuuu reserved 100 csr100 uuuu uuuu bus timeout 0 101 csr101 uuuu uuuu reserved 102 csr102 uuuu uuuu reserved 103 csr103 uuuu 0000 reserved 104 csr104 uuuu uuuu reserved 105 csr105 uuuu uuuu reserved 106 csr106 uuuu uuuu reserved rap addr symbol default value comments use 8/01/00 am79c976 251 preliminary note: u = undefined value, r = running register, s = setup register, t = test register; all default values are in hexadecimal format. o = obsolete register 107 csr107 uuuu uuuu reserved 108 csr108 uuuu uuuu reserved 109 csr109 uuuu uuuu reserved 110 csr110 uuuu uuuu reserved 111 csr111 uuuu uuuu reserved 112 csr112 uuuu uuuu missed frame count o 113 csr113 uuuu uuuu reserved 114 csr114 uuuu uuuu receive collision count o 115 csr115 uuuu uuuu reserved 116 csr116 0000 0000 onnow power mode register s 117 csr117 uuuu uuuu reserved 118 csr118 uuuu uuuu reserved 119 csr119 uuuu 0000 reserved 120 csr120 uuuu uuuu reserved 121 csr121 uuuu uuuu reserved 122 csr122 uuuu 0000 advanced feature control s 123 csr123 uuuu uuuu reserved 124 csr124 uuuu 0000 test register 1 t 125 csr125 uuuu 603c mac enhanced configuration control t 126 csr126 uuuu uuuu reserved 127 csr127 uuuu uuuu reserved rap addr symbol default value comments use 252 am79c976 8/01/00 preliminary bus configuration registers writes to those registers marked as ? reserved ? will have no effect. reads from these locations will produce undefined values. rap mnemonic default name programmability user eeprom 0 msrda 0005h reserved no no 1 mswra 0005h reserved no no 2 mc 0000h miscellaneous configuration yes yes 3 reserved n/a reserved no no 4 led0 00c0h led0 status yes yes 5 led1 0094h led1 status yes yes 6 led2 1080h led2 status yes yes 7 led3 0081h led3 status yes yes 8 reserved n/a reserved no no 9 fdc 0004h full-duplex control yes yes 10-15 reserved n/a reserved no no 16 iobasel n/a reserved no no 17 iobaseu n/a reserved no no 18 bsbc 9000h burst and bus control yes yes 19 eecas 0000h eeprom control and status yes no 20 sws 0000h software style yes no 21 reserved n/a reserved no no 22 pcilat 1818h pci latency yes yes 23 pcisid 0000h pci subsystem id no yes 24 pcisvid 0000h pci subsystem vendor id no yes 25 sramsize 0000h sram size yes yes 26 srambnd 0000h sram boundary yes yes 27 reserved n/a reserved no no 28 ebaddrl n/a expansion bus address lower yes no 29 ebaddru n/a expansion bus address upper yes no 30 ebdata n/a expansion bus data port yes no 31 stval ffffh software timer value yes no 32 miicas 0400h mii control and status yes yes 33 miiaddr n/a mii address yes yes 34 miimdr n/a mii management data yes no 35 pcivid 1022h pci vendor id no yes 36 pmc_a c802h pci power management capabilities (pmc) alias register no yes 37 data0 0000h pci data register zero alias register no yes 38 data1 0000h pci data register one alias register no yes 39 data2 0000h pci data register two alias register no yes 40 data3 0000h pci data register three alias register no yes 41 data4 0000h pci data register four alias register no yes 42 data5 0000h pci data register five alias register no yes 43 data6 0000h pci data register six alias register no yes 44 data7 0000h pci data register seven alias register no yes 45 pmr1 n/a pattern matching register 1 yes no 46 pmr2 n/a pattern matching register 2 yes no 47 pmr3 n/a pattern matching register 3 yes no 8/01/00 am79c976 253 preliminary register bit cross reference table 120 shows the location and default value for each programmable bit or field. the offset column gives the offset in hexadecimal of the register that contains the bit. the codes in the reset type column have the fol- lowing meanings: in many cases, a particular bit can be accessed through more than one register. for these bits, the columns, ? alternate reg. ? , ? bit num ? , and ? alternate bit name," give the alternate access paths. 5 4 ( h hardware reset. the bit is set to its default value when the rst pin is asserted (low). e eeprom reset. the bit is set to its default value when before the eeprom is read or after an eeprom read error is detected p power on reset. the bit is set to its default value when power is first applied to the device. bit name register bit num offset (hex) default value reset type alternate register bit num bit name antst test0 8 1a8 0 e,h bcr32 15 antst ap_phy0_ addr autopoll0 4:0 88 0 e,h ap_phy1_ addr autopoll1 4:0 8a 0 e,h ap_phy1_ dflt autopoll1 5 8a 0 e,h ap_phy2_ addr autopoll2 4:0 8c 0 e,h ap_phy2_ dflt autopoll2 5 8c 0 e,h ap_phy3_ addr autopoll3 4:0 8e 0 e,h ap_phy3_ dflt autopoll3 5 8e 0 e,h ap_phy4_ addr autopoll4 4:0 90 0 e,h ap_phy4_ dflt autopoll4 5 90 0 e,h ap_phy5_ addr autopoll5 4:0 92 0 e,h ap_phy5_ dflt autopoll5 5 92 0 e,h ap_pre_ sup1 autopoll1 6 8a 0 e,h ap_pre_ sup2 autopoll2 6 8c 0 e,h 254 am79c976 8/01/00 preliminary ap_pre_ sup3 autopoll3 6 8e 0 e,h ap_pre_ sup4 autopoll4 6 90 0 e,h ap_pre_ sup5 autopoll5 6 92 0 e,h ap_reg0_ addr autopoll0 12:8 88 1 e,h ap_reg0_en autopoll0 15 88 1 e,h ap_reg1_ addr autopoll1 12:8 8a 0 e,h ap_reg1_en autopoll1 15 8a 0 e,h ap_reg2_ addr autopoll2 12:8 8c 0 e,h ap_reg2_en autopoll2 15 8c 0 e,h ap_reg3_ addr autopoll3 12:8 8e 0 e,h ap_reg3_en autopoll3 15 8e 0 e,h ap_reg4_ addr autopoll4 12:8 90 0 e,h ap_reg4_en autopoll4 15 90 0 e,h ap_reg5_ addr autopoll5 12:8 92 0 e,h ap_reg5_en autopoll5 15 92 0 e,h ap_value0 ap_value0 15:0 0ab 0 h ap_value1 ap_value1 15:0 0aa 0 h ap_value2 ap_value2 15:0 0ac 0 h ap_value3 ap_value3 15:0 0ae 0 h ap_value4 ap_value4 15:0 0b0 0 h ap_value5 ap_value5 15:0 0b2 0 h apad_xmt cmd2 6 50 0 e,h csr4 11 apad_xmt apdw ctrl2 2:0 70 4 e,h bcr32 10:8 apdw apep cmd3 24 54 0 e,h bcr32 11 apep apint0 int0 20 38 0 h apint0en inten0 20 40 0 e,h apint1 int0 21 38 0 h apint1en inten0 21 40 0 e,h apint2 int0 22 38 0 h apint2en inten0 22 40 0 e,h bit name register bit num offset (hex) default value reset type alternate register bit num bit name 8/01/00 am79c976 255 preliminary apint3 int0 24 38 0 h apint3en inten0 24 40 0 e,h apint4 int0 25 38 0 h apint4en inten0 25 40 0 e,h apint5 int0 26 38 0 h apint5en inten0 26 40 0 e,h apromwe cmd2 27 50 0 e,h bcr2 8 apromwe astrp_rcv cmd2 13 50 0 e,h csr4 10 astrp_rcv autoneg_ complete stat0 4 30 0 h badr badr 63:32 104 0 h badr badr 31:16 104 0 h csr25 15:0 badru badr badr 15:0 104 0 h csr24 15:0 badrl badx badx 63:32 100 0 h badx badx 31:16 100 0 h csr31 15:0 badxu badx badx 15:0 100 0 h csr30 15:0 badxl bfd_scale_ down test0 9 1a8 0 e,h bcr33 15 bfd_scale_ down bswp ctrl0 24 68 0 e,h csr3 2 bswp burst_align ctrl0 4 68 0 e,h burst_limit ctrl0 3:0 68 0 e,h cbio_en test0 17 1a8 0 e,h chdpoll cmd2 1 50 0 e,h csr7 12 chdpoll chipid chipid 31:0 0f0 x262 8003h h chpolltime chpolltime 15:0 18a 0 e,h csr49 15:0 rxpollint disable_mwi cmd3 27 54 0 e,h dis_ read_wait cmd3 29 54 0 e,h dis_ write_wait cmd3 28 54 0 e,h dispm cmd3 14 54 0 e,h bcr32 7 dispm dm_dir datambist 56 1a0 0 h dm_data datambist 31:0 1a0 0 h dm_backg datambist 53:52 1a0 0 h dm_addr datambist 51:32 1a0 0 h dm_done datambist 63 1a0 0 h dm_error datambist 62 1a0 0 h bit name register bit num offset (hex) default value reset type alternate register bit num bit name 256 am79c976 8/01/00 preliminary dm_fail_ state datambist 55:54 1a0 0 h dm_fail_ stop datambist 59 1a0 0 h dm_test_ fail datambist 58 1a0 0 h dm_resume datambist 60 1a0 0 h dm_start datambist 61 1a0 0 h drcvbc cmd2 17 50 0 e,h csr15 14 drcvbc drcvpa cmd2 18 50 0 e,h csr15 13 drcvpa drty cmd2 5 50 0 e,h csr15 5 drty dwio cmd2 28 50 0 e,h bcr18 7 dwio dxmt2pd cmd2 10 50 0 e,h csr3 4 dxmt2pd dxmtfcs cmd2 8 50 0 e,h csr15 3 dxmtfcs ecs eeprom_ acc 2 17c 0 h bcr19 2 ecs edi/edo eeprom_ acc 0 17c 0 h bcr19 0 edi/edo eebusy_t test0 13 1a8 0 e,h bcr33 11 eebusy_t eedet eeprom_ acc 13 17c 0 h bcr19 13 eedet een eeprom_ acc 4 17c 0 h bcr19 4 een esk eeprom_ acc 1 17c 0 h bcr19 1 esk emba cmd2 11 50 0 e,h csr3 3 emba event_ count delayed_ int 20:16 0c0 0 e,h exloop cmd2 3 50 0 e,h fccmd flow_ control 16 0c8 0 e,h fcoll cmd2 12 50 0 e,h csr15 4 fcoll fcpen flow_ control 17 0c8 0 e,h fdrpa cmd2 20 50 0 e,h bcr9 2 fdrpa fixp flow_ control 18 0c8 0 e,h fl_addr flash_ addr 23:0 198 0 h fl_data flash_data 7:0 19c 0 h bcr30 7:0 ebdata[7:0] fmdc ctrl2 9:8 70 0 e,h bcr32 13:12 fmdc bit name register bit num offset (hex) default value reset type alternate register bit num bit name 8/01/00 am79c976 257 preliminary force_fd cmd3 12 54 0 e,h bcr9 0 fden force_ls cmd3 11 54 0 e,h force_fs ctrl2 18:16 70 0 e,h fpa flow_ control 20 0c8 0 e,h full_duplex stat0 6 30 0 h ifs1 ifs1 7:0 18c 3ch e,h csr125 7:0 ifs1 init_mib cmd3 25 54 0 e,h inloop cmd2 4 50 0 e,h intlevel cmd3 13 54 0 e,h bcr2 7 intlevel intr int0 31 38 0 h csr0 7 intr intren cmd0 1 48 0 e,h ipg ipg 7:0 18d 60h e,h csr125 15:8 ipg jumbo cmd3 21 54 0 e,h laainc flash_ addr 31 198 0 h bcr29 14 laainc ladrf ladrf 63:48 168 0 h csr11 15:0 ladrf3 ladrf ladrf 47:32 168 0 h csr10 15:0 ladrf2 ladrf ladrf 31:16 168 0 h csr9 15:0 ladrf1 ladrf ladrf 15:0 168 0 h csr8 15:0 ladrf0 lappen cmd2 2 50 0 e,h csr3 5 lappen lc_det stat0 10 30 0 p csr116 9 lcdet lcint int0 27 38 0 h lcinten inten0 27 40 0 e,h lcmode_ee cmd3 5 54 0 e,h csr116 8 lcmode lcmode_sw cmd7 0 64 0 p led0 led0 15:0 0e0 00c0h e,h bcr4 15:0 led0 led1 led1 15:0 0e2 0094h e,h bcr5 15:0 led1 led2 led2 15:0 0e4 1080h e,h bcr6 15:0 led2 led3 led3 15:0 0e6 0081h e,h bcr7 15:0 led3 ledcnttst test0 5 1a8 0 e,h ledpe cmd2 29 50 0 e,h bcr2 12 ledpe l i n k _ s tat s tat 0 5 3 0 0 h ltinten cmd2 9 50 0 e,h csr5 14 ltinten max_delay delayed_ int 10:0 0c0 0 e,h max_lat_a max_lat 7:0 1b1 18h e,h bcr22 15:8 max_lat bit name register bit num offset (hex) default value reset type alternate register bit num bit name 258 am79c976 8/01/00 preliminary mcciint int0 18 38 0 h csr7 3 mcciint mcciinten inten0 18 40 0 e,h csr7 2 mcciinte mccint int0 17 38 0 h csr7 5 mccint mccinten inten0 17 40 0 e,h csr7 4 mccinte mfsm_reset test0 10 1a8 0 e,h miipd stat0 3 30 0 h bcr32 14 miipd miipdtint int0 19 38 0 h csr7 1 miipdtint miipdtinten inten0 19 40 0 e,h min_gnt_a min_gnt 7:0 1b0 18h e,h bcr22 7:0 min_gnt mp_det stat0 11 30 0 p csr116 5 mpmat mpen_ee cmd3 6 54 0 e,h mpen_sw cmd7 1 64 0 p mpint int0 13 38 0 h csr5 4 mpint mpinten inten0 13 40 0 e,h csr5 3 mpinte mppen_ee cmd3 8 54 0 e,h csr116 4 mppen mppen_sw cmd7 2 64 0 p mpplba cmd3 9 54 0 e,h csr5 5 mpplba mreint int0 16 38 0 h csr7 9 mreint mreinten inten0 16 40 0 e,h csr7 8 mreinte nouflo cmd2 30 50 0 e,h bcr18 11 nouflo npa flow_ control 19 0c8 0 e,h padr padr 47:32 160 0 h csr14 15:0 padr2 padr padr 31:16 160 0 h csr13 15:0 padr1 padr padr 15:0 160 0 h csr12 15:0 padr0 pause_cnt pause_cnt 15:0 0de 0 h pause_len flow_ control 15:0 0c8 0 e,h pause_pend stat0 14 30 0 h pausing stat0 13 30 0 h pcidata0 pcidata0 9:0 1bc 0 e,h bcr37 9:0 pcidata0 pcidata1 pcidata1 9:0 1be 0 e,h bcr38 9:0 pcidata1 pcidata2 pcidata2 9:0 1c0 0 e,h bcr39 9:0 pcidata2 pcidata3 pcidata3 9:0 1c2 0 e,h bcr40 9:0 pcidata3 pcidata4 pcidata4 9:0 1c4 0 e,h bcr41 9:0 pcidata4 pcidata5 pcidata5 9:0 1c6 0 e,h bcr42 9:0 pcidata5 bit name register bit num offset (hex) default value reset type alternate register bit num bit name 8/01/00 am79c976 259 preliminary pcidata6 pcidata6 9:0 1c8 0 e,h bcr43 9:0 pcidata6 pcidata7 pcidata7 9:0 1ca 0 e,h bcr44 9:0 pcidata7 phy_addr phy_ access 25:21 0d0 0 h phy_blk_rd_ cmd phy_ access 29 0d0 0 h phy_cmd_ done phy_ access 31 0d0 0 h phy_data phy_ access 15:0 0d0 0 h phy_nblk_ rd_cmd phy_ access 28 0d0 0 h phy_pre_ sup phy_ access 27 0d0 0 h phy_reg_ addr phy_ access 20:16 0d0 0 h rst_pol cmd3 0 54 0 e,h csr116 0 rst_pol phy_wr_ cmd phy_ access 30 0d0 0 h pmat_det stat0 12 30 0 p csr116 7 pmat pmat_mode cmd7 3 64 0 p bcr45 7 pmat_mode pmc pmc 15:0 1b8 c802h e,h bcr36 15:0 pmc pme_en_ovr cmd3 4 54 0 e,h csr116 10 pme_en_ovr pmr_addr pmat0 6:0 190 0 h bcr45 6:0 pmr_addr pmr_b0 pmat0 15:8 190 0 h bcr45 15:8 pmr_b0 pmr_b1 pmat0 23:16 190 0 h bcr46 7:0 pmr_b1 pmr_b2 pmat0 31:24 190 0 h bcr46 15:8 pmr_b2 pmr_b3 pmat1 7:0 194 0 h bcr47 7:0 pmr_b3 pmr_b4 pmat1 15:8 194 0 h bcr47 15:8 pmr_b4 pread eeprom_ acc 14 17c 0 h bcr19 14 pread prefetch_ dis cmd3 30 54 0 e,h prom cmd2 16 50 0 e,h csr15 15 prom pvalid eeprom_ acc 15 17c 0 h bcr19 15 pvalid rcv_ protect rcv_ protect 15:0 0dc 64 h rcv_ring_ len rcv_ring_ len 15:0 150 0 h csr76 15:0 rcvrl rcvalgn cmd2 14 50 0 e,h csr122 0 rcvalgn bit name register bit num offset (hex) default value reset type alternate register bit num bit name 260 am79c976 8/01/00 preliminary rcvfw ctrl1 1:0 6c 1 e,h csr80 13:12 rcvfw[1:0] rdmd cmd0 12 48 0 e,h csr7 13 rdmd rst_phy cmd3 26 54 0 e,h rex_rtry cmd3 18 54 0 e,h rex_uflo cmd3 17 54 0 e,h rint int0 0 38 0 h,r csr0 10 rint rinten inten0 0 40 0 e,h csr3 10 rintm rombase[0] rom_cfg 0 18e 0 h rombase [23:11] rom_cfg 15:3 18e 0 h romtmg ctrl0 11:8 68 9 e,h bcr18 15:12 romtmg rpa cmd2 19 50 0 e,h csr124 3 rpa rtry_lcol cmd3 16 54 0 e,h rtytst_ bump test0 4 1a8 0 e,h csr126 14 rtrytst_a rtytst_out test0 3 1a8 0 e,h csr126 11 rtrytst_d rtytst_ rangen test0 2 1a8 0 e,h csr126 12 rtrytst_c rtytst_slot test0 1 1a8 0 e,h csr126 13 rtrytst_b run cmd0 0 48 0 e,h running stat0 0 30 0 h rwu_driver cmd3 3 54 0 e,h csr116 3 rwu_driver rwu_gate cmd3 2 54 0 e,h csr116 2 rwu_gate rwu_pol cmd3 1 54 0 e,h csr116 1 rwu_pol rx_fast_ spnd cmd0 5 48 0 e,h rx_spnd cmd0 3 48 0 e,h rx_ suspended stat0 2 30 0 h rxfrtgen cmd3 10 54 0 e,h serrlevel test0 0 1a8 0 e,h csr124 10 serrlevel sid sid 15:0 1b4 0 e,h bcr24 15:0 sid sint int0 12 38 0 h csr5 11 sint sinten inten0 12 40 0 e,h csr5 10 sinte slotmod ctrl1 25:24 6c 0 e,h speed stat0 9:7 30 0 h spndint int0 14 38 0 h spndinten inten0 14 40 0 e,h bit name register bit num offset (hex) default value reset type alternate register bit num bit name 8/01/00 am79c976 261 preliminary sram_bnd sram_bnd 15:0 17a 0 e,h bcr26 7:0 sram_bnd sram_size sram_size 15:0 178 0 e,h bcr25 7:0 sram_size sram_type ctrl0 17:16 68 ? e,h stint int0 4 38 0 h csr7 11 stint stinten inten0 4 40 0 e,h csr7 10 stinte stval stval 15:0 0d8 ffffh h bcr31 15:0 stval svid svid 15:0 1b6 0 e,h bcr23 15:0 svid swstyle ctrl3 7:0 74 0 h csr58 7:0 swstyle tdmd cmd0 8 48 0 e,h csr0 3 tdmd tint int0 8 38 0 h,r csr0 9 tint tinten inten0 8 40 0 e,h csr3 9 tintm tsel test0 11 1a8 0 e,h bcr33 14 tsel tx_fast_ spnd cmd0 4 48 0 e,h tx_spnd cmd0 2 48 0 e,h tx_ suspended stat0 1 30 0 h txdnint int0 6 38 0 h,r txdninten inten0 6 40 0 e,h txdpoll cmd2 0 50 0 e,h csr4 12 txdpoll txstrtint int0 5 38 0 h,r csr4 3 txstrt txstrtinten inten0 5 40 0 e,h csr4 2 txstrtm uint int0 7 38 0 h csr4 6 uint uintcmd cmd0 6 48 0 e,h csr4 7 uintcmd vid vid 15:0 1b2 1022h e,h bcr35 15:0 vid vlonly cmd3 19 54 0 e,h vsize cmd3 20 54 0 e,h xmt_ring_ len xmt_ring_ len 15:0 140 0 h csr78 15:0 xmtrl xmtfw ctrl1 9:8 6c 0 e,h csr80 9:8 xmtfw[1:0] xmtpolltime xmtpoll time 15:0 188 0 e,h csr47 15:0 txpollint xmtsp ctrl1 17:16 6c 1 e,h csr80 11:10 xmtsp[1:0] xphyane ctrl2 5 70 0 e,h bcr32 5 xphyane xphyfd ctrl2 4 70 0 e,h bcr32 4 xphyfd xphyrst ctrl2 6 70 0 e,h bcr32 6 xphyrst xphysp ctrl2 3 70 0 e,h bcr32 3 xphysp bit name register bit num offset (hex) default value reset type alternate register bit num bit name 262 am79c976 8/01/00 preliminary register programming summary programmable registers 5 register contents csr0 status and control bits: (default = 0004) 8000 -- 4000 -- 2000 -- 1000 -- 0800 -- 0400 rint 0200 tint 0100 idon 0080 intr 0040 iena 0020 rxon 0010 txon 0008 tdmd 0004 stop 0002 strt 0001 init csr1 lower iadr csr2 upper iadr csr3 interrupt masks and deferral control: (default = 0600) 8000 -- 4000 -- 2000 -- 1000 -- 0800 0400 rintm 0200 tintm 0100 idonm 0080 -- 0040 0020 lappen 0010 dxmt2pd 0008 emba 0004 bswp 0002 -- 0001 -- csr4 interrupt masks, configuration and status bits: (default = 0004) 8000 -- 4000 -- 2000 -- 1000 txdpoll 0800 apad_xmt 0400 astrp_rcv 0200 0100 0080 uintcmd 0040 uint 0020 0010 0008 txstrt 0004 txstrtm 0002 -- 0001 -- csr5 extended interrupt masks, configuration and status bits: (default = 0xxx) 8000 4000 ltinten 2000 txdnint 1000 txdninten 0800 sint 0400 sinte 0200 -- 0100 -- 0080 0040 0020 mpplba 0010 mpint 0008 mpinte 0004 mpen 0002 mpmode 0001 spnd csr7 extended interrupt masks, configuration and status bits: (default = 0000) 8000 fastspnde 4000 2000 rdmd 1000 chdpoll 0800 stint 0400 stinte 0200 mreint 0100 mreinte 0080 mapint 0040 mapinte 0020 mccint 0010 mccinte 0008 mcciint 0004 mcciinte 0002 miipdtint 0001 miipdtnte csr8 - csr11 logical address filter csr12 - csr14 physical address register csr15 mode: (default = 0) 8000 prom 4000 drcvbc 2000 drcvpa 1000 -- 0800 -- 0400 -- 0200 -- 0100 -- 0080 -- 0040 0020 drty 0010 fcoll 0008 dxmtfcs 0004 loop 0002 dtx 0001 drx csr47 txpollint: transmit polling interval csr49 rxpollint: chain polling interval csr58 software style (mapped to bcr20) bits [7:0] = swstyle, software style register. 8/01/00 am79c976 263 preliminary 8000-- 4000-- 2000-- 1000-- 0800 -- 0400 -- 0200 -- 0100 ssize32 0080 swstyle 0040 swstyle 0020 swstyle 0010 swstyle 0008 swstyle 0004 swstyle 0002 swstyle 0001 swstyle csr76 rcvrl: rcv descriptor ring length csr78 xmtrl: xmt descriptor ring length csr80 fifo threshold and dma burst control (default = 1400) 8000 reserved 4000 reserved bits [13:12] = rcvfw, receive fifo watermark 0000 request dma when 48 bytes are present 1000 request dma when 64 bytes are present 2000 request dma when 128 bytes are present 3000 reserved bits [11:10] = xmtsp, transmit start point 0000 start transmission after 16 bytes have been written 0400 start transmission after 64 bytes have been written 0800 start transmission after 128 bytes have been written 0c00 start transmission after the full packet has been written bits [9:8] = xmtfw, transmit fifo watermark 0000 start dma when 16 write cycles can be made 0100 start dma when 64 write cycles can be made 0200 start dma when 128 write cycles can be made 0300 start dma when 256 write cycles can be made bits [7:0] = reserved csr88~89 chip id (contents = v2628003; v = version number) csr116 onnow power mode register 8000 -- 4000 -- 2000 -- 1000 -- 0800 -- 0400 pm_en_ovr 0200 lcdet 0100 lcmode 0080 pmat 0040 empplba 0020 mpmat 0010 mppen 0008 rwu_driver 0004 rwu_gate 0002 rwu_pol 0001 rst_pol csr122 advanced feature control 8000 -- 4000 -- 2000 -- 1000 -- 0800 -- 0400 -- 0200 -- 0100 -- 0080 -- 0040 -- 0020 -- 0010 -- 0008 -- 0004 -- 0002 -- 0001 rcvalgn csr124 bmu test register (default = 0000) 8000 -- 4000 -- 2000 -- 1000 -- 0800 -- 0400 -- 0200 -- 0100 -- 0080 -- 0040 -- 0020 -- 0010 -- 0008 rpa 0004 -- 0002 -- 0001 -- csr125 mac enhanced configuration control (default = 603c bits [15:8] = ipg, interpacket gap (default=60xx, 96 bit times) bits [8:0] = ifs1, interframe space part 1 (default=xx3c, 60 bit times) register contents 264 am79c976 8/01/00 preliminary 5 rap addr register contents 2 mc miscellaneous configuration bits: (default = 0) 8000 -- 4000 -- 2000 -- 1000 ledpe 0800 -- 0400 -- 0200 -- 0100 apromwe 0080 intlevel 0040 -- 0020 -- 0010 -- 0008 -- 0004 -- 0002 -- 0001 -- 4 led0 programs the function and width of the led0 signal. (default = 00c0) 8000 ledout 4000 ledpol 2000 leddis 1000 100e 0800 -- 0400 -- 0200 mpse 0100 fdlse 0080 pse 0040 lnkse 0020 rcvme 0010 xmte 0008 -- 0004 rcve 0002 sfbde 0001 cole 5 led1 programs the function and width of the led1 signal. (default = 0094) 8000 ledout 4000 ledpol 2000 leddis 1000 100e 0800 -- 0400 -- 0200 mpse 0100 fdlse 0080 pse 0040 lnkse 0020 rcvme 0010 xmte 0008 -- 0004 rcve 0002 sfbde 0001 cole 6 led2 programs the function and width of the led2 signal. (default = 1080) 8000 ledout 4000 ledpol 2000 leddis 1000 100e 0800 -- 0400 -- 0200 mpse 0100 fdlse 0080 pse 0040 lnkse 0020 rcvme 0010 xmte 0008 -- 0004 rcve 0002 sfbde 0001 cole 7 led3 programs the function and width of the led3 signal. (default = 0081) 8000 ledout 4000 ledpol 2000 leddis 1000 100e 0800 -- 0400 -- 0200 mpse 0100 fdlse 0080 pse 0040 lnkse 0020 rcvme 0010 xmte 0008 -- 0004 rcve 0002 sfbde 0001 cole 9 fdc full-duplex control. (default= 0004) 8000 -- 4000 -- 2000 -- 1000 -- 0800 -- 0400 -- 0200 -- 0100 -- 0080 -- 0040 -- 0020 -- 0010 -- 0008 -- 0004 fdrpad 0002 -- 0001 fden 18 bsbc burst size and bus control (default = 9000) 8000 romtmg3 4000 romtmg2 2000 romtmg1 1000 romtmg0 0800 nouflo 0400 -- 0200 0100 0080 dwio 0040 0020 0010 -- 0008 -- 0004 -- 0002 -- 0001 -- 19 eecas eeprom control and status (default = 0000) 8000 pvalid 4000 pread 2000 eedet 1000 -- 0800 -- 0400 -- 0200 -- 0100 -- 0080 -- 0040 -- 0020 -- 0010 een 0008 -- 0004 ecs 0002 esk 0001 edi/edo 20 swstyle software style (default = 0000, maps to csr 58) 22 pcilat pci latency (default = 1818) bits [15:8] = max_lat bits [7:0] = min_gnt 25 sram_size sram size (default = 0000) 8/01/00 am79c976 265 preliminary bits [15:0] = sram_size 26 sram_bnd sram boundary (default = 0000) bits [15:0] = sram_bnd 28 epaddrl expansion port address lower 29 epaddru expansion port address upper 8000 4000 lainc 2000 -- 1000 -- 0800 -- 0400 -- 0200 -- 0100 -- 0080 epaddru7 0040 epaddru6 0020 epaddru5 0010 epaddru4 0008 epaddru3 0004 epaddru2 0002 epaddru1 0001 epaddru0 30 ebdata expansion bus data port 31 stval software timer interrupt value (default = ffff) 32 miicas mii status and control (default = 0400) 8000 antst 4000 miipd 2000 fmdc1 1000 fmdc0 0800 apep 0400 apdw2 0200 apdw1 0100 apdw0 0080 dispm 0040 xphyrst 0020 xphyane 0010 xphyfd 0008 xphysp 0004 -- 0002 miiilp 0001 -- 33 miiaddr mii address bits [9:5] = phyad, physical layer device address bits [4:0] = regad, mii/auto-negotiation register address 34 miimdr mii data port 35 pci id pci vendor id register (default = 1022h) 36 pmc_a pci power management capabilities (default = c802) 37 data 0 pci data register zero alias register (default = 0000) 38 data 1 pci data register one alias register (default = 0000) 39 data 2 pci data register two alias register (default = 0000) 40 data 3 pci data register three alias register (default = 0000) 41 data 4 pci data register four alias register (default = 0000) 42 data 5 pci data register five alias register (default = 0000) 43 data 6 pci data register six alias register (default = 0000) 44 data 7 pci data register seven alias register (default = 0000) 45 pmr 1 onnow pattern matching register 1 46 pmr 2 onnow pattern matching register 2 47 pmr 3 onnow pattern matching register 3 rap addr register contents 266 am79c976 8/01/00 preliminary absolute maximum ratings storage temperature . . . . . . . . . . . . . -65 o c to +150 o c ambient temperature. . . . . . . . . . . . . . -65 o c to +70 o c supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . with respect to v ssb , v ss . . . . . . . . . ? 0.3 v to 3.63 v stresses above those listed under absolute maximum ratings may cause permanent device failure. function- ality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability . operating ranges commercial (c) devices temperature (t) . . . . . . . . . . . . . . . . . . . 0 o c to +70 o c supply voltages (vdd, avdd) . . . . . . . . +3.3 v 10% all inputs within the range: . . . v ss ? 0.5 v to 5.5 v operating ranges define those limits between which the functionality of the device is guaranteed. 8/01/00 am79c976 267 preliminary dc characteristics over commercial operating ranges unless specified otherwise parameter symbol parameter description test conditions min max units digital i/o (non-pci pins) v ih input high voltage 2.0 v v il input low voltage 0.8 v v ol output low voltage i ol1 = 6 ma i ol2 = 12 ma (note 1) 0.4 v v oh output high voltage (note 2) i oh1 = -4 ma 2.4 v i oz output leakage current (note 3) 0 v 8/01/00 am79c976 269 preliminary switching characteristics: bus interface note: 1. not tested; parameter guaranteed by design characterization. parameter symbol parameter name test condition min max unit clock timing f clk clk frequency 0 33 mhz t cyc clk period @ 1.5 v for 5 v signaling @ 0.4 v dd for 3.3 v signaling 30 _ ns t high clk high time @ 2.0 v for 5 v signaling @ 0.4 v dd for 3.3 signaling 12 ns t low clk low time @ 0.8 v for 5 v signaling @ 0.3 v dd for 3.3 v signaling 12 ns t fall clk fall time over 2 v p-p for 5 v signaling over 0.4 v dd for 3.3 v signaling (note 1) 1 4 v/ns t rise clk rise time over 2 v p-p for 5 v signaling over 0.4 v dd for 3.3 v signaling (note 1) 1 4 v/ns output and float delay timing t val ad[31:00], c/be [3:0], par, frame , irdy , trdy , stop , devsel , perr , serr valid delay 2 11 ns t val (req ) req valid delay 2 12 ns t on ad[31:00], c/be [3:0], par, frame , irdy , trdy , stop , devsel active delay 2 ns t off ad[31:00], c/be [3:0], par, frame , irdy , trdy , stop , devsel float delay 28 ns setup and hold timing t su ad[31:00], c/be [3:0], par, frame , irdy , trdy , stop , devsel , idsel setup time 7 ns t h ad[31:00], c/be [3:0], par, frame , irdy , trdy , stop , devsel , idsel hold time 0 ns t su (gnt ) gnt setup time 10 ns t h (gnt ) gnt hold time 0 ns 270 am79c976 8/01/00 preliminary switching waveforms key to switching waveforms must be steady may change from h to l may change from l to h does not apply don ? t care, any change permitted will be steady will be changing from h to l will be changing from l to h changing, state unknown center line is high- impedance ? off ? state waveform inputs outputs ks000010-pal 8/01/00 am79c976 271 preliminary switching test circuits "1 ! - ' i oh i ol sense point v threshold c l = 50 pf 22929b50 272 am79c976 8/01/00 preliminary switching waveforms: system bus interface "2 8/01/00 am79c976 273 preliminary switching waveforms: system bus interface (continued) ) '= *$ ! ) ' -*$ ! clk t val(req) tx tx tx min max valid n valid n+1 req min max valid n valid n+1 t val ad[31:00] c/be[3:0], par, frame, irdy, trdy, stop, devsel, perr, serr 22929b54 clk tx tx tx ad[31:00], c/be[3:0], par, frame, irdy, trdy, stop, devsel, perr ad[31:00], c/be[3:0], par, frame, irdy, trdy, stop, devsel, perr valid n t off t on valid n 22929b55 274 am79c976 8/01/00 preliminary switching characteristics: eeprom interface 1 1. parameter value is given for automatic eeprom read operation. when eeprom port (bcr19) is used to access the eeprom, software is responsible for meeting eeprom timing requirements. )"%%0 #( ! parameter symbol parameter name test condition min max unit eeprom timing f eesk eesk frequency (note 1) 650 khz t high (eesk) eesk high time 780 ns t low (eesk) eesk low time 780 ns t val (eedi) eedi valid output delay from eesk (note 1) -15 15 ns t val (eecs) eecs valid output delay from eesk (note 1) -15 15 ns t low (eecs) eecs low time 1550 ns t su (eedo) eedo setup time to eesk (note 1) 50 ns t h (eedo) eedo hold time from eesk (note 1) 0 ns eecs eesk eedi eedo 01 1 0 a5 a4 a3 a2 a1 a0 d15 d14 d13 d2 d1 d0 22929b56 8/01/00 am79c976 275 preliminary switching characteristics: eeprom interface (continued) ))! (0%*%%0 # ! eesk eedo stable eedi eecs t high (eesk) t low (eesk) t low (eecs) t su (eedo) t h (eedo) t val (eedi,eecs) 22929b57 276 am79c976 8/01/00 preliminary switching characteristics: jtag timing ),f 9:%%%"2; e !)= parameter symbol parameter name test condition min max unit jtag (ieee 1149.1) test signal timing t j1 tck frequency 10 mhz t j2 tck period 100 ns t j3 tck high time @ 2.0 v 45 ns t j4 tck low time @ 0.8 v 45 ns t j5 tck rise time 4 ns t j6 tck fall time 4 ns t j7 tdi, tms setup time 8 ns t j8 tdi, tms hold time 10 ns t j9 tdo valid delay 3 30 ns t j10 tdo float delay 50 ns t j11 all outputs (non-test) valid delay 3 25 ns t j12 all outputs (non-test) float delay 36 ns t j13 all inputs (non-test)) setup time 8 ns t j14 all inputs (non-test) hold time 7 ns tck t j3 t j6 t j2 t j5 t j4 2.0 v 1.5 v 0.8 v 2.0 v 1.5 v 0.8 v 22929b58 8/01/00 am79c976 277 preliminary switching characteristics: jtag timing (continued) )/f 9:%%%"2; ! tck tdi, tms tdo t j8 output signals t j2 t j7 t j9 t j11 t j14 input signals t j12 t j13 t j10 22929b59 278 am79c976 8/01/00 preliminary switching characteristics: media independent interface notes: 1. mdio valid measured at the exposed mechanical media independent interface. 2. txclk and rxclk frequency and timing parameters are defined for the external physical layer transceiver as defined in the ieee 802.3u standard. they are not replicated here. 3. t msu and t mh are input requirements when mdio is driven by an external phy device. 4. t mval is the output delay when mdio is driven by the am79c976 device. parameter symbol parameter name test condition min max unit transmit timing t tval tx_en, tx_er, txd valid from tx_clk measured from v ilmax = 0.8 v or measured from v ihmin = 2.0v 0 25 ns receive timing t rsu rx_dv, rx_er, rxd setup to rx_clk measured from v ilmax = 0.8 v or measured from v ihmin = 2.0v 10 ns t rh rx_dv, rx_er, rxd hold from rx_clk measured from v ilmax = 0.8 v or measured from v ihmin = 2.0v 10 ns management cycle timing t mhigh mdc pulse width high time c load = 390 pf 160 ns t mlow mdc pulse width low time c load = 390 pf 160 ns t mcyc mdc cycle period c load = 390 pf 400 ns t msu mdio setup to mdc c load = 470 pf, measured from v ilmax = 0.8 v or measured from v ihmin = 2.0v (note 1, 3) 25 ns t mh mdio hold from mdc c load = 470 pf, measured from v ilmax = 0.8 v or measured from v ihmin = 2.0v (note 1, 3) 10 ns t mval mdio valid from mdc c load = 470 pf, measured from v ilmax = 0.8 v or measured from v ihmin = 2.0v, (note 1, 4) t mcyc - t msu ns 8/01/00 am79c976 279 preliminary switching characteristics: media independent interface (continued) )1 ! ! )2( ! ,4#* ! tx_clk t tval txd[3:0], tx_en, tx_er vihmin vilmax vihmin vilmax 22929b60 rx_clk t rh rxd[3:0], rx_er, rx_dv t rsu vihmin vilmax vihmin vilmax 22929b61 mdc 0.8 v 1.5 v 2.0 v t mhigh t mcyc t mlow 0.8 v 2.4 1.5 v 2.0 v 0.4 22929b62 280 am79c976 8/01/00 preliminary switching characteristics: media independent interface (concluded) ,# !*'. ! , # !* '= *$ ! mdc t mh mdio t msu vihmin vilmax vihmin vilmax 22929b63 mdc t mval vihmin vilmax vihmin vilmax mdio 22929b64 8/01/00 am79c976 281 preliminary switching characteristics: external address detection interface note: 1. may need to delay rx_clk to capture start frame byte delimiter (sfbd) at 100 mbps operation. , g( ! -%&0.>#h )#.6 parameter symbol parameter name test condition min max unit external address detection interface: external phy - mii @ 25 mhz t ead7 sfbd change from rx_clk 0 20 (note 1) ns t ead8 ear deassertion to rx_dv (first rising edge) 40 ns t ead9 ear assertion after sfd event (frame rejection) 0 5,080 ns t ead10 ear assertion width 50 ns external address detection interface: external phy - mii @ 2.5 mhz t ead11 ear deassertion to rx_dv (first rising edge) 400 ns t ead12 ear assertion after sfd event (frame rejection) 0 50,800 ns t ead13 ear assertion width 500 ns receive frame tag timing with media independent interface t ead14 rxfrtge assertion from sfbd (first rising edge) 0 ns t ead15 rxfrtge, rxfrtgd setup to rx_clk 10 ns t ead16 rxfrtge, rxfrtgd hold from rx_clk 10 ns t ead17 rxfrtge deassertion to rx_dv rx_clk @25 mhz rx_clk @2.5 mhz 40 400 ns ns rx_clk rxd[3:0] rx_dv ear preamble sf/bd sfd da da da t ead8 t ead7 t ead9 t ead10 22929b65 sfbd 282 am79c976 8/01/00 preliminary switching characteristics: external address detection interface (concluded) ,"g( ! -%&0.>#h )#.6 rx_clk rxd[3:0] rx_dv ear preamble sf/bd sfd da da da t ead13 t ead11 t ead12 22929b66 8/01/00 am79c976 283 preliminary switching waveforms: receive frame tag ,)( ! ! 8 +# '( rx_clk rxd[3:0] rx_dv ear preamble sf/bd sfd da da da rxfrtge t ead14 rxfrtgd t ead15 t ead16 t ead17 22929b67 284 am79c976 8/01/00 preliminary switching waveforms: external memory interface ,,%&#!$ ! parameter symbol parameter name test condition min max unit ssram timing t erclk erclk period @ 1.5 v 11.111 ns t high erclk high time @ 1.5 v 4.5 ns t low erclk low time @ 1.5 v 4.5 ns t o_su ssram output signals set up time with respect to rising edge of erclk @ 1.5 v 2.5 ns t erd_su ssram erd input signals set up time @ 1.5 v 5 ns t erd_h ssram erd input signals hold time @ 1.5 v 1 ns erclk 0.8 v 0.8 v 1.5 v 1.5 v 2.0 v 2.0 v t low t high t erclk 2.4 v 0.4v output signals: era, eradsp, eradv, eroe, erce, erwe, erd input signals: erd t erd_su t erd_h t o_su 22929b68 8/01/00 am79c976 285 preliminary physical dimensions* pqfp208 0 (i0(7 !!! 2 !"# $"% ! " # & notes: 1. all dimensions and tolerances conform to asme y14.5m-1992 2. controlling dimensions: millimeters 3. these dimensions do not include mold protrusion. allowable protrusion is 0.25 mm per side. these dimensions include mold mismatch and are determined at datum plane -a-. 4. this dimension does not include dambar protrusion. 5. datum plane -a- is located at the mold parting line and is coincident with the bottom of the lead where the lead exits the pl astic body. 6. these dimensions are measured from both innermost and outermost points. 7. deviation from lead-tip true position shall be within 0.04 mm. 8. lead co-planarity shall be within 0.076 mm. co-planarity is measured per specification 06.500. 9. half span (center of package to lead tip) shall be within 0.0085 inches. 3.95 max 3.95 max 0.25 min 3.20 3.60 30.40 30.80 27.90 28.10 3 25.50 ref 0.50 bsc 25.50 ref 27.90 28.10 30.40 30.80 3 0.17 0.27 0.13 0.20 0.17 0.27 0.08 0.08 0.50 0.75 pqr 208 2 208 52 156 104 pin pin pin pin k.koller rev. ai; 5/18/99 appendix a a - 1 look-ahead packet processing (lapp) concept appendix a: look-ahead packet processing introduction a driver for the am79c976 controller would normally require that the cpu copy receive frame data from the controllers buffer space to the applications buffer space after the entire frame has been received by the control- ler. for applications that use a ping-pong windowing style, the traffic on the network will be halted until the current frame has been completely processed by the entire application stack. this means that the time be- tween last byte of a receive frame arriving at the client ? s ethernet controller and the client ? s transmission of the first byte of the next outgoing frame will be separated by: 1. the time that it takes the client ? s cpu interrupt pro- cedure to pass software control from the current task to the driver, 2. plus the time that it takes the client driver to pass the header data to the application and request an application buffer, 3. plus the time that it takes the application to gener- ate the buffer pointer and then return the buffer pointer to the driver, 4. plus the time that it takes the client driver to transfer all of the frame data from the controller ? s buffer space into the application ? s buffer space and then call the application again to process the complete frame, 5. plus the time that it takes the application to process the frame and generate the next outgoing frame, 6. plus the time that it takes the client driver to set up the descriptor for the controller and then write a tdmd bit to csr0. the sum of these times can often be about the same as the time taken to actually transmit the frames on the wire, thereby, yielding a network utilization rate of less than 50 percent. an important thing to note is that the am79c976 con- troller ? s data transfers to its buffer space are such that the system bus is needed by the am79c976 controller for approximately 4 percent of the time. this leaves 96 percent of the system bus bandwidth for the cpu to perform some of the interframe operations in advance of the completion of network receive activity, if possible. the question then becomes: how much of the tasks that need to be performed between reception of a frame and transmission of the next frame can be per- formed before the reception of the frame actually ends at the network, and how can the cpu be instructed to perform these tasks during the network reception time? the answer depends upon exactly what is happening in the driver and application code, but the steps that can be performed at the same time as the receive data are arriving include as much as the first three steps and part of the fourth step shown in the sequence above. by performing these steps before the entire frame has arrived, the frame throughput can be substantially in- creased. a good increase in performance can be expected when the first three steps are performed before the end of the network receive operation. a much more significant performance increase could be realized if the am79c976 controller could place the frame data di- rectly into the application ? s buffer space; (i.e., eliminate the need for step 4.) in order to make this work, it is necessary that the application buffer pointer be deter- mined before the frame has completely arrived, then the buffer pointer in the next descriptor for the receive frame would need to be modified in order to direct the am79c976 controller to write directly to the application buffer. more details on this operation will be given later. an alternative modification to the existing system can gain a smaller but still significant improvement in per- formance. this alternative leaves step 4 unchanged in that the cpu is still required to perform the copy oper- ation, but it allows a large portion of the copy operation to be done before the frame has been completely re- ceived by the controller, i.e., the cpu can perform the copy operation of the receive data from the am79c976 controller ? s buffer space into the application buffer space before the frame data has completely arrived from the network. this allows the copy operation of step 4 to be performed concurrently with the arrival of network data, rather than sequentially, following the end of network receive activity. 8/01/00 am79c976 a-2 preliminary outline of lapp flow this section gives a suggested outline for a driver that utilizes the lapp feature of the am79c976 controller. note: the labels in the following text are used as ref- erences in the timeline diagram that follows (figure a-1). ' the driver should set up descriptors in groups of three, with the own and stp bits of each set of three de- scriptors to read as follows: 11b, 10b, 00b. an option bit (lappen) exists in csr3, bit position 5; the software should set this bit. when set, the lappen bit directs the am79c976 controller to generate an in- terrupt when stp has been written to a receive de- scriptor by the am79c976 controller. 8 the am79c976 controller polls the current receive de- scriptor at some point in time before a message arrives. the am79c976 controller determines that this receive buffer is owned by the am79c976 controller and it stores the descriptor information to be used when a message does arrive. n0 frame preamble appears on the wire, followed by sfd and destination address. n1 the 64th byte of frame data arrives from the wire. this causes the am79c976 controller to begin frame data dma operations to the first buffer. c0 when the 64th byte of the message arrives, the am79c976 controller performs a looka- head operation to the next receive descriptor. this descriptor should be owned by the am79c976 controller. c1 the am79c976 controller intermittently re- quests the bus to transfer frame data to the first buffer as it arrives on the wire. s1 the driver remains idle. c2 when the am79c976 controller has com- pletely filled the first buffer, it writes status to the first descriptor. c3 when the first descriptor for the frame has been written, changing ownership from the am79c976 controller to the cpu, the am79c976 controller will generate an srp in- terrupt. (this interrupt appears as a rint interrupt in csr0). s1 the srp interrupt causes the cpu to switch tasks to allow the am79c976 control- ler ? s driver to run. c4 during the cpu interrupt-generated task switching, the am79c976 controller is per- forming a lookahead operation to the third de- scriptor. at this point in time, the third descriptor is owned by the cpu. note: even though the third buffer is not owned by the am79c976 controller, existing amd ethernet control- lers will continue to perform data dma into the buffer space that the controller already owns (i.e., buffer num- ber 2). the controller does not know if buffer space in buffer number 2 will be sufficient or not for this frame, but it has no way to tell except by trying to move the en- tire message into that space. only when the message does not fit will it signal a buffer error condition--there is no need to panic at this point that it discovers that it does not yet own descriptor number 3. s2 the first task of the drivers interrupt service route is to collect the header information from the am79c976 controller ? s first buffer and pass it to the application. s3 the application will return an application buffer pointer to the driver. the driver will add an off- set to the application data buffer pointer, since the am79c976 controller will be placing the first portion of the message into the first and second buffers. (the modified application data buffer pointer will only be directly used by the am79c976 controller when it reaches the third buffer.) the driver will place the modified data buffer pointer into the final descriptor of the group (#3) and will grant ownership of this de- scriptor to the am79c976 controller. c5 interleaved with s2, s3, and s4 driver activity, the am79c976 controller will write frame data to buffer number 2. s4 the driver will next proceed to copy the con- tents of the am79c976 controller ? s first buffer to the beginning of the application space. this copy will be to the exact (unmodified) buffer pointer that was passed by the application. s5 after copying all of the data from the first buffer into the beginning of the application data buffer, the driver will begin to poll the owner- ship bit of the second descriptor. the driver is waiting for the am79c976 controller to finish filling the second buffer. c6 at this point, knowing that it had not previously owned the third descriptor and knowing that the current message has not ended (there is more data in the fifo), the am79c976 con- troller will make a last ditch lookahead to the final (third) descriptor. this time the ownership will be true (i.e., the descriptor belongs to the controller), because the driver wrote the appli- a-3 am79c976 8/01/00 preliminary cation pointer into this descriptor and then changed the ownership to give the descriptor to the am79c976 controller back at s3. note that if steps s1, s2, and s3 have not com- pleted at this time, a buff error will result. c7 after filling the second buffer and performing the last chance lookahead to the next descrip- tor, the am79c976 controller will write the sta- tus and change the ownership bit of descriptor number 2. s6 after the ownership of descriptor number 2 has been changed by the am79c976 controller, the next driver poll of the second descriptor will show ownership granted to the cpu. the driver now copies the data from buffer number 2 into the middle section of the application buffer space. this operation is interleaved with the c7 and c8 operations. c8 the am79c976 controller will perform data dma to the last buffer, whose pointer is point- ing to application space. data entering the least buffer will not need the infamous double copy that is required by existing drivers, since it is being placed directly into the application buffer space. n2 the message on the wire ends. s7 when the driver completes the copy of buffer number 2 data to the application buffer space, it begins polling descriptor number 3. c9 when the am79c976 controller has finished all data dma operations, it writes status and changes ownership of descriptor number 3. s8 the driver sees that the ownership of descrip- tor number 3 has changed, and it calls the ap- plication to tell the application that a frame has arrived. s9 the application processes the received frame and generates the next tx frame, placing it into a tx buffer. s10 the driver sets up the tx descriptor for the am79c976 controller. 8/01/00 am79c976 a-4 preliminary -<00 ! buffer #3 buffer #2 buffer #1 ethernet wire activity: ethernet controller activity: software activity: s10: driver sets up tx descriptor. s9: application processes packet, generates tx packet. s8: driver calls application to tell application that packethas arrived. s7: driver polls descriptor of buffer #3. s6: driver copies data from buffer #2 to the application buffer. s5: driver polls descriptor #2. s4: driver copies data from buffer #1 to the application buffer. s3: driver writes modified application pointer to descriptor #3. s2: driver call to application to get application buffer pointer. s1: interrupt latency. s0: driver is idle. } n2:eom n0: packet preamble, sfd and destination address are arriving. { packet data arriving } } } c9: controller writes descriptor #3. c8: controller is performing intermittent bursts of dma to fill data buffer #3. c7: controller writes descriptor #2. c6: "last chance" lookahead to descriptor #3 (own). c5: controller is performing intermittent bursts of dma to fill data buffer #2 c3: srp interrupt is generated. c2: controller writes descriptor #1. c1: controller is performing intermittent bursts of dma to fill data buffer #1. c0: lookahead to descriptor #2. n1: 64th byte of packet data arrives. c4: lookahead to descriptor #3 (own). d-1 a-5 am79c976 8/01/00 preliminary lapp software requirements software needs to set up a receive ring with descriptors formed into groups of three. the first descriptor of each group should have own = 1 and stp = 1, the second descriptor of each group should have own = 1 and stp = 0. the third descriptor of each group should have own = 0 and stp = 0. the size of the first buffer (as indicated in the first descriptor) should be at least equal to the largest expected header size; however, for maximum efficiency of cpu utilization, the first buffer size should be larger than the header size. it should be equal to the expected number of message bytes, minus the time needed for interrupt latency and minus the ap- plication call latency, minus the time needed for the driver to write to the third descriptor, minus the time needed for the drive to copy data from buffer number 2 to the application buffer space. note that the time needed for the copies performed by the driver depends upon the sizes of the second and third buffers, and that the sizes of the second and third buffers need to be set according to the time needed for the data copy opera- tions. this means that an iterative self-adjusting mech- anism needs to be placed into the software to determine the correct buffer sizing for optimal opera- tion. fixed values for buffer sizes may be used; in such a case, the lapp method will still provide a significant performance increase, but the performance increase will not be maximized. figure a-2 illustrates this setup for a receive ring size of 9. - <00 9' lapp rules for parsing descriptors when using the lapp method, software must use a modified form of descriptor parsing as follows: software will examine own and stp to determine where an rcv frame begins. rcv frames will only begin in buffers that have own = 0 and stp = 1. software shall assume that a frame continues until it finds either enp = 1 or err = 1. software must discard all descriptors with own = 0 and stp = 0 and move to the next descriptor when searching for the beginning of a new frame; enp and err should be ignored by software during this search. software cannot change an stp value in the receive descriptor ring after the initial setup of the ring is complete, even if software has ownership of the stp descriptor #1 descriptor #2 descriptor #3 descriptor #4 descriptor #5 descriptor #6 descriptor #7 descriptor #8 descriptor #9 own = 1 stp = 1 size = a-(s1+s2+s3+s4+s6) own = 1 stp = 0 size = s1+s2+s3+s4 own = 0 stp = 0 size = s6 own = 1 stp = 1 size = a-(s1+s2+s3+s4+s6) own = 1 stp = 0 size = s1+s2+s3+s4 own = 0 stp = 0 size = s6 own = 1 stp = 1 size = a-(s1+s2+s3+s4+s6) own = 1 stp = 0 size = s1+s2+s3+s4 own = 0 stp = 0 size = s6 a = expected message size in bytes s1 = interrupt latency s2 = application call latency s3 = time needed for driver to write to third descriptor s4 = time needed for driver to copy data from buffer #1 to application buffer space s6 = time needed for driver to copy data from buffer #2 to application buffer space note that the times needed for tasks s1, s2, s3, s4, and s6 should be divided by 0.8 microseconds to yield an equivalent number of network byte times before subtracting these quantities from the expected message size a. d-2 8/01/00 am79c976 a-6 preliminary descriptor, unless the previous stp descriptor in the ring is also owned by the software. when lappen = 1, then hardware will use a modified form of descriptor parsing as follows: the controller will examine own and stp to deter- mine where to begin placing an rcv frame. a new rcv frame will only begin in a buffer that has own = 1 and stp =1. the controller will always obey the own bit for de- termining whether or not it may use the next buffer for a chain. the controller will always mark the end of a frame with either enp = 1 or err = 1. the controller will discard all descriptors with own = 1 and stp = 0 and move to the next descriptor when searching for a place to begin a new frame. it discards these descriptors by simply changing the ownership bit from own = 1 to own = 0. such a descriptor is unused for receive purposes by the controller, and the driver must recognize this. (the driver will recognize this if it follows the software rules.) the controller will ignore all descriptors with own = 0 and stp = 0 and move to the next descriptor when searching for a place to begin a new frame. in other words, the controller is allowed to skip entries in the ring that it does not own, but only when it is looking for a place to begin a new frame. some examples of lapp descriptor interaction choose an expected frame size of 1060 bytes. choose buffer sizes of 800, 200, and 200 bytes. example 1 : assume that a 1060 byte frame arrives correctly, and that the timing of the early interrupt and the software is smooth. the descriptors will have changed from: example 2 : assume that instead of the expected 1060 byte frame, a 900 byte frame arrives, either because there was an error in the network, or be- cause this is the last frame in a file transmission se- quence note: the am79c976 controller might write a zero to enp location in the third descriptor. here are the two possibilities: 1. if the controller finishes the data transfers into buffer number 2 after the driver writes the application modified buffer pointer into the third descriptor, then descriptor number before the frame arrives after the frame arrives comments (after frame arrival) own stp enp a own stp enp e 1 1 1 x 0 1 0 bytes 1-800 2 1 0 x 0 0 0 bytes 801-1000 3 0 0 x 0 0 1 bytes 1001-1060 4 1 1 x 1 1 x controller ? s current location 5 1 0 x 1 0 x not yet used 6 0 0 x 0 0 x not yet used etc. 1 1 x 1 1 x net yet used & b. enp or err descriptor number before the frame arrives after the frame arrives comments (after frame arrival) own stp enp a own stp enp e 1 1 1 x 0 1 0 bytes 1-800 2 1 0 x 0 0 0 bytes 801-1000 3 0 0 x 0 0 ? * discarded buffer 4 1 1 x 1 1 x controller ? s current location 5 1 0 x 1 0 x not yet used 6 0 0 x 0 0 x not yet used etc. 1 1 x 1 1 x net yet used & b. enp or err a-7 am79c976 8/01/00 preliminary the controller will write a zero to enp for this buffer and will write a zero to own and stp. 2. if the controller finishes the data transfers into buffer number 2 before the driver writes the applications modified buffer point into the third descriptor, then the controller will complete the frame in buffer num- ber 2 and then skip the then unowned third buffer. in this case, the am79c976 controller will not have had the opportunity to reset the enp bit in this descriptor, and it is possible that the software left this bit as enp = 1 from the last time through the ring. therefore, the software must treat the location as a don ? t care. the rule is, after finding enp = 1 (or err = 1) in descriptor number 2, the software must ignore enp bits until it finds the next stp = 1. example 3 : assume that instead of the expected 1060 byte frame, a 100 byte frame arrives, because there was an error in the network, or because this is the last frame in a file transmission sequence, or perhaps because it is an acknowledge frame. * same as note in example 2 above, except that in this case, it is very unlikely that the driver can respond to the interrupt and get the pointer from the application before the am79c976 controller has completed its poll of the next descriptors. this means that for almost all occurrences of this case, the am79c976 controller will not find the own bit set for this descriptor and, there- fore, the enp bit will almost always contain the old value, since the am79c976 controller will not have had an opportunity to modify it. **note that even though the am79c976 controller will write a zero to this enp location, the software should treat the location as a don ? t care, since after finding the enp = 1 in descriptor number 2, the software should ig- nore enp bits until it finds the next stp = 1. 6 for maximum performance, buffer sizes should be ad- justed depending upon the expected frame size and the values of the interrupt latency and application call latency. the best driver code will minimize the cpu uti- lization while also minimizing the latency from frame end on the network to the frame sent to application from driver (frame latency). these objectives are aimed at increasing throughput on the network while decreas- ing cpu utilization. note: the buffer sizes in the ring may be altered at any time that the cpu has ownership of the corresponding descriptor. the best choice for buffer sizes will maxi- mize the time that the driver is swapped out, while min- imizing the time from the last byte written by the am79c976 controller to the time that the data is passed from the driver to the application. in the dia- gram, this corresponds to maximizing s0, while mini- mizing the time between c9 and s8. (the timeline happens to show a minimal time from c9 to s8.) note: by increasing the size of buffer number 1, we in- crease the value of s0. however, when we increase the size of buffer number 1, we also increase the value of s4. if the size of buffer number 1 is too large, then the driver will not have enough time to perform tasks s2, s3, s4, s5, and s6. the result is that there will be delay from the execution of task c9 until the execution of task s8. a perfectly timed system will have the values for s5 and s7 at a minimum. an average increase in performance can be achieved, if the general guidelines of buffer sizes in figure 2 is fol- lowed. however, as was noted earlier, the correct sizing for buffers will depend upon the expected message size. there are two problems with relating expected message size with the correct buffer sizing: 1. message sizes cannot always be accurately pre- dicted, since a single application may expect differ- ent message sizes at different times. therefore, the buffer sizes chosen will not always maximize throughput. 2. within a single application, message sizes might be somewhat predictable, but when the same driver is to be shared with multiple applications, there may not be a common predictable message size. additional problems occur when trying to define the correct sizing because the correct size also depends descriptor number before the frame arrives after the frame arrives comments (after frame arrival) own stp enp a own stp enp e 1 1 1 x 0 1 0 bytes 1-800 2 1 0 x 0 0 0** discarded buffer 3 0 0 x 0 0 ? discarded buffer 4 1 1 x 1 1 x controller ? s current location 5 1 0 x 1 0 x not yet used 6 0 0 x 0 0 x not yet used etc. 1 1 x 1 1 x net yet used & b.enp or err 8/01/00 am79c976 a-8 preliminary upon the interrupt latency, which may vary from system to system, depending upon both the hardware and the software installed in each system. in order to deal with the unpredictable nature of the message size, the driver can implement a self-tuning mechanism that examines the amount of time spent in tasks s5 and s7. as such, while the driver is polling for each descriptor, it could count the number of poll oper- ations performed and then adjust the number 1 buffer size to a larger value, by adding ? t ? bytes to the buffer count, if the number of poll operations was greater than ? x. ? if fewer than ? x ? poll operations were needed for each of s5 and s7, then software should adjust the buffer size to a smaller value by subtracting ? y ? bytes from the buffer count. experiments with such a tuning mechanism must be performed to determine the best values for ? x ? and ? y. ? note: whenever the size of buffer number 1 is ad- justed, buffer sizes for buffer number 2 and buffer num- ber 3 should also be adjusted. in some systems, the typical mix of receive frames on a network for a client application consists mostly of large data frames, with very few small frames. in this case, for maximum efficiency of buffer sizing, when a frame arrives under a certain size limit, the driver should not adjust the buffer sizes in response to the short frame. <008? 8-'#+ an alternative to the above suggested flow is to use two interrupts, one at the start of the receive frame and the other at the end of the receive frame, instead of just looking for the srp interrupt as described above. this alternative attempts to reduce the amount of time that the software wastes while polling for descriptor own bits. this time would then be available for other cpu tasks. it also minimizes the amount of time the cpu needs for data copying. this savings can be applied to other cpu tasks. the time from the end of frame arrival on the wire to de- livery of the frame to the application is labeled as frame latency. for the one-interrupt method, frame latency is minimized, while cpu utilization increases. for the two-interrupt method, frame latency becomes greater, while cpu utilization decreases. see figure a-3. note: some of the cpu time that can be applied to non-ethernet tasks is used for task switching in the cpu. one task switch is required to swap a non-ether- net task into the cpu (after s7a) and a second task switch is needed to swap the ethernet driver back in again (at s8a). if the time needed to perform these task switches exceeds the time saved by not polling descrip- tors, then there is a net loss in performance with this method. therefore, the lapp method implemented should be carefully chosen. figure a-4 shows the buffer sizing for the two-interrupt method. note that the second buffer size will be about the same for each method. there is another alternative which is a marriage of the two previous methods. this third possibility would use the buffer sizes set by the two-interrupt method, but would use the polling method of determining frame end. this will give good frame latency but at the price of very high cpu utilization. and still, there are even more compromise positions that use various fixed buffer sizes and, effectively, the flow of the one-inter- rupt method. all of these compromises will reduce the complexity of the one-interrupt method by removing the heuristic buffer sizing code, but they all become less ef- ficient than heuristic code would allow. a-9 am79c976 8/01/00 preliminary - <00 ! 8-'#+ buffer #3 buffer #2 buffer #1 ethernet wire activity: ethernet controller activity: software activity: s10: driver sets up tx descriptor. s9: application processes packet, generates tx packet. s8: driver calls application to tell application that packet has arrived. s7: driver is swapped out, allowing a non-ethernet application to run. s6: driver copies data from buffer #2 to the application buffer. s5: driver polls descriptor #2. s4: driver copies data from buffer #1 to the application buffer. s3: driver writes modified application pointer to descriptor #3. s2: driver call to application to get application buffer pointer. s1: interrupt latency. s0: driver is idle. } n2:eom n0: packet preamble, sfd and destination address are arriving. { packet data arriving } } } c9: controller writes descriptor #3. c8: controller is performing intermittent bursts of dma to fill data buffer #3. c7: controller writes descriptor #2. c6: "last chance" lookahead to descriptor #3 (own). c5: controller is performing intermittent bursts of dma to fill data buffer # 2 c3: srp interrupt is generated. c2: controller writes descriptor #1. c1: controller is performing intermittent bursts of dma to fill data buffer #1 . c0: lookahead to descriptor #2. n1: 64th byte of packet data arrives. c10: erp interrupt is generated. } s8a: interrupt latency. } s7a: driver interrupt service routine executes return. c4: lookahead to descriptor #3 (own). d-3 8/01/00 am79c976 a-10 preliminary -"<00 9' 8-'#+ descriptor #1 descriptor #2 descriptor #3 descriptor #4 descriptor #5 descriptor #6 descriptor #7 descriptor #8 descriptor #9 own = 1 stp = 1 size = header_size (minimum 64 bytes) own = 1 stp = 0 size = s1+s2+s3+s4 own = 0 stp = 0 size = 1518 - (s1+s2+s3+s4+header_size) own = 1 stp = 1 size = header_size (minimum 64 bytes) own = 1 stp = 0 size = s1+s2+s3+s4 own = 0 stp = 0 size = 1518 - (s1+s2+s3+s4+header_size) own = 1 stp = 1 size = header_size (minimum 64 bytes) own = 1 stp = 0 size = s1+s2+s3+s4 own = 0 stp = 0 size = 1518 - (s1+s2+s3+s4+header_size) a = expected message size in bytes s1 = interrupt latency s2 = application call latency s3 = time needed for driver to write to third descriptor s4 = time needed for driver to copy data from buffer #1 to application buffer space s6 = time needed for driver to copy data from buffer #2 to application buffer space note that the times needed for tasks s1, s2, s3, s4, and s6 should be divided by 0.8 microseconds to yield an equivalent number of network byte times before subtracting these quantities from the expected message size a. d-4 appendix b b - 1 ## ! appendix b: mii management registers as specified in the ieee standard, the basic register set consists of the control register (register 0) and the status register (register 1). the extended register set consists of registers 2 to 31 (decimal). all phys that provide an mii shall incorporate the basic register set. both sets of registers are accessible through the mii management interface. table 1 lists the most interesting registers. control register (register 0) table 2 shows the mii management control register (register 0). table b-1. mii management register set table b-2. mii management control register (register 0) 1 ' ()* () +"#*"# &+* register address register name basic/ extended 0mii control b 1 mii status b 2-3 phy identifier e 4 auto-negotiation advertisement e 5 auto-negotiation link partner ability e ! * ( ' : ; 15 soft reset when write: 1 = phy software reset 0 = normal operation when read: 1 = reset in process 0 = reset done r/w, sc 14 loopback 1 = enables loopback mode 0 = disables loopback mode r/w 13 speed selection 1 = 100 mbps 0 = 10 mbps r/w 12 auto-negotiation enable 1 = enable auto-negotiation 0 = disable auto-negotiation r/w 11 power down 1 = power down, 0 = normal operation r/w 10 isolate 1 = electrically isolate phy from mii 0 = normal operation r/w 9 restart auto-negotiation 1 = restart auto-negotiation 0 = normal operation r/w, sc 8 duplex mode 1 = full duplex 0 = half duplex r/w 7 collision test 1 = enable col signal test 0 = disable col signal test r/w 6-0 reserved write as 0, ignore on read ro 8/01/00 am79c976 b-2 preliminary status register (register 1) the mii management status register identifies the physical and auto-negotiation capabilities of the phy. this register is read only; a write will have no effect. see table 3. table b-3. mii management status register (register 1) 1 ' * +,-*, &-&+,,*, &, bits name description read/write (note 1) 15 100base-t4 1 = phy able to perform 100base-t4 0 = phy not able to perform 100base-t4 ro 14 100base-x full duplex 1 = phy able to perform full-duplex 100base-x 0 = phy not able to perform full-duplex 100base-x ro 13 100base-x half duplex 1 = phy able to perform half-duplex 100base-x 0 = phy not able to perform half-duplex 100base-x ro 12 10 mbps full duplex 1 = phy able to operate at 10 mbps full-duplex mode 0 = phy not able to operate at 10 mbps full-duplex mode ro 11 10 mbps half duplex 1 = phy able to operate at 10 mbps half-duplex mode 0 = phy not able to operate at 10 mbps half-duplex mode ro 10-7 reserved ignore when read ro 6 mf preamble suppression 1 = phy will accept management frames with preamble suppressed 0 = phy not able to accept management frames with preamble suppressed ro 5 auto-negotiation complete 1 = auto-negotiation process completed 0 = auto-negotiation process not completed ro 4 remote fault 1 = remote fault condition detected 0 = no remote fault condition detected ro, lh 3 auto-negotiation ability 1 = phy is able to perform auto-negotiation 0 = phy is not able to perform auto-negotiation ro 2link status 1 = link is up 0 = link is down ro, ll 1 jabber detect 1 = jabber condition detected 0 = no jabber condition detected ro 0 extended capability 1 = extended register capabilities 0 = basic register set capabilities only ro b-3 am79c976 8/01/00 preliminary auto-negotiation advertisement register (register 4) the purpose of this register is to advertise the technol- ogy ability to the link partner device. see table 4. when this register is modified, restart auto-negotia- tion (register 0, bit 9) must be enabled to guarantee the change is implemented. table b-4. auto-negotiation advertisement register (register 4) (+ $5 $ ! the technology bit field consists of bits a0-a8 in the ieee 802.3 selector base page. table 5 summarizes the bit assignments. table b-5. technology ability field bit assignments bit(s) name description read/ write 15 next page when set, the device wishes to engage in next page exchange. if clear, the device does not wish to engage in next page exchange r/w 14 reserved ignore when read ro 13 remote fault when set, a remote fault bit is inserted into the base link code word during the auto negotiation process. when cleared, the base link code word will have the bit position for remote fault as cleared r/w 12:5 technology ability technology ability field r/w 4:0 selector field selector field ro bit technology a0 10base-t a1 10base-t full duplex a2 100base-tx a3 100base-tx full duplex a4 100base-t4 a5 pause operation for full duplex links a6 reserved for future technology a7 reserved for future technology 8/01/00 am79c976 b-4 preliminary auto-negotiation link partner ability register (register 5) the auto-negotiation link partner ability register is read only. the register contains the advertised ability of the link partner. the bit definitions represent the re- ceived link code word. this register contains either the base page or the link partner ? s next pages. see table 6. table b-6. auto-negotiation link partner ability register (register 5) - base page format bit(s) name description read/ write 15 next page link partner next page request ro 14 acknowledge link partner acknowledgment ro 13 remote fault link partner remote fault request ro 12:5 technology ability link partner technology ability field ro 4:0 selector field link partner selector field ro index-1 am79c976 8/01/00 preliminary index numerics 16-bit software model . . . . . . . . . . . . . . . . . 62 3.3 vaux presence sense . . . . . . . . . . . . . . . .27 32-bit multiplexed bus interface unit . . . . . . . .3 32-bit software model . . . . . . . . . . . . . . . . .63 a absolute maximum ratings . . . . . . . . . . . .266 ad 24 address and data . . . . . . . . . . . . . . . . . . . . . .24 address match logic . . . . . . . . . . . . . . . . .227 address matching. . . . . . . . . . . . . . . . . . . . . 71 address parity error response . . . . . . . . . . .39 address prom space . . . . . . . . . . . . . . . . .107 analog power (1 pin) . . . . . . . . . . . . . . . . . .31 ap_value0 auto-poll value0 register . . . . . . . . . . . .122 ap_value1 auto-poll value1 register . . . . . . . . . . . .122 ap_value2 auto-poll value2 register . . . . . . . . . . . .123 ap_value3 auto-poll value3 register . . . . . . . . . . . .123 ap_value4 auto-poll value4 register . . . . . . . . . . . .123 ap_value5 auto-poll value5 register . . . . . . . . . . . .123 apdw values . . . . . . . . . . . . . . . . . . . . . . .218 automatic eeprom read operation . . . . . .96 automatic pad generation . . . . . . . . . . . . . . 69 automatic pad stripping . . . . . . . . . . . . . . . .72 automatic pread eeprom timing . . . .275 auto-negotiation . . . . . . . . . . . . . . . . . . . . . .85 auto-negotiation advertisement register (register 4) . . . . . . . . . . . . . . . . . . . . . . . . .b-3 auto-negotiation with multiple phy devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 auto-poll state machine . . . . . . . . . . . . . . . .84 autopoll0 auto-poll0 register . . . . . . . . . . . . . . . . .123 autopoll1 auto-poll1 register . . . . . . . . . . . . . . . . .124 autopoll2 auto-poll2 register . . . . . . . . . . . . . . . . .125 autopoll3 auto-poll3 register . . . . . . . . . . . . . . . . . 126 autopoll4 auto-poll4 register . . . . . . . . . . . . . . . . . 127 autopoll5 auto-poll5 register . . . . . . . . . . . . . . . . . 128 avdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 b basic burst read transfer . . . . . . . . . . . . . . . 41 basic burst write transfer . . . . . . . . . . . . . . 44 basic functions . . . . . . . . . . . . . . . . . . . . . . .32 basic non-burst read transfer . . . . . . . . . . 40 basic non-burst write transfer . . . . . . . . . . 42 bcr0 master mode read active . . . . . . . . . . . . 198 bcr1 master mode write active . . . . . . . . . . . 198 bcr16 i/o base address lower . . . . . . . . . . . . . 207 bcr19 eeprom control and status . . . . . . . . .209 bcr2 miscellaneous configuration . . . . . . . . . . 199 bcr20 software style . . . . . . . . . . . . . . . . . . . . . 212 bcr28 expansion bus port address lower (used for flash/eprom and sram accesses) . . . . . . . . . . . . . . . . . . . . . . . . . 216 bcr29 expansion port address upper (used for flash/eprom accesses) . . . . . 216 bcr30 expansion bus data port register . . . . . .217 bcr31 software timer register . . . . . . . . . . . . . 217 bcr32 mii control and status register . . . . . . . 217 bcr33 mii address register . . . . . . . . . . . . . . . . 219 bcr34 mii management data register . . . . . . . 220 bcr35 pci vendor id register . . . . . . . . . . . . . . 220 bcr36 pci power management capabilities 8/01/00 am79c976 index-2 preliminary bcr37 pci data register zero (data0) alias register . . . . . . . . . . . . . . . . . . . . . .221 bcr38 pci data register one (data1) alias register . . . . . . . . . . . . . . . . . . . . . .221 bcr39 pci data register two (data2) alias register . . . . . . . . . . . . . . . . . . . . . .221 bcr4 led 0 status . . . . . . . . . . . . . . . . . . . . . .199 bcr40 pci data register three (data3) alias register . . . . . . . . . . . . . . . . . . . . . .222 bcr41 pci data register four (data4) alias register . . . . . . . . . . . . . . . . . . . . . .222 bcr42 pci data register five (data5) alias register . . . . . . . . . . . . . . . . . . . . . .222 bcr43 pci data register six (data6) alias register . . . . . . . . . . . . . . . . . . . . . .223 bcr44 pci data register seven (data7) alias register . . . . . . . . . . . . . . . . . . . . . .223 bcr45 onnow pattern matching register #1 . . .223 bcr46 onnow pattern matching register #2 . . .224 bcr47 onnow pattern matching register #3 . . .224 bcr5 led1 status . . . . . . . . . . . . . . . . . . . . . . .201 bcr6 led2 status . . . . . . . . . . . . . . . . . . . . . . .203 bcr7 led3 status . . . . . . . . . . . . . . . . . . . . . . .205 bcr9 full-duplex control . . . . . . . . . . . . . . . . .207 block diagram . . . . . . . . . . . . . . . . . . . . . . . . .4 board interface . . . . . . . . . . . . . . . . . . . . . . . 26 boot rom chip select . . . . . . . . . . . . . . . . .29 boundary scan circuit . . . . . . . . . . . . . . . .103 boundary scan register . . . . . . . . . . . . . . .104 bsr mode of operation . . . . . . . . . . . . . . .104 buffer size tuning . . . . . . . . . . . . . . . . . . .a-7 burst write transfer . . . . . . . . . . . . . . . . . . .45 bus acquisition . . . . . . . . . . . . . . . . . . . .40, 41 bus command and byte enables . . . . . . . . .24 bus configuration registers . . . .197, 252, 264 bus grant . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 bus master dma transfers . . . . . . . . . . . . . 40 bus request . . . . . . . . . . . . . . . . . . . . . . . . . .25 c c/be . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 carrier sense . . . . . . . . . . . . . . . . . . . . . . . . 29 chipid chip id register . . . . . . . . . . . . . . . . . . . .129 chpolltime chain poll timer register 1 . . . . . . . . . . .29 clk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 clk waveform for 3.3 v signaling . . . . . . 272 clk waveform for 5 v signaling . . . . . . . 272 clksel1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 clksel2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 clock select 1 . . . . . . . . . . . . . . . . . . . . . . . .27 clock select 2 . . . . . . . . . . . . . . . . . . . . . . . .27 clock timing . . . . . . . . . . . . . . . . . . . . . . . .269 cmd0 command0 . . . . . . . . . . . . . . . . . . . . . . . . 130 cmd2 command2 . . . . . . . . . . . . . . . . . . . . . . . . 131 cmd3 command3 . . . . . . . . . . . . . . . . . . . . . . . . 135 cmd7 command7 . . . . . . . . . . . . . . . . . . . . . . . . 138 col . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 collision . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 collision handling . . . . . . . . . . . . . . . . . . . .68 command style access . . . . . . . . . . . . . . . . . 122 connection diagram (pqr208) . . . . . . . . . . 18 control and status registers . . . .173, 248, 262 control register (register 0) . . . . . . . . . . . b-1 crs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 csr0 controller status and control register . . 173 csr1 initialization block address 0 . . . . . . . . . 175 csr10 logical address filter 2 . . . . . . . . . . . . .184 csr100 bus timeout . . . . . . . . . . . . . . . . . . . . . . .193 csr101-111 reserved 1 . . . . . . . . . . . . . . . . . . . . . . . . 93 csr11 logical address filter 3 . . . . . . . . . . . . .184 index-3 am79c976 8/01/00 preliminary csr112 missed frame count . . . . . . . . . . . . . . . .193 csr113 reserved . . . . . . . . . . . . . . . . . . . . . . . . . .193 csr114 receive collision count . . . . . . . . . . . . .193 csr116 onnow power mode register . . . . . . . . .194 csr117-121 reserved . . . . . . . . . . . . . . . . . . . . . . . . . .195 csr12 physical address register 0 . . . . . . . . . .184 csr122 advanced feature control . . . . . . . . . . . .195 csr123 reserved . . . . . . . . . . . . . . . . . . . . . . . . . .195 csr124 test register 1 . . . . . . . . . . . . . . . . . . . . .195 csr125 mac enhanced configuration control . .196 csr13 physical address register 1 . . . . . . . . . .185 csr14 physical address register 2 . . . . . . . . . .185 csr15 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .185 csr16-23 reserved locations . . . . . . . . . . . . . . . . .186 csr2 initialization block address 1 . . . . . . . . .175 csr24 base address of receive ring lower . . .187 csr25 base address of receive ring upper . . .187 csr26-29 reserved . . . . . . . . . . . . . . . . . . . . . . . . . .187 csr3 interrupt masks and deferral control . . .175 csr30 base address of transmit ring lower . .187 csr31 base address of transmit ring upper . .187 csr32-46 reserved . . . . . . . . . . . . . . . . . . . . . . . . . .188 csr4 test and features control . . . . . . . . . . . .177 csr47 transmit polling interval . . . . . . . . . . . . .188 csr48 receive poll time counter . . . . . . . . . . . 188 csr49 receive polling interval . . . . . . . . . . . . . 188 csr5 extended control and interrupt 1 . . . . . . 179 csr50-57 reserved . . . . . . . . . . . . . . . . . . . . . . . . . 189 csr58 software style . . . . . . . . . . . . . . . . . . . . . 189 csr59-75 reserved . . . . . . . . . . . . . . . . . . . . . . . . . 191 csr6 rx/tx descriptor table length . . . . . . . 181 csr7 extended control and interrupt 2 . . . . . . 181 csr76 receive ring length . . . . . . . . . . . . . . . . 191 csr77 reserved . . . . . . . . . . . . . . . . . . . . . . . . . 191 csr78 transmit ring length . . . . . . . . . . . . . . .191 csr79 reserved . . . . . . . . . . . . . . . . . . . . . . . . . 191 csr8 logical address filter 0 . . . . . . . . . . . . .184 csr80 dma transfer counter and fifo threshold control . . . . . . . . . . . . . 191, 193 csr81-87 reserved . . . . . . . . . . . . . . . . . . . . . . . . . 193 csr88 chip id register lower . . . . . . . . . . . . . . 193 csr89 chip id register upper . . . . . . . . . . . . . . 193 csr9 logical address filter 1 1 . . . . . . . . . . . .84 csr90-99 reserved . . . . . . . . . . . . . . . . . . . . . . . . . 193 ctrl0 control0 register . . . . . . . . . . . . . . . . . . . 139 ctrl1 control1 register . . . . . . . . . . . . . . . . . . . 140 ctrl2 control2 register . . . . . . . . . . . . . . . . . . . 143 ctrl3 control3 register . . . . . . . . . . . . . . . . . . . 144 cycle frame . . . . . . . . . . . . . . . . . . . . . . . . . 24 8/01/00 am79c976 index-4 preliminary d datambist memory built-in self-test access register . . . . . . . . . . . . . . . . . . . . . . . . . .145 dc characteristics . . . . . . . . . . . . . . . . . . . .267 delayed_int delayed interrupts register . . . . . . . . . . .147 descriptor dma transfers . . . . . . . . . . . . . .52 descriptor management . . . . . . . . . . . . . . . .61 descriptor management unit . . . . . . . . . . . .59 descriptor ring read in burst mode . . . . . .54 descriptor ring read in non-burst mode . . . . . . . . . . . . . . . . . . . . . .53 descriptor ring write in burst mode . . . . . . . . . . . . . . . . . . . . . . . . . .57 descriptor ring write in non-burst mode . . . . . . . . . . . . . . . . . . . . . .56 descriptor rings . . . . . . . . . . . . . . . . . . . . . .61 destination address handling . . . . . . . . . . . .67 detailed functions . . . . . . . . . . . . . . . . . . . . .33 device select . . . . . . . . . . . . . . . . . . . . . . . . .24 devsel . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 digital and i/o buffer power (24 pins) . . . . .31 digital ground (8 pins) . . . . . . . . . . . . . . . . .31 digital i/o (non-pci pins) . . . . . . . . . . . . .267 direct access to the interface . . . . . . . . . . . .98 direct flash access . . . . . . . . . . . . . . . . . . . .94 disconnect of burst transfer . . . . . . . . . . . .38 disconnect of slave burst transfer - host inserts wait states . . . . . . . . . . . . . . .39 disconnect of slave burst transfer - no host wait states . . . . . . . . . . . . . . . . . .38 disconnect of slave cycle when busy . . . .38 disconnect when busy . . . . . . . . . . . . . . . . .37 disconnect with data transfer . . . . . . . .45, 46 disconnect without data transfer . . . . .46, 47 dma burst alignment . . . . . . . . . . . . . . . . .45 double word i/o mode . . . . . . . . . . . . . . . .108 dual-speed csma/cd . . . . . . . . . . . . . . . . . .2 e ear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 eecs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 eedet setting . . . . . . . . . . . . . . . . . . . . . .211 eedi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 eedo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 eeprom auto-detection . . . . . . . . . . . . . . .98 eeprom chip select . . . . . . . . . . . . . . . . . .28 eeprom crc calculation . . . . . . . . . . . . .98 eeprom data in . . . . . . . . . . . . . . . . . . . . . 28 eeprom data out . . . . . . . . . . . . . . . . . . . . 28 eeprom interface . . . . . . . . . . . . . . . . . . . . 28 eeprom programmable pin (phy_rst) . . .3 eeprom read functional timing . . . . . . .274 eeprom serial clock . . . . . . . . . . . . . . . . .28 eeprom timing . . . . . . . . . . . . . . . . . . . .274 eeprom_acc eeprom access register . . . . . . . . . . . 147 eesk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 era . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 eradsp/cen . . . . . . . . . . . . . . . . . . . . . . . . 29 eradv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 erce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 erclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 erd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 eroe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 error detection . . . . . . . . . . . . . . . . . . . . . . . 67 erwe/flwe . . . . . . . . . . . . . . . . . . . . . . . . 29 expansion bus interface . . . . . . . . . . . . . . . . 91 expansion rom - boot device access . . . . 92 expansion rom bus read sequence . . . . . . 93 expansion rom output enable . . . . . . . . . . 29 expansion rom transfers . . . . . . . . . . . . . . 37 external address detection interface. . . . 2, 30 external phy - mii @ 2.5 mhz . . . . . . . 281 external phy - mii @ 25 mhz . . . . . . . 281 receive frame tagging . . . . . . . . . . . . . . 91 external address detection interface (eadi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 external address reject . . . . . . . . . . . . . . . . 30 external clock input . . . . . . . . . . . . . . . . . . . 27 external memory address . . . . . . . . . . . . . . . 28 external memory address advance . . . . . . . 29 external memory address strobe . . . . . . . . . 29 external memory clock . . . . . . . . . . . . . . . . 29 external memory data . . . . . . . . . . . . . . . . . 29 external memory interface . . . . . . . . . . . . . . 28 external memory write enable . . . . . . . . . . 29 external ssram chip enable . . . . . . . . . . .29 external ssram output enable . . . . . . . . . . 29 f fifo burst write at end of unaligned buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 fifo burst write at start of unaligned buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 fifo dma transfers . . . . . . . . . . . . . . . . . . 57 fla . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 index-5 am79c976 8/01/00 preliminary flash read from expansion bus data port . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 flash/eprom read . . . . . . . . . . . . . . . . . . .94 flash_addr flash address register . . . . . . . . . . . . . .150 flash_data flash data register . . . . . . . . . . . . . . . . .150 flcs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 floe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 flow flow control register . . . . . . . . . . . . . . .151 flow, lapp . . . . . . . . . . . . . . . . . . . . . . . . .a-2 fmdc values . . . . . . . . . . . . . . . . . . . . . . .218 frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 frame format at the mii interface connection . . . . . . . . . . . . . . . . . . . . . . . . . . .83 framing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 full-duplex link status led support . . . . .81 full-duplex operation . . . . . . . . . . . . . . . . . .80 g general description . . . . . . . . . . . . . . . . . . . . 3 gnt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 h h_reset . . . . . . . . . . . . . . . . . . . . . . . . . .104 i i/o buffer ground (25 pins) . . . . . . . . . . . . .31 i/o map in dword i/o mode (dwio = 1) . . . . . . . . . . . . . . . . . . . . . . . . .109 i/o registers . . . . . . . . . . . . . . . . . . . . . . . .107 i/o resources . . . . . . . . . . . . . . . . . . . . . . .106 idsel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 ieee 1149.1 (1990) test access port interface . . . . . . . . . . . . . . . . . . . . . . . . .31, 103 ieee 1149.1 test access port interface (jtag) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 ieee 802.3 frame and length field transmission order . . . . . . . . . . . . . . . . . . . .73 ifs1 inter-frame spacing part 1 register . . . .152 initialization . . . . . . . . . . . . . . . . . . . . . . . . . .59 initialization block . . . . . . . . . . . . . . . . . . . 225 initialization block (ssize32 = 0) . . . . . . .225 initialization block (ssize32 = 1) . . . . . . .225 initialization block dma transfers . . . . . . .52 initialization device select . . . . . . . . . . . . . .24 initiator ready . . . . . . . . . . . . . . . . . . . . . . . .25 input setup and hold timing . . . . . . . . . . .272 instruction register and decoding logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 int0 interrupt0 . . . . . . . . . . . . . . . . . . . . . . . . . 153 inta . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 inten0 interrupt0 enable . . . . . . . . . . . . . . . . . . . 155 interface pin assignment . . . . . . . . . .149, 211 interrupt request . . . . . . . . . . . . . . . . . . . . . . 24 ipg inter-packet gap register . . . . . . . . . . . . 157 irdy 25 j jtag (ieee 1149.1) tck waveform for 5 v signaling . . . . . . . . . . . . . . . . . . . . . 276 jtag (ieee 1149.1) test signal timing . . . . . . . . . . . . . . . . . . . . . . . . .276, 277 k key to switching waveforms . . . . . . . . . . . 270 l lapp 3 buffer grouping . . . . . . . . . . . . . .a-5 lapp 3 buffer grouping for two-interrupt method . . . . . . . . . . . . . . . .a-10 lapp flow two-interrupt method . . . . . . . . . . . . . . . a-8 lapp timeline a-4 lapp timeline for two-interrupt method . . . . . . . . . . . . . . . . . . . . . . . . . . . . .a-9 late collision . . . . . . . . . . . . . . . . . . . . . . . .71 led control logic. . . . . . . . . . . . . . . . . . . . 99 led default configuration . . . . . . . . . . . . . . 99 led support . . . . . . . . . . . . . . . . . . . . . . . . . 98 led0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 led0 control register . . . . . . . . . . . . . . . . 158 led1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 led1 control register . . . . . . . . . . . . . . . . 159 led2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 led2 control register . . . . . . . . . . . . . . . . 159 led3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 led3 control register . . . . . . . . . . . . . . . . 159 legal i/o accesses in double word i/o mode (dwio =1) . . . . . . . . . . . . . . . . . 109 legal i/o accesses in word i/o mode (dwio = 0) . . . . . . . . . . . . . . . . . . . . . . . . . 109 logical address filter register . . . . . . . . . .157 look-ahead packet processing . . . . . . . . . . . . 2 8/01/00 am79c976 index-6 preliminary look-ahead packet processing (lapp) concept . . . . . . . . . . . . . . . . . . . . .a-1 loopback operation . . . . . . . . . . . . . . . . . . .80 loss of carrier . . . . . . . . . . . . . . . . . . . . . . . .71 m mac control pause frames . . . . . . . . . . . . .87 magic packet application . . . . . . . . . . . . . . . .3 management cycle timing . . . . . . . . . . . . .278 management data clock . . . . . . . . . . . . . . . .30 management data i/o . . . . . . . . . . . . . . . . . .30 management data output valid delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .280 management data setup and hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .280 master abort . . . . . . . . . . . . . . . . . . . . . .49, 51 master bus interface unit . . . . . . . . . . . . . . .40 master cycle data parity error response . . 52 master initiated termination . . . . . . . . . . . . .48 max_lat_a pci maximum latency alias register . .160 mdc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 mdc waveform . . . . . . . . . . . . . . . . . . . . .279 mdio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 media access control . . . . . . . . . . . . . . . . . .66 media access management . . . . . . . . . . . . . .67 media independent interface . . . . . . . . . .29, 81 media independent interface (mii) . . . . . .1, 22 medium allocation . . . . . . . . . . . . . . . . . . . .67 memory-mapped registers . . . . . . . . . . . . .122 mib offset . . . . . . . . . . . . . . . . . . . . . . . . . .122 mii management control register (register 0) . . . . . . . . . . . . . . . . . . . . . . . . .b-1 mii management frames . . . . . . . . . . . . . . .82 mii management interface . . . . . . . . . . . . . .82 mii management registers . . . . . . . . . . . . .b-1 mii network status interface . . . . . . . . . . . .82 mii receive frame tagging . . . . . . . . . . . . .91 mii receive interface . . . . . . . . . . . . . . . . . .81 mii transmit interface . . . . . . . . . . . . . . . . .81 min_gnt_a pci minimum grant alias register . . . .160 miscellaneous loopback features . . . . . . . .80 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226 n network interface . . . . . . . . . . . . . . . . . . . . .32 network port manager . . . . . . . . . . . . . . . . .85 non-burst read transfer . . . . . . . . . . . . . . .42 non-burst write transfer . . . . . . . . . . . . . . .44 normal and tri-state outputs . . . . . . . . . . . 271 o onnow functional diagram . . . . . . . . . . . . 100 onnow wake-up sequence . . . . . . . . . . . . 100 operating ranges . . . . . . . . . . . . . . . . . . . . 266 operation without mmi management interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 other data registers . . . . . . . . . . . . . . . . . . 104 outline of lapp flow . . . . . . . . . . . . . . . . .a-2 output and float delay timing . . . . . . . . . . 269 output tri-state delay timing . . . . . . . . . . 273 output valid delay timing . . . . . . . . . . . . . 273 p padr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 physical address register . . . . . . . . . . . . 160 pal function . . . . . . . . . . . . . . . . . . . . . . . . . . 3 par . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 parity error . . . . . . . . . . . . . . . . . . . . . . . . . . 25 parity error response . . . . . . . . . . . . . . .39, 51 pattern match ram . . . . . . . . . . . . . . . . . . 103 pause count register . . . . . . . . . . . . . . . . . . 161 pci base-class register offset 0bh . . . . . . 114 pci bus interface pins - 3.3 v signaling . . . . . . . . . . . . . . . . . . . . . .267 pci bus interface pins - 5 v signaling . . . . . . . . . . . . . . . . . . . . . . . .267 pci cache line size register offset 0ch . . . . . . . . . . . . . . . . . . . . . . . . . . 115 pci capabilities pointer register offset 34h . . . . . . . . . . . . . . . . . . . . . . . . . . 118 pci capability identifier register offset 44h . . . . . . . . . . . . . . . . . . . . . . . . . . 119 pci command register . . . . . . . . . . . . . . . . 111 pci command register offset 04h . . . . . . 111 pci configuration alias registers . . . . . . . 111 pci configuration registers 106, . . . .111, 245 pci configuration space layout . . . . . . . . 106 pci data register offset 4bh . . . . . . . . . . . 121 pci device id register offset 02h . . . . . . . 111 pci expansion rom base address register offset 30h . . . . . . . . . . . . 117 pci header type register offset 0eh . . . . 115 pci interface . . . . . . . . . . . . . . . . . . . . . . . . . 24 pci interrupt line register offset 3ch . . . . . . . . . . . . . . . . . . . . . . . . . . 118 pci interrupt pin register offset 3dh . . . . . . . . . . . . . . . . . . . . . . . . . . 118 index-7 am79c976 8/01/00 preliminary pci latency timer register offset 0dh . . . . . . . . . . . . . . . . . . . . . . . . . .115 pci max_lat register offset 3fh . . . . . . . . . . . . . . . . . . . . . . . . . .119 pci memory mapped i/o base address register offset 14h . . . . . . . . . . . . . . . . . . .116 pci min_gnt register offset 3eh . . . . . .118 pci next item pointer register offset 45h . . . . . . . . . . . . . . . . . . . . . . . . . .119 pci pmcsr bridge support extensions register offset 4ah . . . . . . . . . . . . . . . . . . .121 pci power management capabilities register (pmc) offset 46h . . . . . . . . . . . . .119 pci power management control/status register (pmcsr) offset 48h . . . . . . . . . . .120 pci programming interface register offset 09h . . . . . . . . . . . . . . . . . . . . . . . . . .114 pci revision id register offset 08h . . . . . . . . . . . . . . . . . . . . . . . . . .114 pci status register offset 06h . . . . . . . . . .113 pci sub-class register offset 0ah . . . . . .114 pci subsystem id register offset 2eh . . . . . . . . . . . . . . . . . . . . . . . . . .117 pci subsystem vendor id register offset 2ch . . . . . . . . . . . . . . . . . . . . . . . . . .116 pci vendor id register . . . . . . . . . . . . . . .111 pci vendor id register offset 00h . . . . . .111 pcidata0 pci data register zero alias register . . . . . . . . . . . . . . . . . . . . . . . . . .161 pcidata1 pci data register one alias register . . . . . . . . . . . . . . . . . . . . . . . . . .161 pcidata2 pci data register two alias register . . . . . . . . . . . . . . . . . . . . . . . . . .162 pcidata3 pci data register three alias register . . . . . . . . . . . . . . . . . . . . . . . . . .162 pcidata4 pci data register four alias register . . . . . . . . . . . . . . . . . . . . . . . . . .162 pcidata5 pci data register five alias register . . . . . . . . . . . . . . . . . . . . . . . . . .162 pcidata6 pci data register six alias register . . . . . . . . . . . . . . . . . . . . . . . . . .162 pcidata7 pci data register seven alias register . . . . . . . . . . . . . . . . . . . . . . . . . .162 peripheral component interconnect (pci) bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 perr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 pg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 phy access register . . . . . . . . . . . . . . . . . 163 phy reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 phy_rst . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 physical dimensions . . . . . . . . . . . . . . . . . . 285 pin capacitance . . . . . . . . . . . . . . . . . . . . . . 267 pin descriptions . . . . . . . . . . . . . . . . . . . . . . 24 pin designations by group . . . . . . . . . . . . . . 21 pin designations by pin number (pqr208) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 pmat0 onnow pattern register 0 . . . . . . . . . . . . 164 pmat1 onnow pattern register1 . . . . . . . . . . . . 164 pmc_a pci power management capabilities alias register . . . . . . . . . . . . . . . . . . . . . .165 pme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 power good . . . . . . . . . . . . . . . . . . . . . . . . . . 26 power management event . . . . . . . . . . . . . . . 26 power management interface . . . . . . . . . . . . 22 power management support . . . . . . . . . . . . . 99 power on reset . . . . . . . . . . . . . . . . . . . . . . 105 power savings mode . . . . . . . . . . . . . . . . . . . 99 power supplies . . . . . . . . . . . . . . . . . . . . . . .23 power supply current . . . . . . . . . . . . . . . . . 268 power supply pins . . . . . . . . . . . . . . . . . . . . .31 pqr208 plastic quad flat pack (measured in millimeters) . . . . . . . . . . . . . .285 preemption during burst transaction . . .48, 50 preemption during non-burst transaction . . . . . . . . . . . . . . . . . . . . . . .48, 49 programmable inter packet gap (ipg) . . . . . . 2 programmable registers . . . . . . . . . . . . . . . 262 r rap register address port . . . . . . . . . . . . . . . 172 rap register . . . . . . . . . . . . . . . . . . . . . . . . 172 rcv_ring_len receive ring length register . . . . . . . . . 165 rdra and tdra . . . . . . . . . . . . . . . . . . . . 226 receive address match . . . . . . . . . . . . . . . . . 72 8/01/00 am79c976 index-8 preliminary receive clock . . . . . . . . . . . . . . . . . . . . . . . .30 receive data . . . . . . . . . . . . . . . . . . . . . . . . .30 receive data valid 30 receive descriptor (swstyle = 0) . . . . .227 receive descriptor (swstyle = 2) . . . . .227 receive descriptor (swstyle = 3) . . . . .228 receive descriptor (swstyle = 4) . . . . .228 receive descriptor (swstyle = 5) . . . . .228 receive descriptors . . . . . . . . . . . . . . . . . . .227 receive error . . . . . . . . . . . . . . . . . . . . . . . . .30 receive exception conditions . . . . . . . . . . .73 receive fcs checking . . . . . . . . . . . . . . . . .73 receive frame tag data . . . . . . . . . . . . . . . .31 receive frame tag enable . . . . . . . . . . . . . .31 receive frame tag timing with media independent interface . . . . . . . .281, 283 receive function programming . . . . . . . . . .71 receive operation . . . . . . . . . . . . . . . . . . . . .71 receive polling . . . . . . . . . . . . . . . . . . . . . . .65 receive protect register . . . . . . . . . . . . . . .165 receive ring base address register . . . . .128 receive timing . . . . . . . . . . . . . . . . . .278, 279 receive watermark programming . . . . . . .192 register bit cross reference . . . . . . . . . . . .253 register initialization . . . . . . . . . . . . . . . . . .111 register programming summary . . . . . . . .262 register summary . . . . . . . . . . . . . . . . . . . .245 regulating network traffic . . . . . . . . . . . . .87 re-initialization . . . . . . . . . . . . . . . . . . . . . . .59 reject timing - external phy mii @ 2.5 mhz . . . . . . . . . . . . . . . . . . . . . . . . .282 reject timing - external phy mii @ 25 mhz . . . . . . . . . . . . . . . . . . . . . . . . . .281 remote wake up . . . . . . . . . . . . . . . . . . . . .26 req . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 reset register . . . . . . . . . . . . . . . . . . . . . . .107 rlen and tlen . . . . . . . . . . . . . . . . . . . . .225 rom_cfg rom base address configuration register . . . . . . . . . . . . . . . . . . . . . . . . . .166 rst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 run and suspend . . . . . . . . . . . . . . . . . . . . . .60 running registers . . . . . . . . . . . . . . . . . . . . .111 rwu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 rx_clk . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 rx_dv . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 rx_er . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 rxd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 rxfrtgd . . . . . . . . . . . . . . . . . . . . . . . . . . 31 rxfrtge . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 s s_reset . . . . . . . . . . . . . . . . . . . . . . . . . . .105 serr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .a-2 setup and hold timing . . . . . . . . . . . . . . . . 269 setup registers . . . . . . . . . . . . . . . . . . . . . . . 111 sfbd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 sid_a pci subsystem id alias register . . . . . .166 slave bus interface unit . . . . . . . . . . . . . . . . 33 slave configuration read . . . . . . . . . . . . . . 34 slave configuration transfers . . . . . . . . . . . . 33 slave configuration write . . . . . . . . . . . . . . . 34 slave cycle data parity error response . . . . 40 slave i/o transfers . . . . . . . . . . . . . . . . . . . . 33 slave read using i/o command . . . . . . . . . 35 slave write using memory command . . . . . 36 software . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 software access . . . . . . . . . . . . . . . . . . . . . 106 software interface . . . . . . . . . . . . . . . . . . . . . 32 software interrupt timer . . . . . . . . . . . . . . . . 66 software timer value register . . . . . . . . . . 169 some examples of lapp descriptor interaction . . . . . . . . . . . . . . . . . . . . . . . . . .a-6 sr2 initialization block address 1 . . . . . . . . . 175 sram boundary register . . . . . . . . . . . . . . 167 sram configuration . . . . . . . . . . . . . . . . . . 95 sram size register . . . . . . . . . . . . . . . . . .167 start frame-byte delimiter . . . . . . . . . . . . . .30 stat0 status0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 status register (register 1) . . . . . . . . . . . . . b-2 stop . . . . . . . . . . . . . . . . . . . . . . . . . . .25, 105 stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 supported instructions . . . . . . . . . . . . . . . . . 103 svid_a pci subsystem vendor id alias register . . . . . . . . . . . . . . . . . . . . . . . . . .170 switching characteristics bus interface . . . . . . . . . . . . . . . . . . . . . . 269 eeprom interface . . . . . . . . . . . . . . . . . 274 external address detection interface . . . . . . . . . . . . . . . . . . . . 281, 282 jtag timing . . . . . . . . . . . . . . . . . . . . . . 276 media independent interface . . . . . . . . . . 278 switching test circuits . . . . . . . . . . . . . . . .271 index-9 am79c976 8/01/00 preliminary switching waveforms . . . . . . . . . . . . . . . . .270 expansion bus interface . . . . . . . . . . . . .284 receive frame tag . . . . . . . . . . . . . . . . .283 system bus interface . . . . . . . . . . . . . . . . . . .32 system error . . . . . . . . . . . . . . . . . . . . . . . . .25 t tap finite state machine . . . . . . . . . . . . . .103 target abort . . . . . . . . . . . . . . . . . . . . . .47, 48 target initiated termination. . . . . . . . . . . . . 45 target ready . . . . . . . . . . . . . . . . . . . . . . . . .25 tck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 tdi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 tdo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 technology ability field bit assignments . . . . . . . . . . . . . . . . . . . . . . . .b-3 test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 test clock . . . . . . . . . . . . . . . . . . . . . . . . . . .31 test data in . . . . . . . . . . . . . . . . . . . . . . . . . .31 test data out . . . . . . . . . . . . . . . . . . . . . . . . .31 test mode select . . . . . . . . . . . . . . . . . . . . . .31 test reset . . . . . . . . . . . . . . . . . . . . . . . . . . .27 tms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 transmit and receive message data encapsulation . . . . . . . . . . . . . . . . . . . . . . . .66 transmit clock . . . . . . . . . . . . . . . . . . . . . . .29 transmit data . . . . . . . . . . . . . . . . . . . . . . . .29 transmit descriptors . . . . . . . . . . . . . . . . . .238 transmit enable . . . . . . . . . . . . . . . . . . . . . . .29 transmit error conditions . . . . . . . . . . . . . . .70 transmit fcs generation . . . . . . . . . . . . . . .70 transmit function programming . . . . . . . . .69 transmit operation . . . . . . . . . . . . . . . . . . . .69 transmit polling . . . . . . . . . . . . . . . . . . . . . .64 transmit ring base address register . . . . .129 transmit start point programming . . . . . . .192 transmit timing . . . . . . . . . . . . .278, 279, 284 transmit watermark programming . . . . . . .192 trdy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 tx_clk . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 tx_en . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 txd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 u user accessible registers . . . . . . . . . . . . . . 111 v vaux_sense . . . . . . . . . . . . . . . . . . . . . . . 27 vdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 vid_a pci vendor id alias register . . . . . . . . . 171 vlan support . . . . . . . . . . . . . . . . . . . . . . . 78 vss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 vssb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 w wake-up mode indicator . . . . . . . . . . . . . . . 27 word i/o mode . . . . . . . . . . . . . . . . . . . . . . 108 wumi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 x xclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 xmt_ring_len transmit ring length register . . . . . . . .171 xmtpolltime transmit poll timer register . . . . . . . . .171 xtal1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 xtal2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8/01/00 am79c976 index-10 preliminary the contents of this document are provided in connection with advanced micro devices, inc. ( ? amd ? ) products. amd makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. no license, whether express, impli ed, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. except as set forth in am d ? s standard terms and conditions of sale, amd assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpo se, or infringement of any intellectual property right. amd ? s products are not designed, intended, authorized or warranted for use as components in systems intended for surgical im- plant into the body, or in other applications intended to support or sustain life, or in any other application in which the fai lure of amd ? s product could create a situation where personal injury, death, or severe property or environmental damage may occur. amd reserves the right to discontinue or make changes to its products at any time without notice. 7udghpdunv copyright 1999, 2000 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are registered trademarks of advanced micro devices, inc. alertit, any1home, eimr, eimr+, gigaphy, himib, homephy, imr2, mace, magic packet, netphy, pcnet, pcnet-home, quest, and quiet are trademarks of advanced micro devices, inc. rll25 is a trademark of tut systems, inc. other product names used in this publication are for identification purposes only and may be trademarks of their respective com panies. 22929c |
Price & Availability of AM79C976KCW
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |